[Lldb-commits] [lldb] [lldb] add RISCV target specific info in API tests (PR #99039)

[David Spickett via lldb-commits]

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@@ -34,6 +34,8 @@ def check_first_register_readable(test_case):
         test_case.expect("register read r0", substrs=["r0 = 0x"])
     elif arch in ["powerpc64le"]:
         test_case.expect("register read r0", substrs=["r0 = 0x"])
+    elif arch in ["rv64gc"]:
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DavidSpickett wrote:

Curious here what ` test_case.getArchitecture()` returns, is it exactly this string?

I just remember that riscv can be configured all sorts of ways and I don't know if that ends up in this string.

This is fine for this patch though, folks will find this code easily enough if it's a problem for them.

https://github.com/llvm/llvm-project/pull/99039