[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

[David Spickett via lldb-commits]

================
@@ -0,0 +1,84 @@
+//===-- RegisterContextPOSIXCore_riscv64.cpp ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextPOSIXCore_riscv64.h"
+
+#include "lldb/Utility/DataBufferHeap.h"
+
+using namespace lldb_private;
+
+std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+RegisterContextCorePOSIX_riscv64::Create(
+    lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+    const lldb_private::DataExtractor &gpregset,
+    llvm::ArrayRef<lldb_private::CoreNote> notes) {
+  Flags flags = 0;
+
+  auto register_info_up =
+      std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags);
+  return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
+      new RegisterContextCorePOSIX_riscv64(thread, std::move(register_info_up),
+                                           gpregset, notes));
+}
+
+RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
+    Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+    const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
+    : RegisterContextPOSIX_riscv64(thread, std::move(register_info)) {
+
+  m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+                                                  gpregset.GetByteSize());
+  m_gpr.SetData(m_gpr_buffer);
+  m_gpr.SetByteOrder(gpregset.GetByteOrder());
+
+  ArchSpec arch = m_register_info_up->GetTargetArchitecture();
+  DataExtractor fpregset = getRegset(notes, arch.GetTriple(), FPR_Desc);
+  m_fpr_buffer = std::make_shared<DataBufferHeap>(fpregset.GetDataStart(),
----------------
DavidSpickett wrote:

For obvious reasons, not a RISC-V expert, but Debian chose RV64GC (https://wiki.debian.org/RISC-V#Hardware_baseline_and_ABI_choice) which apparently converts to `RV64IMAFDCZicsr_Zifencei` and `F` is single precision floating point.

So I agree, it's reasonable for lldb to assume they exist. Certainly not a concern for this PR.

https://github.com/llvm/llvm-project/pull/93297