[Lldb-commits] [lldb] 772f296 - [lldb][AArch64][Linux] Correct name of FPCR field

[David Spickett via lldb-commits]

Author: David Spickett
Date: 2023-11-27T09:10:56Z
New Revision: 772f296214e10323ca16921c02b1852307b7d51b

URL: https://github.com/llvm/llvm-project/commit/772f296214e10323ca16921c02b1852307b7d51b
DIFF: https://github.com/llvm/llvm-project/commit/772f296214e10323ca16921c02b1852307b7d51b.diff

LOG: [lldb][AArch64][Linux] Correct name of FPCR field

It should be "RMode" as in "rounding mode" not "RMMode".

Added: 
    

Modified: 
    lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp
    lldb/test/API/commands/register/register/register_command/TestRegisters.py
    lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

Removed: 
    


################################################################################
diff  --git a/lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp
index 77c7116d3c624ae..51553817921f350 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp
@@ -53,7 +53,7 @@ LinuxArm64RegisterFlags::DetectMTECtrlFields(uint64_t hwcap, uint64_t hwcap2) {
 LinuxArm64RegisterFlags::Fields
 LinuxArm64RegisterFlags::DetectFPCRFields(uint64_t hwcap, uint64_t hwcap2) {
   std::vector<RegisterFlags::Field> fpcr_fields{
-      {"AHP", 26}, {"DN", 25}, {"FZ", 24}, {"RMMode", 22, 23},
+      {"AHP", 26}, {"DN", 25}, {"FZ", 24}, {"RMode", 22, 23},
       // Bits 21-20 are "Stride" which is unused in AArch64 state.
   };
 

diff  --git a/lldb/test/API/commands/register/register/register_command/TestRegisters.py b/lldb/test/API/commands/register/register/register_command/TestRegisters.py
index 386991c18db7c8c..5c4f3a4bb374c26 100644
--- a/lldb/test/API/commands/register/register/register_command/TestRegisters.py
+++ b/lldb/test/API/commands/register/register/register_command/TestRegisters.py
@@ -630,9 +630,9 @@ def test_register_read_fields(self):
         # N/Z/C/V bits will always be present, so check only for those.
         self.expect("register read cpsr", substrs=["= (N = 0, Z = 1, C = 1, V = 0"])
         self.expect("register read fpsr", substrs=["= (QC = 0, IDC = 0, IXC = 0"])
-        # AHP/DN/FZ/RMMode always present, others may vary.
+        # AHP/DN/FZ/RMode always present, others may vary.
         self.expect(
-            "register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMMode = 0"]
+            "register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMode = 0"]
         )
 
     @skipUnlessPlatform(["linux"])

diff  --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 58f104eb49de245..d6907075820ece7 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -578,9 +578,9 @@ def test_aarch64_sve_regs_full(self):
         # The N/Z/C/V bits are always present so just check for those.
         self.expect("register read cpsr", substrs=["= (N = 0, Z = 0, C = 0, V = 0"])
         self.expect("register read fpsr", substrs=["= (QC = 0, IDC = 0, IXC = 0"])
-        # AHP/DN/FZ/RMMode always present, others may vary.
+        # AHP/DN/FZ/RMode always present, others may vary.
         self.expect(
-            "register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMMode = 0"]
+            "register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMode = 0"]
         )
 
     @skipIfLLVMTargetMissing("AArch64")