[Lldb-commits] [lldb] [lldb][AArch64] Add isAArch64SMEFA64 check to SME testing (PR #68094)

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``````````bash
darker --check --diff -r 9a408588d1b8b7899eff593c537de539a4a12651..3816b0fbc31825d3878b031a49fb78dd7c256278 lldb/packages/Python/lldbsuite/test/lldbtest.py lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
``````````

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View the diff from darker here.
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``````````diff
--- test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py	2023-10-03 12:14:52.000000 +0000
+++ test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py	2023-10-03 12:28:00.613685 +0000
@@ -107,12 +107,14 @@
     def run_sve_test(self, mode):
         if (mode == Mode.SVE) and not self.isAArch64SVE():
             self.skipTest("SVE registers must be supported.")
 
         if (mode == Mode.SSVE) and not self.isAArch64SMEFA64():
-            self.skipTest("Streaming SVE registers must be supported and the "
-                          "smefa64 extension must be present.")
+            self.skipTest(
+                "Streaming SVE registers must be supported and the "
+                "smefa64 extension must be present."
+            )
 
         self.build_for_mode(mode)
 
         supported_vg = self.get_supported_vg()
 
@@ -201,12 +203,14 @@
         self.run_sve_test(Mode.SSVE)
 
     def setup_svg_test(self, mode):
         # Even when running in SVE mode, we need access to SVG for these tests.
         if not self.isAArch64SMEFA64():
-            self.skipTest("Streaming SVE registers must be present and the "
-                          "smefa64 extension must be present.")
+            self.skipTest(
+                "Streaming SVE registers must be present and the "
+                "smefa64 extension must be present."
+            )
 
         self.build_for_mode(mode)
 
         supported_vg = self.get_supported_vg()
 
--- test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py	2023-10-03 12:14:52.000000 +0000
+++ test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py	2023-10-03 12:28:00.718448 +0000
@@ -84,12 +84,14 @@
     def skip_if_needed(self, mode):
         if (mode == Mode.SVE) and not self.isAArch64SVE():
             self.skipTest("SVE registers must be supported.")
 
         if (mode == Mode.SSVE) and not self.isAArch64SMEFA64():
-            self.skipTest("SSVE registers must be supported and the smefa64 "
-                          "extension must be present.")
+            self.skipTest(
+                "SSVE registers must be supported and the smefa64 "
+                "extension must be present."
+            )
 
     def sve_registers_configuration_impl(self, mode):
         self.skip_if_needed(mode)
 
         self.build(dictionary=self.get_build_flags(mode))
--- test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py	2023-10-03 12:14:52.000000 +0000
+++ test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py	2023-10-03 12:28:00.774799 +0000
@@ -40,12 +40,14 @@
     def skip_if_needed(self, mode):
         if (mode == Mode.SVE) and not self.isAArch64SVE():
             self.skipTest("SVE registers must be supported.")
 
         if (mode == Mode.SSVE) and not self.isAArch64SMEFA64():
-            self.skipTest("SSVE registers must be supported and the smefa64 "
-                          "extension must be present.")
+            self.skipTest(
+                "SSVE registers must be supported and the smefa64 "
+                "extension must be present."
+            )
 
     def make_simd_value(self, n):
         pad = " ".join(["0x00"] * 7)
         return "{{0x{:02x} {} 0x{:02x} {}}}".format(n, pad, n, pad)
 

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https://github.com/llvm/llvm-project/pull/68094