[Lldb-commits] [PATCH] D157846: [lldb][AArch64] Add SME's tests for SVE register state to TestArm64DynamicRegsets

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added a comment.

> I was actually curious if LLDB user can distinguish whether we are reading SVE registers from streaming mode or normal SVE mode. But yes only config registers like vg can tell that registers are read in non-SVE(FPSIMD), normal SVE, or streaming modes.

Right, good point and yes they can but not until https://reviews.llvm.org/D154927. In that I also update the tests to check that svcr has the correct value for the expected mode the test is running in.

They'll be able to check SVCR.SM (bit 0) to know if they are in streaming mode (which will eventually be nicely printed `M = 1` but that's unrelated to this series).

They can also see if SVG and VG match, but vector lengths can overlap so this won't always work, so SVCR is the official way to do it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157846/new/

https://reviews.llvm.org/D157846