[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added a comment.

> I am talking to our kernel folks to understand the background to that.

The result is that yes cores an implement it as separate state but as mentioned here, taking that into account in lldb would be rather confusing in 99% of situations. If we simply want to read what instructions in the current context will see, using the bottom 128 bits of the Z registers is fine.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155269/new/

https://reviews.llvm.org/D155269