[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added a comment.

> As a simplification of all of this, and to avoid using g/G, we added QSaveRegisterState which tells the stub (debugserver etc) to save the current register context, and then after the inferior function call has completed, QRestoreRegisterState to restore them all.

Looks like we do support that in lldb-server, I just hadn't come across it because I've been down at the native process level. I've updated `ReadAllRegisterValues` down there so it will restore to whatever the saved mode was.

> In the process of restoring / writing the registers, I expect we will try to write the floating point register contents into the process which would drop it out of SSVE mode?

Right, yes it would if we follow this statement from the kernel docs:

  Note that when SME is present and streaming SVE mode is in use the FPSIMD subset of registers will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode in the target.

I am talking to our kernel folks to understand the background to that. I suspect that it may be the case that for example, writing to the bottom 128 bits of streaming mode z0 may not be reflected in the SIMD unit's v0. Or at least, one could build a core that acted that way.


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  https://reviews.llvm.org/D155269/new/

https://reviews.llvm.org/D155269