[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

[Jason Molenda via Phabricator via lldb-commits]

jasonmolenda added a comment.

Just curious -- would it be better to have a single `vg` register shown to the user which is the vector length in non-streaming mode when the processor is in non-streaming mode, and the vector length in streaming mode when the processor is in streaming mode? I haven't worked with a target supporting SSVE mode, but if I'm following correctly we can show the SVE registers in non-streaming mode (and vg) and we can show the SSVE registers in streaming mode (and svg).  As you say above, we can show svg when in non-streaming mode but we can't show vg when in streaming mode.  Should we only show a single vg for the currently-available registers?


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  https://reviews.llvm.org/D155269/new/

https://reviews.llvm.org/D155269