[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

Tue Jul 11 23:20:43 PDT 2023

DavidSpickett added a comment.

> You mention a couple of times that when in SSVE mode, we can only write to the SVE registers and doing so forces the processor out of SSVE Mode. We can read the SSVE registers while in SSVE mode though right?

We are always able to read the header for either mode, which tells us the vector length among other useful metadata. Register data though...

Maybe I should just enumerate the states.

Write to SVE while in SSVE - switch to SVE mode
Write to SSVE while in SVE - switch to SSVE mode
Write to SVE while in SVE - no change
Write to SSVE while in SSVE - no change

Read SVE while in SSVE - no register data returned
Read SSVE while in SVE - no register data returned
Read SSVE while in SSVE - SSVE registers returned
Read SVE while in SVE - SVE registers returned

Then we have SIMD (v0-31) which is a bit of a wrench in this. We must read SIMD via the SVE regset even while SSVE is active, but writing to that same set brings us out of SSVE mode (into SIMD mode, I think, but it could just be SVE mode).

So perhaps you see from that why I don't plan to use the mode switching this way in lldb.

I will in follow on patches report the current mode via a pseudo control register, and report the streaming vector length again with a pseudo. To resolve the ambiguity of naming the registers the same thing.

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D154926