[Lldb-commits] [lldb] 247714f - [LLDB] Move MIPS64/PPC64 and misc. to optional GetRegisterInfo
David Spickett via lldb-commits
lldb-commits at lists.llvm.org
Wed Sep 28 03:36:41 PDT 2022
Author: David Spickett
Date: 2022-09-28T10:36:31Z
New Revision: 247714f0a6307307ac9a972d4828cfb5f8b45f4b
URL: https://github.com/llvm/llvm-project/commit/247714f0a6307307ac9a972d4828cfb5f8b45f4b
DIFF: https://github.com/llvm/llvm-project/commit/247714f0a6307307ac9a972d4828cfb5f8b45f4b.diff
LOG: [LLDB] Move MIPS64/PPC64 and misc. to optional GetRegisterInfo
Depends on D134536
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134537
Added:
Modified:
lldb/source/Core/EmulateInstruction.cpp
lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
Removed:
################################################################################
diff --git a/lldb/source/Core/EmulateInstruction.cpp b/lldb/source/Core/EmulateInstruction.cpp
index 271301b9d3831..b175cfcc59af4 100644
--- a/lldb/source/Core/EmulateInstruction.cpp
+++ b/lldb/source/Core/EmulateInstruction.cpp
@@ -82,9 +82,9 @@ bool EmulateInstruction::ReadRegister(const RegisterInfo *reg_info,
bool EmulateInstruction::ReadRegister(lldb::RegisterKind reg_kind,
uint32_t reg_num,
RegisterValue ®_value) {
- RegisterInfo reg_info;
- if (GetRegisterInfo(reg_kind, reg_num, reg_info))
- return ReadRegister(®_info, reg_value);
+ llvm::Optional<RegisterInfo> reg_info = GetRegisterInfo(reg_kind, reg_num);
+ if (reg_info)
+ return ReadRegister(&(*reg_info), reg_value);
return false;
}
@@ -123,9 +123,9 @@ bool EmulateInstruction::WriteRegister(const Context &context,
lldb::RegisterKind reg_kind,
uint32_t reg_num,
const RegisterValue ®_value) {
- RegisterInfo reg_info;
- if (GetRegisterInfo(reg_kind, reg_num, reg_info))
- return WriteRegister(context, ®_info, reg_value);
+ llvm::Optional<RegisterInfo> reg_info = GetRegisterInfo(reg_kind, reg_num);
+ if (reg_info)
+ return WriteRegister(context, &(*reg_info), reg_value);
return false;
}
@@ -133,11 +133,11 @@ bool EmulateInstruction::WriteRegisterUnsigned(const Context &context,
lldb::RegisterKind reg_kind,
uint32_t reg_num,
uint64_t uint_value) {
- RegisterInfo reg_info;
- if (GetRegisterInfo(reg_kind, reg_num, reg_info)) {
+ llvm::Optional<RegisterInfo> reg_info = GetRegisterInfo(reg_kind, reg_num);
+ if (reg_info) {
RegisterValue reg_value;
- if (reg_value.SetUInt(uint_value, reg_info.byte_size))
- return WriteRegister(context, ®_info, reg_value);
+ if (reg_value.SetUInt(uint_value, reg_info->byte_size))
+ return WriteRegister(context, &(*reg_info), reg_value);
}
return false;
}
diff --git a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
index 341d954e74be6..14041c7e69e94 100644
--- a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -1098,10 +1098,10 @@ bool EmulateInstructionMIPS64::Emulate_DADDiu(llvm::MCInst &insn) {
* Assume 2's complement and rely on unsigned overflow here.
*/
uint64_t result = src_opd_val + imm;
- RegisterInfo reg_info_sp;
-
- if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
- context.SetRegisterPlusOffset(reg_info_sp, imm);
+ llvm::Optional<RegisterInfo> reg_info_sp =
+ GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64);
+ if (reg_info_sp)
+ context.SetRegisterPlusOffset(*reg_info_sp, imm);
/* We are allocating bytes on stack */
context.type = eContextAdjustStackPointer;
@@ -1125,8 +1125,6 @@ bool EmulateInstructionMIPS64::Emulate_DADDiu(llvm::MCInst &insn) {
bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) {
uint64_t address;
- RegisterInfo reg_info_base;
- RegisterInfo reg_info_src;
bool success = false;
uint32_t imm16 = insn.getOperand(2).getImm();
uint64_t imm = SignedBits(imm16, 15, 0);
@@ -1136,10 +1134,11 @@ bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) {
src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
- if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base,
- reg_info_base) ||
- !GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src,
- reg_info_src))
+ llvm::Optional<RegisterInfo> reg_info_base =
+ GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base);
+ llvm::Optional<RegisterInfo> reg_info_src =
+ GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src);
+ if (!reg_info_base || !reg_info_src)
return false;
/* read SP */
@@ -1156,19 +1155,20 @@ bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) {
Context context;
RegisterValue data_src;
context.type = eContextPushRegisterOnStack;
- context.SetRegisterToRegisterPlusOffset(reg_info_src, reg_info_base, 0);
+ context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
Status error;
- if (!ReadRegister(®_info_base, data_src))
+ if (!ReadRegister(&(*reg_info_base), data_src))
return false;
- if (data_src.GetAsMemoryData(®_info_src, buffer, reg_info_src.byte_size,
- eByteOrderLittle, error) == 0)
+ if (data_src.GetAsMemoryData(&(*reg_info_src), buffer,
+ reg_info_src->byte_size, eByteOrderLittle,
+ error) == 0)
return false;
- if (!WriteMemory(context, address, buffer, reg_info_src.byte_size))
+ if (!WriteMemory(context, address, buffer, reg_info_src->byte_size))
return false;
}
@@ -1190,9 +1190,7 @@ bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
imm = insn.getOperand(2).getImm();
- RegisterInfo reg_info_base;
- if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base,
- reg_info_base))
+ if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base))
return false;
/* read base register */
@@ -1211,16 +1209,15 @@ bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
if (nonvolatile_reg_p(src)) {
RegisterValue data_src;
- RegisterInfo reg_info_src;
-
- if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src,
- reg_info_src))
+ llvm::Optional<RegisterInfo> reg_info_src =
+ GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src);
+ if (!reg_info_src)
return false;
Context context;
context.type = eContextRegisterLoad;
- return WriteRegister(context, ®_info_src, data_src);
+ return WriteRegister(context, &(*reg_info_src), data_src);
}
return false;
@@ -1279,9 +1276,10 @@ bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) {
result = src_opd_val + rt_opd_val;
Context context;
- RegisterInfo reg_info_sp;
- if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
- context.SetRegisterPlusOffset(reg_info_sp, rt_opd_val);
+ llvm::Optional<RegisterInfo> reg_info_sp =
+ GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64);
+ if (reg_info_sp)
+ context.SetRegisterPlusOffset(*reg_info_sp, rt_opd_val);
/* We are allocating bytes on stack */
context.type = eContextAdjustStackPointer;
@@ -2307,9 +2305,7 @@ bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) {
m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
imm = insn.getOperand(num_operands - 1).getImm();
- RegisterInfo reg_info_base;
- if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
- reg_info_base))
+ if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
return false;
/* read base register */
@@ -2341,13 +2337,10 @@ bool EmulateInstructionMIPS64::Emulate_LDST_Reg(llvm::MCInst &insn) {
index =
m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());
- RegisterInfo reg_info_base, reg_info_index;
- if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
- reg_info_base))
+ if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
return false;
- if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index,
- reg_info_index))
+ if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index))
return false;
/* read base register */
diff --git a/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp b/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
index 19598ebfd4c30..5f4f5015e5a30 100644
--- a/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
+++ b/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
@@ -239,14 +239,15 @@ bool EmulateInstructionPPC64::EmulateLD(uint32_t opcode) {
Log *log = GetLog(LLDBLog::Unwind);
LLDB_LOG(log, "EmulateLD: {0:X+8}: ld r{1}, {2}(r{3})", m_addr, rt, ids, ra);
- RegisterInfo r1_info;
- if (!GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le, r1_info))
+ llvm::Optional<RegisterInfo> r1_info =
+ GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le);
+ if (!r1_info)
return false;
// restore SP
Context ctx;
ctx.type = eContextRestoreStackPointer;
- ctx.SetRegisterToRegisterPlusOffset(r1_info, r1_info, 0);
+ ctx.SetRegisterToRegisterPlusOffset(*r1_info, *r1_info, 0);
WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_ppc64le, 0);
LLDB_LOG(log, "EmulateLD: success!");
@@ -289,16 +290,17 @@ bool EmulateInstructionPPC64::EmulateSTD(uint32_t opcode) {
}
// set context
- RegisterInfo rs_info;
- if (!GetRegisterInfo(eRegisterKindLLDB, rs_num, rs_info))
+ llvm::Optional<RegisterInfo> rs_info =
+ GetRegisterInfo(eRegisterKindLLDB, rs_num);
+ if (!rs_info)
return false;
- RegisterInfo ra_info;
- if (!GetRegisterInfo(eRegisterKindLLDB, ra, ra_info))
+ llvm::Optional<RegisterInfo> ra_info = GetRegisterInfo(eRegisterKindLLDB, ra);
+ if (!ra_info)
return false;
Context ctx;
ctx.type = eContextPushRegisterOnStack;
- ctx.SetRegisterToRegisterPlusOffset(rs_info, ra_info, ids);
+ ctx.SetRegisterToRegisterPlusOffset(*rs_info, *ra_info, ids);
// store
uint64_t ra_val = ReadRegisterUnsigned(eRegisterKindLLDB, ra, 0, &success);
@@ -334,13 +336,13 @@ bool EmulateInstructionPPC64::EmulateOR(uint32_t opcode) {
LLDB_LOG(log, "EmulateOR: {0:X+8}: mr r{1}, r{2}", m_addr, ra, rb);
// set context
- RegisterInfo ra_info;
- if (!GetRegisterInfo(eRegisterKindLLDB, ra, ra_info))
+ llvm::Optional<RegisterInfo> ra_info = GetRegisterInfo(eRegisterKindLLDB, ra);
+ if (!ra_info)
return false;
Context ctx;
ctx.type = eContextSetFramePointer;
- ctx.SetRegister(ra_info);
+ ctx.SetRegister(*ra_info);
// move
bool success;
@@ -369,13 +371,14 @@ bool EmulateInstructionPPC64::EmulateADDI(uint32_t opcode) {
LLDB_LOG(log, "EmulateADDI: {0:X+8}: addi r1, r1, {1}", m_addr, si_val);
// set context
- RegisterInfo r1_info;
- if (!GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le, r1_info))
+ llvm::Optional<RegisterInfo> r1_info =
+ GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le);
+ if (!r1_info)
return false;
Context ctx;
ctx.type = eContextRestoreStackPointer;
- ctx.SetRegisterToRegisterPlusOffset(r1_info, r1_info, 0);
+ ctx.SetRegisterToRegisterPlusOffset(*r1_info, *r1_info, 0);
// adjust SP
bool success;
diff --git a/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp b/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
index acd10bd70c095..47fc210b5d641 100644
--- a/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+++ b/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
@@ -84,10 +84,8 @@ bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
const bool show_address = true;
const bool show_bytes = true;
const bool show_control_flow_kind = true;
- m_inst_emulator_up->GetRegisterInfo(unwind_plan.GetRegisterKind(),
- unwind_plan.GetInitialCFARegister(),
- m_cfa_reg_info);
-
+ m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+ unwind_plan.GetRegisterKind(), unwind_plan.GetInitialCFARegister());
m_fp_is_cfa = false;
m_register_values.clear();
m_pushed_regs.clear();
@@ -130,9 +128,8 @@ bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
// cache the stack pointer register number (in whatever register
// numbering this UnwindPlan uses) for quick reference during
// instruction parsing.
- RegisterInfo sp_reg_info;
- m_inst_emulator_up->GetRegisterInfo(
- eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp_reg_info);
+ RegisterInfo sp_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+ eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
// The architecture dependent condition code of the last processed
// instruction.
@@ -172,8 +169,8 @@ bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
lldb::RegisterKind row_kind =
m_unwind_plan_ptr->GetRegisterKind();
// set m_cfa_reg_info to the row's CFA reg.
- m_inst_emulator_up->GetRegisterInfo(row_kind, row_cfa_regnum,
- m_cfa_reg_info);
+ m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+ row_kind, row_cfa_regnum);
// set m_fp_is_cfa.
if (sp_reg_info.kinds[row_kind] == row_cfa_regnum)
m_fp_is_cfa = false;
@@ -219,8 +216,8 @@ bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
lldb::RegisterKind row_kind =
m_unwind_plan_ptr->GetRegisterKind();
// set m_cfa_reg_info to the row's CFA reg.
- m_inst_emulator_up->GetRegisterInfo(row_kind, row_cfa_regnum,
- m_cfa_reg_info);
+ m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+ row_kind, row_cfa_regnum);
// set m_fp_is_cfa.
if (sp_reg_info.kinds[row_kind] == row_cfa_regnum)
m_fp_is_cfa = false;
@@ -623,11 +620,10 @@ bool UnwindAssemblyInstEmulation::WriteRegister(
// to using SP to calculate the CFA.
if (m_fp_is_cfa) {
m_fp_is_cfa = false;
- RegisterInfo sp_reg_info;
lldb::RegisterKind sp_reg_kind = eRegisterKindGeneric;
uint32_t sp_reg_num = LLDB_REGNUM_GENERIC_SP;
- m_inst_emulator_up->GetRegisterInfo(sp_reg_kind, sp_reg_num,
- sp_reg_info);
+ RegisterInfo sp_reg_info =
+ *m_inst_emulator_up->GetRegisterInfo(sp_reg_kind, sp_reg_num);
RegisterValue sp_reg_val;
if (GetRegisterValue(sp_reg_info, sp_reg_val)) {
m_cfa_reg_info = sp_reg_info;
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