[Lldb-commits] [PATCH] D130342: [LLDB][RISCV] Add riscv register definition and read/write
Emmmer S via Phabricator via lldb-commits
lldb-commits at lists.llvm.org
Wed Aug 10 23:24:18 PDT 2022
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7bece0f03bf6: [LLDB][RISCV] Add riscv register definition and read/write (authored by Emmmer).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130342/new/
https://reviews.llvm.org/D130342
Files:
lldb/source/Host/common/HostInfoBase.cpp
lldb/source/Plugins/Process/Linux/CMakeLists.txt
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
lldb/source/Plugins/Process/Utility/CMakeLists.txt
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
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