[Lldb-commits] [PATCH] D131244: [LLDB] Missing break in a switch statement alters the execution flow.

[Slava Gurevich via Phabricator via lldb-commits]

fixathon updated this revision to Diff 450466.
fixathon added a comment.

Code update to address the comments

Differential Revision: https://reviews.llvm.org/D131244


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131244/new/

https://reviews.llvm.org/D131244

Files:
  lldb/source/Plugins/Process/Utility/ARMUtils.h


Index: lldb/source/Plugins/Process/Utility/ARMUtils.h
===================================================================
--- lldb/source/Plugins/Process/Utility/ARMUtils.h
+++ lldb/source/Plugins/Process/Utility/ARMUtils.h
@@ -25,7 +25,8 @@
                                       ARM_ShifterType &shift_t) {
   switch (type) {
   default:
-  // assert(0 && "Invalid shift type");
+    assert(0 && "Invalid shift type");
+    break;
   case 0:
     shift_t = SRType_LSL;
     return imm5;
@@ -302,7 +303,7 @@
 // (imm32, carry_out) = ThumbExpandImm_C(imm12, carry_in)
 static inline uint32_t ThumbExpandImm_C(uint32_t opcode, uint32_t carry_in,
                                         uint32_t &carry_out) {
-  uint32_t imm32; // the expanded result
+  uint32_t imm32 = 0; // the expanded result
   const uint32_t i = bit(opcode, 26);
   const uint32_t imm3 = bits(opcode, 14, 12);
   const uint32_t abcdefgh = bits(opcode, 7, 0);
@@ -311,6 +312,8 @@
   if (bits(imm12, 11, 10) == 0) {
     switch (bits(imm12, 9, 8)) {
     default: // Keep static analyzer happy with a default case
+      break;
+
     case 0:
       imm32 = abcdefgh;
       break;


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