[Lldb-commits] [PATCH] D116912: [lldb] Check for arm64 in TestDisassembleRawData

[Dave Lee via Phabricator via lldb-commits]

kastiglione created this revision.
kastiglione added reviewers: jasonmolenda, JDevlieghere.
Herald added subscribers: omjavaid, kristof.beyls.
kastiglione requested review of this revision.
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This test checks for `aarch64` but the lit config could also contain `arm64`.
This change adds `arm64` to make the test pass in all cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116912

Files:
  lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py


Index: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py
===================================================================
--- lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py
+++ lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py
@@ -31,7 +31,7 @@
         elif re.match("powerpc64le", arch):
             target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le")
             raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38])
-        elif arch == "aarch64":
+        elif arch in ("aarch64", "arm64"):
             target = self.dbg.CreateTargetWithFileAndTargetTriple("", "aarch64")
             raw_bytes = bytearray([0x60, 0x0c, 0x80, 0x52])
         elif arch == "arm":
@@ -57,7 +57,7 @@
         elif re.match("powerpc64le", arch):
             self.assertEqual(inst.GetMnemonic(target), "li")
             self.assertEqual(inst.GetOperands(target), "4, 0")
-        elif arch == "aarch64":
+        elif arch in ("aarch64", "arm64"):
             self.assertEqual(inst.GetMnemonic(target), "mov")
             self.assertEqual(inst.GetOperands(target), "w0, #0x63")
         elif arch == "arm":


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