[Lldb-commits] [lldb] 6561c07 - [lldb] [Process/Utility] Define qN regs on ARM via helper macro
Michał Górny via lldb-commits
lldb-commits at lists.llvm.org
Wed Oct 20 04:08:26 PDT 2021
Author: Michał Górny
Date: 2021-10-20T13:08:17+02:00
New Revision: 6561c074c072beb6c8e400a62bd5943a1f26a72a
URL: https://github.com/llvm/llvm-project/commit/6561c074c072beb6c8e400a62bd5943a1f26a72a
DIFF: https://github.com/llvm/llvm-project/commit/6561c074c072beb6c8e400a62bd5943a1f26a72a.diff
LOG: [lldb] [Process/Utility] Define qN regs on ARM via helper macro
Add a FPU_QREG macro to define qN registers. This is a piece-wise
attempt of reconstructing D112066 with the goal of figuring out which
part of the larger change breaks the buildbot.
Differential Revision: https://reviews.llvm.org/D112066
Added:
Modified:
lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
Removed:
################################################################################
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
index 2eabe1659c2b..a0bae19b1fbc 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
@@ -320,6 +320,15 @@ static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM};
nullptr, g_##name##_invalidates, \
}
+#define FPU_QREG(name, offset) \
+ { \
+ #name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \
+ eFormatVectorOfUInt8, \
+ {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \
+ LLDB_INVALID_REGNUM, fpu_##name }, \
+ g_##name##_contains, nullptr, \
+ }
+
static RegisterInfo g_register_infos_arm[] = {
// NAME ALT SZ OFFSET ENCODING FORMAT
// EH_FRAME DWARF GENERIC
@@ -612,198 +621,22 @@ static RegisterInfo g_register_infos_arm[] = {
FPU_REG(d30, 8, 60, q15),
FPU_REG(d31, 8, 62, q15),
- {
- "q0",
- nullptr,
- 16,
- FPU_OFFSET(0),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q0, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q0},
- g_q0_contains,
- nullptr,
- },
- {
- "q1",
- nullptr,
- 16,
- FPU_OFFSET(4),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q1, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q1},
- g_q1_contains,
- nullptr,
- },
- {
- "q2",
- nullptr,
- 16,
- FPU_OFFSET(8),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q2, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q2},
- g_q2_contains,
- nullptr,
- },
- {
- "q3",
- nullptr,
- 16,
- FPU_OFFSET(12),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q3, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q3},
- g_q3_contains,
- nullptr,
- },
- {
- "q4",
- nullptr,
- 16,
- FPU_OFFSET(16),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q4, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q4},
- g_q4_contains,
- nullptr,
- },
- {
- "q5",
- nullptr,
- 16,
- FPU_OFFSET(20),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q5, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q5},
- g_q5_contains,
- nullptr,
- },
- {
- "q6",
- nullptr,
- 16,
- FPU_OFFSET(24),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q6, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q6},
- g_q6_contains,
- nullptr,
- },
- {
- "q7",
- nullptr,
- 16,
- FPU_OFFSET(28),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q7, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q7},
- g_q7_contains,
- nullptr,
- },
- {
- "q8",
- nullptr,
- 16,
- FPU_OFFSET(32),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q8, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q8},
- g_q8_contains,
- nullptr,
- },
- {
- "q9",
- nullptr,
- 16,
- FPU_OFFSET(36),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q9, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q9},
- g_q9_contains,
- nullptr,
- },
- {
- "q10",
- nullptr,
- 16,
- FPU_OFFSET(40),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q10, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q10},
- g_q10_contains,
- nullptr,
- },
- {
- "q11",
- nullptr,
- 16,
- FPU_OFFSET(44),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q11, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q11},
- g_q11_contains,
- nullptr,
- },
- {
- "q12",
- nullptr,
- 16,
- FPU_OFFSET(48),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q12, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q12},
- g_q12_contains,
- nullptr,
- },
- {
- "q13",
- nullptr,
- 16,
- FPU_OFFSET(52),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q13, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q13},
- g_q13_contains,
- nullptr,
- },
- {
- "q14",
- nullptr,
- 16,
- FPU_OFFSET(56),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q14, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q14},
- g_q14_contains,
- nullptr,
- },
- {
- "q15",
- nullptr,
- 16,
- FPU_OFFSET(60),
- eEncodingVector,
- eFormatVectorOfUInt8,
- {LLDB_INVALID_REGNUM, dwarf_q15, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_q15},
- g_q15_contains,
- nullptr,
- },
+ FPU_QREG(q0, 0),
+ FPU_QREG(q1, 4),
+ FPU_QREG(q2, 8),
+ FPU_QREG(q3, 12),
+ FPU_QREG(q4, 16),
+ FPU_QREG(q5, 20),
+ FPU_QREG(q6, 24),
+ FPU_QREG(q7, 28),
+ FPU_QREG(q8, 32),
+ FPU_QREG(q9, 36),
+ FPU_QREG(q10, 40),
+ FPU_QREG(q11, 44),
+ FPU_QREG(q12, 48),
+ FPU_QREG(q13, 52),
+ FPU_QREG(q14, 56),
+ FPU_QREG(q15, 60),
{
"exception",
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