[Lldb-commits] [lldb] b492b0b - [lldb] [Process/Utility] Define dN regs on ARM via helper macro
Michał Górny via lldb-commits
lldb-commits at lists.llvm.org
Tue Oct 19 08:06:29 PDT 2021
Author: Michał Górny
Date: 2021-10-19T17:06:03+02:00
New Revision: b492b0be95d9134bfb092eb2c73cf6996c4518f7
URL: https://github.com/llvm/llvm-project/commit/b492b0be95d9134bfb092eb2c73cf6996c4518f7
DIFF: https://github.com/llvm/llvm-project/commit/b492b0be95d9134bfb092eb2c73cf6996c4518f7.diff
LOG: [lldb] [Process/Utility] Define dN regs on ARM via helper macro
Use FPU_REG macro to define dN registers, removing the wrong value_regs
while at it. This is a piece-wise attempt of reconstructing D112066
with the goal of figuring out which part of the larger change breaks
the buildbot.
Differential Revision: https://reviews.llvm.org/D112066
Added:
Modified:
lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
Removed:
################################################################################
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
index 1f30cb0723ce..2eabe1659c2b 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
@@ -254,23 +254,6 @@ static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
-static uint32_t g_d0_contains[] = {fpu_s0, fpu_s1, LLDB_INVALID_REGNUM};
-static uint32_t g_d1_contains[] = {fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
-static uint32_t g_d2_contains[] = {fpu_s4, fpu_s5, LLDB_INVALID_REGNUM};
-static uint32_t g_d3_contains[] = {fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
-static uint32_t g_d4_contains[] = {fpu_s8, fpu_s9, LLDB_INVALID_REGNUM};
-static uint32_t g_d5_contains[] = {fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
-static uint32_t g_d6_contains[] = {fpu_s12, fpu_s13, LLDB_INVALID_REGNUM};
-static uint32_t g_d7_contains[] = {fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
-static uint32_t g_d8_contains[] = {fpu_s16, fpu_s17, LLDB_INVALID_REGNUM};
-static uint32_t g_d9_contains[] = {fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
-static uint32_t g_d10_contains[] = {fpu_s20, fpu_s21, LLDB_INVALID_REGNUM};
-static uint32_t g_d11_contains[] = {fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
-static uint32_t g_d12_contains[] = {fpu_s24, fpu_s25, LLDB_INVALID_REGNUM};
-static uint32_t g_d13_contains[] = {fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
-static uint32_t g_d14_contains[] = {fpu_s28, fpu_s29, LLDB_INVALID_REGNUM};
-static uint32_t g_d15_contains[] = {fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
-
static uint32_t g_d0_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
static uint32_t g_d1_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
static uint32_t g_d2_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
@@ -596,390 +579,38 @@ static RegisterInfo g_register_infos_arm[] = {
nullptr,
},
- {
- "d0",
- nullptr,
- 8,
- FPU_OFFSET(0),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d0, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d0},
- g_d0_contains,
- g_d0_invalidates,
- },
- {
- "d1",
- nullptr,
- 8,
- FPU_OFFSET(2),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d1, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d1},
- g_d1_contains,
- g_d1_invalidates,
- },
- {
- "d2",
- nullptr,
- 8,
- FPU_OFFSET(4),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d2, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d2},
- g_d2_contains,
- g_d2_invalidates,
- },
- {
- "d3",
- nullptr,
- 8,
- FPU_OFFSET(6),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d3, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d3},
- g_d3_contains,
- g_d3_invalidates,
- },
- {
- "d4",
- nullptr,
- 8,
- FPU_OFFSET(8),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d4, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d4},
- g_d4_contains,
- g_d4_invalidates,
- },
- {
- "d5",
- nullptr,
- 8,
- FPU_OFFSET(10),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d5, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d5},
- g_d5_contains,
- g_d5_invalidates,
- },
- {
- "d6",
- nullptr,
- 8,
- FPU_OFFSET(12),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d6, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d6},
- g_d6_contains,
- g_d6_invalidates,
- },
- {
- "d7",
- nullptr,
- 8,
- FPU_OFFSET(14),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d7, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d7},
- g_d7_contains,
- g_d7_invalidates,
- },
- {
- "d8",
- nullptr,
- 8,
- FPU_OFFSET(16),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d8, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d8},
- g_d8_contains,
- g_d8_invalidates,
- },
- {
- "d9",
- nullptr,
- 8,
- FPU_OFFSET(18),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d9, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d9},
- g_d9_contains,
- g_d9_invalidates,
- },
- {
- "d10",
- nullptr,
- 8,
- FPU_OFFSET(20),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d10, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d10},
- g_d10_contains,
- g_d10_invalidates,
- },
- {
- "d11",
- nullptr,
- 8,
- FPU_OFFSET(22),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d11, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d11},
- g_d11_contains,
- g_d11_invalidates,
- },
- {
- "d12",
- nullptr,
- 8,
- FPU_OFFSET(24),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d12, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d12},
- g_d12_contains,
- g_d12_invalidates,
- },
- {
- "d13",
- nullptr,
- 8,
- FPU_OFFSET(26),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d13, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d13},
- g_d13_contains,
- g_d13_invalidates,
- },
- {
- "d14",
- nullptr,
- 8,
- FPU_OFFSET(28),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d14, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d14},
- g_d14_contains,
- g_d14_invalidates,
- },
- {
- "d15",
- nullptr,
- 8,
- FPU_OFFSET(30),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d15, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d15},
- g_d15_contains,
- g_d15_invalidates,
- },
- {
- "d16",
- nullptr,
- 8,
- FPU_OFFSET(32),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d16},
- nullptr,
- g_d16_invalidates,
- },
- {
- "d17",
- nullptr,
- 8,
- FPU_OFFSET(34),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d17},
- nullptr,
- g_d17_invalidates,
- },
- {
- "d18",
- nullptr,
- 8,
- FPU_OFFSET(36),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d18},
- nullptr,
- g_d18_invalidates,
- },
- {
- "d19",
- nullptr,
- 8,
- FPU_OFFSET(38),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d19},
- nullptr,
- g_d19_invalidates,
- },
- {
- "d20",
- nullptr,
- 8,
- FPU_OFFSET(40),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d20},
- nullptr,
- g_d20_invalidates,
- },
- {
- "d21",
- nullptr,
- 8,
- FPU_OFFSET(42),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d21},
- nullptr,
- g_d21_invalidates,
- },
- {
- "d22",
- nullptr,
- 8,
- FPU_OFFSET(44),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d22},
- nullptr,
- g_d22_invalidates,
- },
- {
- "d23",
- nullptr,
- 8,
- FPU_OFFSET(46),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d23},
- nullptr,
- g_d23_invalidates,
- },
- {
- "d24",
- nullptr,
- 8,
- FPU_OFFSET(48),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d24},
- nullptr,
- g_d24_invalidates,
- },
- {
- "d25",
- nullptr,
- 8,
- FPU_OFFSET(50),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d25},
- nullptr,
- g_d25_invalidates,
- },
- {
- "d26",
- nullptr,
- 8,
- FPU_OFFSET(52),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d26},
- nullptr,
- g_d26_invalidates,
- },
- {
- "d27",
- nullptr,
- 8,
- FPU_OFFSET(54),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d27},
- nullptr,
- g_d27_invalidates,
- },
- {
- "d28",
- nullptr,
- 8,
- FPU_OFFSET(56),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d28},
- nullptr,
- g_d28_invalidates,
- },
- {
- "d29",
- nullptr,
- 8,
- FPU_OFFSET(58),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d29},
- nullptr,
- g_d29_invalidates,
- },
- {
- "d30",
- nullptr,
- 8,
- FPU_OFFSET(60),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d30},
- nullptr,
- g_d30_invalidates,
- },
- {
- "d31",
- nullptr,
- 8,
- FPU_OFFSET(62),
- eEncodingIEEE754,
- eFormatFloat,
- {LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM,
- LLDB_INVALID_REGNUM, fpu_d31},
- nullptr,
- g_d31_invalidates,
- },
+ FPU_REG(d0, 8, 0, q0),
+ FPU_REG(d1, 8, 2, q0),
+ FPU_REG(d2, 8, 4, q1),
+ FPU_REG(d3, 8, 6, q1),
+ FPU_REG(d4, 8, 8, q2),
+ FPU_REG(d5, 8, 10, q2),
+ FPU_REG(d6, 8, 12, q3),
+ FPU_REG(d7, 8, 14, q3),
+ FPU_REG(d8, 8, 16, q4),
+ FPU_REG(d9, 8, 18, q4),
+ FPU_REG(d10, 8, 20, q5),
+ FPU_REG(d11, 8, 22, q5),
+ FPU_REG(d12, 8, 24, q6),
+ FPU_REG(d13, 8, 26, q6),
+ FPU_REG(d14, 8, 28, q7),
+ FPU_REG(d15, 8, 30, q7),
+ FPU_REG(d16, 8, 32, q8),
+ FPU_REG(d17, 8, 34, q8),
+ FPU_REG(d18, 8, 36, q9),
+ FPU_REG(d19, 8, 38, q9),
+ FPU_REG(d20, 8, 40, q10),
+ FPU_REG(d21, 8, 42, q10),
+ FPU_REG(d22, 8, 44, q11),
+ FPU_REG(d23, 8, 46, q11),
+ FPU_REG(d24, 8, 48, q12),
+ FPU_REG(d25, 8, 50, q12),
+ FPU_REG(d26, 8, 52, q13),
+ FPU_REG(d27, 8, 54, q13),
+ FPU_REG(d28, 8, 56, q14),
+ FPU_REG(d29, 8, 58, q14),
+ FPU_REG(d30, 8, 60, q15),
+ FPU_REG(d31, 8, 62, q15),
{
"q0",
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