[Lldb-commits] [lldb] f37834c - [lldb] [test] Add a minimal test for x86 dbreg reading

Michał Górny via lldb-commits lldb-commits at lists.llvm.org
Thu Nov 12 05:09:14 PST 2020


Author: Michał Górny
Date: 2020-11-12T14:09:03+01:00
New Revision: f37834c7dcbe69405bf3e182d2b3e3227cc4a569

URL: https://github.com/llvm/llvm-project/commit/f37834c7dcbe69405bf3e182d2b3e3227cc4a569
DIFF: https://github.com/llvm/llvm-project/commit/f37834c7dcbe69405bf3e182d2b3e3227cc4a569.diff

LOG: [lldb] [test] Add a minimal test for x86 dbreg reading

Add a test verifying that after the 'watchpoint' command, new values
of x86 debug registers can be read back correctly.  The primary purpose
of this test is to catch broken DRn reading and help debugging it.

Differential Revision: https://reviews.llvm.org/D91264

Added: 
    lldb/test/Shell/Register/Inputs/x86-db-read.cpp
    lldb/test/Shell/Register/x86-db-read.test

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/lldb/test/Shell/Register/Inputs/x86-db-read.cpp b/lldb/test/Shell/Register/Inputs/x86-db-read.cpp
new file mode 100644
index 000000000000..7aa957e10db8
--- /dev/null
+++ b/lldb/test/Shell/Register/Inputs/x86-db-read.cpp
@@ -0,0 +1,12 @@
+#include <cstdint>
+#include <csignal>
+
+uint8_t g_8w;
+uint16_t g_16rw;
+uint32_t g_32w;
+uint32_t g_32rw;
+
+int main() {
+  ::raise(SIGSTOP);
+  return 0;
+}

diff  --git a/lldb/test/Shell/Register/x86-db-read.test b/lldb/test/Shell/Register/x86-db-read.test
new file mode 100644
index 000000000000..f8380440c627
--- /dev/null
+++ b/lldb/test/Shell/Register/x86-db-read.test
@@ -0,0 +1,36 @@
+# Debug registers are currently printed only on FreeBSD.
+# REQUIRES: system-freebsd
+# REQUIRES: native && (target-x86 || target-x86_64) && dbregs-set
+# RUN: %clangxx_host -g %p/Inputs/x86-db-read.cpp -o %t
+# RUN: %lldb -b -s %s %t | FileCheck %s
+process launch
+# CHECK: Process {{[0-9]+}} stopped
+
+watchpoint set variable -w write g_8w
+# CHECK: Watchpoint created: Watchpoint 1: addr = 0x{{[0-9a-f]*}} size = 1 state = enabled type = w
+watchpoint set variable -w read_write g_16rw
+# CHECK: Watchpoint created: Watchpoint 2: addr = 0x{{[0-9a-f]*}} size = 2 state = enabled type = rw
+watchpoint set variable -w write g_32w
+# CHECK: Watchpoint created: Watchpoint 3: addr = 0x{{[0-9a-f]*}} size = 4 state = enabled type = w
+watchpoint set variable -w read_write g_32rw
+# CHECK: Watchpoint created: Watchpoint 4: addr = 0x{{[0-9a-f]*}} size = 4 state = enabled type = rw
+
+print &g_8w
+# CHECK: (uint8_t *) $0 = [[VAR8W:0x[0-9a-f]*]]
+print &g_16rw
+# CHECK: (uint16_t *) $1 = [[VAR16RW:0x[0-9a-f]*]]
+print &g_32w
+# CHECK: (uint32_t *) $2 = [[VAR32W:0x[0-9a-f]*]]
+print &g_32rw
+# CHECK: (uint32_t *) $3 = [[VAR64RW:0x[0-9a-f]*]]
+
+register read --all
+# CHECK-DAG: dr0 = [[VAR8W]]
+# CHECK-DAG: dr1 = [[VAR16RW]]
+# CHECK-DAG: dr2 = [[VAR32W]]
+# CHECK-DAG: dr3 = [[VAR64RW]]
+# CHECK-DAG: dr6 = 0x{{(00000000)?}}ffff0ff0
+# CHECK-DAG: dr7 = 0x{{(00000000)?}}fd7104aa
+
+process continue
+# CHECK: Process {{[0-9]+}} exited with status = 0


        


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