[Lldb-commits] [PATCH] D90741: [LLDB] Fix SVE reginfo for sequential offset in g packet

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid created this revision.
omjavaid added a reviewer: labath.
Herald added subscribers: kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
omjavaid requested review of this revision.

This moves in the direction of our effort to synchronize register descriptions between LLDB and GDB xml description. We want to able to send registers in a way that their offset fields can be re-constructed based on register sizes in the increasing order of register number.

In context to Arm64 SVE, FPCR and FPSR are same registers in FPU regset and SVE regset. Previously FPSR/FPCR offset was set at the end of SVE data because Linux ptrace data placed FPCR and FPSR at the end of SVE register set.

Now we have two options

1. to include 2 additional primary FPCR/FPSR at the end of SVE regset and make existing FPCR/FPSR in FPU regset as their value regs.
2. use the same register for both SVE and FPU register set.

I have taken the second choice and considering interoperability with other stubs like QEMU and that g packets should generate register data in increasing order of register numbers. We have to move FPCR/FPSR offset up to its original location according to register numbering scheme of ARM64 registers with SVE registers included.


https://reviews.llvm.org/D90741

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp


Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
===================================================================
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -89,7 +89,7 @@
     const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
     sve_reg_offset = sve::ptrace_fpsimd_offset + (reg - GetRegNumSVEZ0()) * 16;
   } else if (m_sve_state == SVEState::Full) {
-    uint32_t sve_z0_offset = GetGPRSize() + 8;
+    uint32_t sve_z0_offset = GetGPRSize() + 16;
     sve_reg_offset =
         sve::SigRegsOffset() + reg_info->byte_offset - sve_z0_offset;
   }
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -288,8 +288,10 @@
 
     uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
 
-    reg_info_ref[sve_vg].byte_offset = offset;
-    offset += reg_info_ref[sve_vg].byte_size;
+    reg_info_ref[fpu_fpsr].byte_offset = offset;
+    reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
+    reg_info_ref[sve_vg].byte_offset = offset + 8;
+    offset += 16;
 
     // Update Z registers size and offset
     uint32_t s_reg_base = fpu_s0;
@@ -314,8 +316,7 @@
       offset += reg_info_ref[it].byte_size;
     }
 
-    reg_info_ref[fpu_fpsr].byte_offset = offset;
-    reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
+    m_per_vq_reg_infos[sve_vq] = reg_info_ref;
   }
 
   m_register_info_p = reg_info_ref.data();
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===================================================================
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -1111,7 +1111,7 @@
     sve_reg_offset =
         SVE_PT_FPSIMD_OFFSET + (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16;
   } else if (m_sve_state == SVEState::Full) {
-    uint32_t sve_z0_offset = GetGPRSize() + 8;
+    uint32_t sve_z0_offset = GetGPRSize() + 16;
     sve_reg_offset =
         SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset;
   }


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