[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support
Muhammad Omair Javaid via Phabricator via lldb-commits
lldb-commits at lists.llvm.org
Mon Mar 30 03:44:57 PDT 2020
omjavaid created this revision.
omjavaid added reviewers: labath, clayborg, jankratochvil, jasonmolenda.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
This patch adds support for AArch64 SVE register infos description and register access via ptrace.
AArch64 SVE is a an optional extension of Arm v8.3-a architecture which introduces 32 vector registers Z, 16 predicate P registers and FFR predicate register. These registers have fixed names but can dynamically be configured to different size based on underlying OS configuration.
This patch adds register info struct that describes SVE register infos. Also provides native register context routines to access SVE registers. It introduces a mechanism to configure SVE register size and offsets at startup before exchanging register information across gdb-remote process.
It makes use of linux kernel definitions copied into lldb/source/Plugins/Process/Linux/LinuxPTraceDefines_arm64sve.h for backward compatibility with sysroots which might yet not support SVE definitions.
There are two test cases added to the testsuite one of them checks register size configuration based on vg (vector granule register). Also a test is added which verifies registers can be read and written.
There is no physical hardware currently available to test SVE and we make use of QEMU for the purpose of testing this feature.
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