[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid created this revision.
omjavaid added a reviewer: labath.
Herald added subscribers: danielkiss, kristof.beyls.

AArch64 reigster X and V registers are primary GPR and vector registers respectively. If these registers are modified their corresponding children w regs or s/d regs should be invalidated. Specially when a register write fails it is important that failure gets reflected to all the registers which draw their value from a particular value register.


https://reviews.llvm.org/D77045

Files:
  lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D77045.253532.patch
Type: text/x-patch
Size: 13633 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/lldb-commits/attachments/20200330/db5e92ac/attachment-0001.bin>