[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

Muhammad Omair Javaid via Phabricator via lldb-commits lldb-commits at lists.llvm.org
Mon Mar 30 02:40:32 PDT 2020

omjavaid created this revision.
omjavaid added a reviewer: labath.
Herald added subscribers: danielkiss, kristof.beyls.

AArch64 reigster X and V registers are primary GPR and vector registers respectively. If these registers are modified their corresponding children w regs or s/d regs should be invalidated. Specially when a register write fails it is important that failure gets reflected to all the registers which draw their value from a particular value register.



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