[Lldb-commits] [PATCH] D69371: [ARM64] Cleanup and speedup NativeRegisterContextLinux_arm64

[Omair Javaid via lldb-commits]

On Fri, 25 Oct 2019 at 17:53, Pavel Labath via Phabricator
<reviews at reviews.llvm.org> wrote:
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> labath added a comment.
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> In D69371#1721077 <https://reviews.llvm.org/D69371#1721077>, @omjavaid wrote:
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> > We ll be dealing with Linux user mode and mostly aarch64 data registers except for cpsr, fpsr and fpcr. I think we should be fine but let me confirm this again from documentation.
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> Right, but you're creating a general interface for all architectures, not just several aarch64 registers. Even if they don't make use of that facility now, it would be good to make sure they can do that in the future.
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> For instance, on x86, the kernel may decide to reject https://github.com/torvalds/linux/blob/master/arch/x86/kernel/ptrace.c#L187 some values of some registers, and silently ignore some bits in others https://github.com/torvalds/linux/blob/master/arch/x86/kernel/ptrace.c#L349. That's why I think it would be better to commit changes to memory automatically/immediately, and minimize the chances that subsequent "read" operations will return data which does not reflect the actual values held by the OS.

So I gave  fixed or undefined bits a thought and also considered
implications of reading/writing certain status or control registers.
User visible registers dont really have big implications and we can
afford to keep user-corrupted values until resume as in theory all
state changes are going to happen on resume and target/thread state is
halted.

But even if we don't want the user to be writing fixed value bit
fields, we can easily choose to invalidate register caches in case of
certain registers.

For example
if (regno == cpsr)
   InvalidateAllRegisters().

In case of arm64, NativeRegisterContextLinux_arm64::WriteRegister may
call NativeRegisterContextLinux_arm64::InvalidateAllRegisters() if a
register like cpsr, fpsr or fpcr is being written.
Other architectures can use similar implementation or ignore register
caching altogether.

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> CHANGES SINCE LAST ACTION
>   https://reviews.llvm.org/D69371/new/
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> https://reviews.llvm.org/D69371
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-- 
Omair Javaid
www.linaro.org