[Lldb-commits] [PATCH] D62732: [WIP][RISCV] Initial port of LLDB for RISC-V

[Simon Cook via Phabricator via lldb-commits]

simoncook updated this revision to Diff 205287.
simoncook added a comment.

- Refactored register tables to match style used in i386/x86_64
- Add enum for RISC-V DWARF numbers
- Add F registers (assuming 32-bit, at runtime this seems to be overwritten to 64-bit if D extension is provided)
- Add default unwind plan for first frame


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62732/new/

https://reviews.llvm.org/D62732

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/API/SystemInitializerFull.cpp
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.h
  lldb/source/Plugins/ABI/SysV-riscv/CMakeLists.txt
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Target/Platform.cpp
  lldb/source/Target/Thread.cpp
  lldb/source/Utility/ArchSpec.cpp

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