[Lldb-commits] [PATCH] D62771: [LLDBregisterNum] Update function call llvm::codeview::getRegisterNames(CPUType) in lldb

[Wanyi Ye via Phabricator via lldb-commits]

kusmour created this revision.
kusmour added reviewers: xiaobai, compnerd.
Herald added subscribers: lldb-commits, kristof.beyls, javed.absar.
Herald added a project: LLDB.

llvm updated the function from `llvm::codeview::getRegisterNames()` to `llvm::codeview::getRegisterNames(CPUType)`
according to the function implementation, there are only two different register number list: ARM64 for ARM64, X64 for all others
the backends for arm64 and aarch64 are merged so from lldb side, aarch64 will have `llvm::codeview::CPUType::ARM64`
and others will set CPUType to `llvm::codeview::CPUType::X64` for now


Repository:
  rLLDB LLDB

https://reviews.llvm.org/D62771

Files:
  lldb/source/Plugins/SymbolFile/NativePDB/PdbFPOProgramToDWARFExpression.cpp


Index: lldb/source/Plugins/SymbolFile/NativePDB/PdbFPOProgramToDWARFExpression.cpp
===================================================================
--- lldb/source/Plugins/SymbolFile/NativePDB/PdbFPOProgramToDWARFExpression.cpp
+++ lldb/source/Plugins/SymbolFile/NativePDB/PdbFPOProgramToDWARFExpression.cpp
@@ -24,9 +24,18 @@
 using namespace lldb_private::postfix;
 
 static uint32_t ResolveLLDBRegisterNum(llvm::StringRef reg_name, llvm::Triple::ArchType arch_type) {
+  llvm::codeview::CPUType cpu;
+  switch(arch_type) {
+    case llvm::Triple::ArchType::aarch64:
+    case llvm::Triple::ArchType::aarch64_be:
+    case llvm::Triple::ArchType::aarch64_32:
+      cpu = llvm::codeview::CPUType::ARM64;
+    default:
+      cpu = llvm::codeview::CPUType::X64;
+  }
   // lookup register name to get lldb register number
   llvm::ArrayRef<llvm::EnumEntry<uint16_t>> register_names =
-      llvm::codeview::getRegisterNames();
+      llvm::codeview::getRegisterNames(cpu);
   auto it = llvm::find_if(
       register_names,
       [&reg_name](const llvm::EnumEntry<uint16_t> &register_entry) {


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