[Lldb-commits] [lldb] r359387 - Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateADDRegShift

[Raphael Isemann via lldb-commits]

Author: teemperor
Date: Sat Apr 27 11:15:35 2019
New Revision: 359387

URL: http://llvm.org/viewvc/llvm-project?rev=359387&view=rev
Log:
Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateADDRegShift

Summary:
As reported in LLVM bug 41487, the check in this function is wrong and should be
the same as the described check in the comment (which is correctly copied from the
ARM ISA reference).

Reviewers: #lldb, davide, JDevlieghere

Reviewed By: #lldb, davide, JDevlieghere

Subscribers: davide, javed.absar, kristof.beyls, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D60654

Modified:
    lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=359387&r1=359386&r2=359387&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Sat Apr 27 11:15:35 2019
@@ -10150,7 +10150,7 @@ bool EmulateInstructionARM::EmulateADDRe
       shift_t = DecodeRegShift(Bits32(opcode, 6, 5));
 
       // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
-      if ((d == 15) || (m == 15) || (m == 15) || (s == 15))
+      if ((d == 15) || (n == 15) || (m == 15) || (s == 15))
         return false;
       break;