[Lldb-commits] [lldb] r326756 - Upstreaming avx512 register support in debugserver. These changes
Jason Molenda via lldb-commits
lldb-commits at lists.llvm.org
Mon Mar 5 16:27:41 PST 2018
Author: jmolenda
Date: Mon Mar 5 16:27:41 2018
New Revision: 326756
URL: http://llvm.org/viewvc/llvm-project?rev=326756&view=rev
Log:
Upstreaming avx512 register support in debugserver. These changes
were originally written by Chris Bieneman, they've undergone a
number of changes since then.
Also including the debugserver bridgeos support, another arm
environment that runs Darwin akin to ios. These codepaths are
activated when running in a bridgeos environment which we're not
set up to test today.
There's additional (small) lldb changes to handle bridgeos binaries
that still need to be merged up.
Tested on a darwin system with avx512 hardware and without.
<rdar://problem/36424951>
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestZMMRegister.py
Modified:
lldb/trunk/include/lldb/Core/RegisterValue.h
lldb/trunk/packages/Python/lldbsuite/test/decorators.py
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestYMMRegister.py
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/main.c
lldb/trunk/tools/debugserver/source/DNBDefs.h
lldb/trunk/tools/debugserver/source/MacOSX/MachProcess.mm
lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h
lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h
lldb/trunk/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h
lldb/trunk/tools/debugserver/source/RNBRemote.cpp
Modified: lldb/trunk/include/lldb/Core/RegisterValue.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/RegisterValue.h?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/include/lldb/Core/RegisterValue.h (original)
+++ lldb/trunk/include/lldb/Core/RegisterValue.h Mon Mar 5 16:27:41 2018
@@ -35,7 +35,7 @@ namespace lldb_private {
class RegisterValue {
public:
- enum { kMaxRegisterByteSize = 32u };
+ enum { kMaxRegisterByteSize = 64u };
enum Type {
eTypeInvalid,
Modified: lldb/trunk/packages/Python/lldbsuite/test/decorators.py
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/decorators.py?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/packages/Python/lldbsuite/test/decorators.py (original)
+++ lldb/trunk/packages/Python/lldbsuite/test/decorators.py Mon Mar 5 16:27:41 2018
@@ -10,6 +10,7 @@ import platform
import re
import sys
import tempfile
+import subprocess
# Third-party modules
import six
@@ -741,3 +742,20 @@ def skipIfXmlSupportMissing(func):
fail_value = True # More likely to notice if something goes wrong
have_xml = xml.GetValueForKey("value").GetBooleanValue(fail_value)
return unittest2.skipIf(not have_xml, "requires xml support")(func)
+
+# Call sysctl on darwin to see if a specified hardware feature is available on this machine.
+def skipUnlessFeature(feature):
+ def is_feature_enabled(self):
+ if platform.system() == 'Darwin':
+ try:
+ DEVNULL = open(os.devnull, 'w')
+ output = subprocess.check_output(["/usr/sbin/sysctl", feature], stderr=DEVNULL)
+ # If 'feature: 1' was output, then this feature is available and
+ # the test should not be skipped.
+ if re.match('%s: 1\s*' % feature, output):
+ return None
+ else:
+ return "%s is not supported on this system." % feature
+ except subprocess.CalledProcessError:
+ return "%s is not supported on this system." % feature
+ return skipTestIfFn(is_feature_enabled)
Modified: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestYMMRegister.py
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestYMMRegister.py?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestYMMRegister.py (original)
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestYMMRegister.py Mon Mar 5 16:27:41 2018
@@ -21,8 +21,9 @@ class TestYMMRegister(TestBase):
@skipIfiOSSimulator
@skipIfTargetAndroid()
@skipIf(archs=no_match(['i386', 'x86_64']))
+ @expectedFailureAll(oslist=["linux"], bugnumber="rdar://30523153")
def test(self):
- self.build()
+ self.build(dictionary={"CFLAGS_EXTRAS": "-march=haswell"})
self.setTearDownCleanup()
exe = self.getBuildArtifact("a.out")
@@ -56,9 +57,10 @@ class TestYMMRegister(TestBase):
else:
register_range = 8
for i in range(register_range):
+ j = i - ((i / 8) * 8)
self.runCmd("thread step-inst")
- register_byte = (byte_pattern1 | i)
+ register_byte = (byte_pattern1 | j)
pattern = "ymm" + str(i) + " = " + str('{') + (
str(hex(register_byte)) + ' ') * 31 + str(hex(register_byte)) + str('}')
@@ -66,7 +68,7 @@ class TestYMMRegister(TestBase):
"register read ymm" + str(i),
substrs=[pattern])
- register_byte = (byte_pattern2 | i)
+ register_byte = (byte_pattern2 | j)
pattern = "ymm" + str(i) + " = " + str('{') + (
str(hex(register_byte)) + ' ') * 31 + str(hex(register_byte)) + str('}')
Added: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestZMMRegister.py
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestZMMRegister.py?rev=326756&view=auto
==============================================================================
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestZMMRegister.py (added)
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/TestZMMRegister.py Mon Mar 5 16:27:41 2018
@@ -0,0 +1,126 @@
+"""
+Test that we correctly read the YMM registers.
+"""
+
+from __future__ import print_function
+
+
+import os
+import time
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class TestYMMRegister(TestBase):
+ mydir = TestBase.compute_mydir(__file__)
+ NO_DEBUG_INFO_TESTCASE = True
+
+ @skipUnlessDarwin
+ @skipIfiOSSimulator
+ @skipIf(archs=no_match(['i386', 'x86_64']))
+ @debugserver_test
+ @skipUnlessFeature('hw.optional.avx512f')
+ def test(self):
+ self.build(dictionary={"CFLAGS_EXTRAS": "-mavx512f"})
+ self.setTearDownCleanup()
+
+ exe = self.getBuildArtifact("a.out")
+ target = self.dbg.CreateTarget(exe)
+
+ self.assertTrue(target, VALID_TARGET)
+
+ byte_pattern1 = 0x80
+ byte_pattern2 = 0xFF
+
+ # This test is working with assembly instructions; it'll make
+ # it easier to debug the console output if the assembly is
+ # displayed.
+ self.runCmd("settings set stop-disassembly-display always")
+
+ # Launch the process and stop.
+ self.expect("run", PROCESS_STOPPED, substrs=['stopped'])
+
+ # Check stop reason; Should be either signal SIGTRAP or EXC_BREAKPOINT
+ output = self.res.GetOutput()
+ matched = False
+ substrs = [
+ 'stop reason = EXC_BREAKPOINT',
+ 'stop reason = signal SIGTRAP']
+ for str1 in substrs:
+ matched = output.find(str1) != -1
+ with recording(self, False) as sbuf:
+ print("%s sub string: %s" % ('Expecting', str1), file=sbuf)
+ print("Matched" if matched else "Not Matched", file=sbuf)
+ if matched:
+ break
+ self.assertTrue(matched, STOPPED_DUE_TO_SIGNAL)
+
+ if self.getArchitecture() == 'x86_64':
+ register_range = 16
+ else:
+ register_range = 8
+ for i in range(register_range):
+ j = i - ((i / 8) * 8)
+ self.runCmd("thread step-inst")
+
+ register_byte = (byte_pattern1 | j)
+ pattern = "ymm" + str(i) + " = " + str('{') + (
+ str(hex(register_byte)) + ' ') * 31 + str(hex(register_byte)) + str('}')
+
+ self.expect(
+ "register read ymm" + str(i),
+ substrs=[pattern])
+
+ register_byte = (byte_pattern2 | j)
+ pattern = "ymm" + str(i) + " = " + str('{') + (
+ str(hex(register_byte)) + ' ') * 31 + str(hex(register_byte)) + str('}')
+
+ self.runCmd("thread step-inst")
+ self.expect(
+ "register read ymm" + str(i),
+ substrs=[pattern])
+
+ self.expect("continue", PROCESS_STOPPED, substrs=['stopped'])
+
+ # Check stop reason; Should be either signal SIGTRAP or EXC_BREAKPOINT
+ output = self.res.GetOutput()
+ matched = False
+ substrs = [
+ 'stop reason = EXC_BREAKPOINT',
+ 'stop reason = signal SIGTRAP']
+ for str1 in substrs:
+ matched = output.find(str1) != -1
+ with recording(self, False) as sbuf:
+ print("%s sub string: %s" % ('Expecting', str1), file=sbuf)
+ print("Matched" if matched else "Not Matched", file=sbuf)
+ if matched:
+ break
+ self.assertTrue(matched, STOPPED_DUE_TO_SIGNAL)
+
+ if self.getArchitecture() == 'x86_64':
+ register_range = 32
+ else:
+ register_range = 8
+ for i in range(register_range):
+ j = i - ((i / 8) * 8)
+ self.runCmd("thread step-inst")
+ self.runCmd("thread step-inst")
+
+ register_byte = (byte_pattern2 | j)
+ pattern = "zmm" + str(i) + " = " + str('{') + (
+ str(hex(register_byte)) + ' ') * 63 + str(hex(register_byte)) + str('}')
+
+ self.expect(
+ "register read zmm" + str(i),
+ substrs=[pattern])
+
+ register_byte = (byte_pattern2 | j)
+ pattern = "zmm" + str(i) + " = " + str('{') + (
+ str(hex(register_byte)) + ' ') * 63 + str(hex(register_byte)) + str('}')
+
+ self.runCmd("thread step-inst")
+ self.expect(
+ "register read zmm" + str(i),
+ substrs=[pattern])
Modified: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/main.c
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/main.c?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/main.c (original)
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_avx/main.c Mon Mar 5 16:27:41 2018
@@ -9,15 +9,14 @@
void func() {
unsigned int ymmvalues[16];
- unsigned char val;
- unsigned char i;
- for (i = 0 ; i < 16 ; i++)
+ for (int i = 0 ; i < 16 ; i++)
{
- val = (0x80 | i);
+ unsigned char val = (0x80 | i);
ymmvalues[i] = (val << 24) | (val << 16) | (val << 8) | val;
}
unsigned int ymmallones = 0xFFFFFFFF;
+#if defined(__AVX__)
__asm__("int3;"
"vbroadcastss %1, %%ymm0;"
"vbroadcastss %0, %%ymm0;"
@@ -36,32 +35,109 @@ void func() {
"vbroadcastss %8, %%ymm7;"
"vbroadcastss %0, %%ymm7;"
#if defined(__x86_64__)
- "vbroadcastss %9, %%ymm8;"
+ "vbroadcastss %1, %%ymm8;"
"vbroadcastss %0, %%ymm8;"
- "vbroadcastss %10, %%ymm9;"
+ "vbroadcastss %2, %%ymm9;"
"vbroadcastss %0, %%ymm9;"
- "vbroadcastss %11, %%ymm10;"
+ "vbroadcastss %3, %%ymm10;"
"vbroadcastss %0, %%ymm10;"
- "vbroadcastss %12, %%ymm11;"
+ "vbroadcastss %4, %%ymm11;"
"vbroadcastss %0, %%ymm11;"
- "vbroadcastss %13, %%ymm12;"
+ "vbroadcastss %5, %%ymm12;"
"vbroadcastss %0, %%ymm12;"
- "vbroadcastss %14, %%ymm13;"
+ "vbroadcastss %6, %%ymm13;"
"vbroadcastss %0, %%ymm13;"
- "vbroadcastss %15, %%ymm14;"
+ "vbroadcastss %7, %%ymm14;"
"vbroadcastss %0, %%ymm14;"
- "vbroadcastss %16, %%ymm15;"
+ "vbroadcastss %8, %%ymm15;"
"vbroadcastss %0, %%ymm15;"
#endif
::"m"(ymmallones),
"m"(ymmvalues[0]), "m"(ymmvalues[1]), "m"(ymmvalues[2]), "m"(ymmvalues[3]),
"m"(ymmvalues[4]), "m"(ymmvalues[5]), "m"(ymmvalues[6]), "m"(ymmvalues[7])
+ );
+#endif
+
+#if defined(__AVX512F__)
+ unsigned int zmmvalues[32];
+ for (int i = 0 ; i < 32 ; i++)
+ {
+ unsigned char val = (0x80 | i);
+ zmmvalues[i] = (val << 24) | (val << 16) | (val << 8) | val;
+ }
+
+ __asm__("int3;"
+ "vbroadcastss %1, %%zmm0;"
+ "vbroadcastss %0, %%zmm0;"
+ "vbroadcastss %2, %%zmm1;"
+ "vbroadcastss %0, %%zmm1;"
+ "vbroadcastss %3, %%zmm2;"
+ "vbroadcastss %0, %%zmm2;"
+ "vbroadcastss %4, %%zmm3;"
+ "vbroadcastss %0, %%zmm3;"
+ "vbroadcastss %5, %%zmm4;"
+ "vbroadcastss %0, %%zmm4;"
+ "vbroadcastss %6, %%zmm5;"
+ "vbroadcastss %0, %%zmm5;"
+ "vbroadcastss %7, %%zmm6;"
+ "vbroadcastss %0, %%zmm6;"
+ "vbroadcastss %8, %%zmm7;"
+ "vbroadcastss %0, %%zmm7;"
#if defined(__x86_64__)
- ,
- "m"(ymmvalues[8]), "m"(ymmvalues[9]), "m"(ymmvalues[10]), "m"(ymmvalues[11]),
- "m"(ymmvalues[12]), "m"(ymmvalues[13]), "m"(ymmvalues[14]), "m"(ymmvalues[15])
+ "vbroadcastss %1, %%zmm8;"
+ "vbroadcastss %0, %%zmm8;"
+ "vbroadcastss %2, %%zmm9;"
+ "vbroadcastss %0, %%zmm9;"
+ "vbroadcastss %3, %%zmm10;"
+ "vbroadcastss %0, %%zmm10;"
+ "vbroadcastss %4, %%zmm11;"
+ "vbroadcastss %0, %%zmm11;"
+ "vbroadcastss %5, %%zmm12;"
+ "vbroadcastss %0, %%zmm12;"
+ "vbroadcastss %6, %%zmm13;"
+ "vbroadcastss %0, %%zmm13;"
+ "vbroadcastss %7, %%zmm14;"
+ "vbroadcastss %0, %%zmm14;"
+ "vbroadcastss %8, %%zmm15;"
+ "vbroadcastss %0, %%zmm15;"
+ "vbroadcastss %1, %%zmm16;"
+ "vbroadcastss %0, %%zmm16;"
+ "vbroadcastss %2, %%zmm17;"
+ "vbroadcastss %0, %%zmm17;"
+ "vbroadcastss %3, %%zmm18;"
+ "vbroadcastss %0, %%zmm18;"
+ "vbroadcastss %4, %%zmm19;"
+ "vbroadcastss %0, %%zmm19;"
+ "vbroadcastss %5, %%zmm20;"
+ "vbroadcastss %0, %%zmm20;"
+ "vbroadcastss %6, %%zmm21;"
+ "vbroadcastss %0, %%zmm21;"
+ "vbroadcastss %7, %%zmm22;"
+ "vbroadcastss %0, %%zmm22;"
+ "vbroadcastss %8, %%zmm23;"
+ "vbroadcastss %0, %%zmm23;"
+ "vbroadcastss %1, %%zmm24;"
+ "vbroadcastss %0, %%zmm24;"
+ "vbroadcastss %2, %%zmm25;"
+ "vbroadcastss %0, %%zmm25;"
+ "vbroadcastss %3, %%zmm26;"
+ "vbroadcastss %0, %%zmm26;"
+ "vbroadcastss %4, %%zmm27;"
+ "vbroadcastss %0, %%zmm27;"
+ "vbroadcastss %5, %%zmm28;"
+ "vbroadcastss %0, %%zmm28;"
+ "vbroadcastss %6, %%zmm29;"
+ "vbroadcastss %0, %%zmm29;"
+ "vbroadcastss %7, %%zmm30;"
+ "vbroadcastss %0, %%zmm30;"
+ "vbroadcastss %8, %%zmm31;"
+ "vbroadcastss %0, %%zmm31;"
+#endif
+ ::"m"(ymmallones),
+ "m"(zmmvalues[0]), "m"(zmmvalues[1]), "m"(zmmvalues[2]), "m"(zmmvalues[3]),
+ "m"(zmmvalues[4]), "m"(zmmvalues[5]), "m"(zmmvalues[6]), "m"(zmmvalues[7])
+ );
#endif
- );
}
int main(int argc, char const *argv[]) { func(); }
Modified: lldb/trunk/tools/debugserver/source/DNBDefs.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/DNBDefs.h?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/DNBDefs.h (original)
+++ lldb/trunk/tools/debugserver/source/DNBDefs.h Mon Mar 5 16:27:41 2018
@@ -290,16 +290,16 @@ struct DNBRegisterValue {
uint64_t uint64;
float float32;
double float64;
- int8_t v_sint8[32];
- int16_t v_sint16[16];
- int32_t v_sint32[8];
- int64_t v_sint64[4];
- uint8_t v_uint8[32];
- uint16_t v_uint16[16];
- uint32_t v_uint32[8];
- uint64_t v_uint64[4];
- float v_float32[8];
- double v_float64[4];
+ int8_t v_sint8[64];
+ int16_t v_sint16[32];
+ int32_t v_sint32[16];
+ int64_t v_sint64[8];
+ uint8_t v_uint8[64];
+ uint16_t v_uint16[32];
+ uint32_t v_uint32[16];
+ uint64_t v_uint64[8];
+ float v_float32[16];
+ double v_float64[8];
void *pointer;
char *c_str;
} value;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachProcess.mm
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachProcess.mm?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachProcess.mm (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachProcess.mm Mon Mar 5 16:27:41 2018
@@ -716,6 +716,45 @@ bool MachProcess::GetMachOInformationFro
inf.min_version_os_version += std::to_string(zz);
}
}
+#if defined (LC_BUILD_VERSION)
+ if (lc.cmd == LC_BUILD_VERSION)
+ {
+ struct build_version_command build_vers;
+ if (ReadMemory(load_cmds_p, sizeof(struct build_version_command),
+ &build_vers) != sizeof(struct build_version_command)) {
+ return false;
+ }
+ switch (build_vers.platform)
+ {
+ case PLATFORM_MACOS:
+ inf.min_version_os_name = "macosx";
+ break;
+ case PLATFORM_IOS:
+ inf.min_version_os_name = "iphoneos";
+ break;
+ case PLATFORM_TVOS:
+ inf.min_version_os_name = "tvos";
+ break;
+ case PLATFORM_WATCHOS:
+ inf.min_version_os_name = "watchos";
+ break;
+ case PLATFORM_BRIDGEOS:
+ inf.min_version_os_name = "bridgeos";
+ break;
+ }
+ uint32_t xxxx = build_vers.sdk >> 16;;
+ uint32_t yy = (build_vers.sdk >> 8) & 0xffu;
+ uint32_t zz = build_vers.sdk & 0xffu;
+ inf.min_version_os_version = "";
+ inf.min_version_os_version += std::to_string(xxxx);
+ inf.min_version_os_version += ".";
+ inf.min_version_os_version += std::to_string(yy);
+ if (zz != 0) {
+ inf.min_version_os_version += ".";
+ inf.min_version_os_version += std::to_string(zz);
+ }
+ }
+#endif
load_cmds_p += lc.cmdsize;
}
return true;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp Mon Mar 5 16:27:41 2018
@@ -21,7 +21,7 @@
#include "MachThread.h"
extern "C" bool CPUHasAVX(); // Defined over in DNBArchImplX86_64.cpp
-
+extern "C" bool CPUHasAVX512f(); // Defined over in DNBArchImplX86_64.cpp
#if defined(LLDB_DEBUGSERVER_RELEASE) || defined(LLDB_DEBUGSERVER_DEBUG)
enum debugState { debugStateUnknown, debugStateOff, debugStateOn };
@@ -132,6 +132,22 @@ enum {
fpu_ymm5,
fpu_ymm6,
fpu_ymm7,
+ fpu_k0,
+ fpu_k1,
+ fpu_k2,
+ fpu_k3,
+ fpu_k4,
+ fpu_k5,
+ fpu_k6,
+ fpu_k7,
+ fpu_zmm0,
+ fpu_zmm1,
+ fpu_zmm2,
+ fpu_zmm3,
+ fpu_zmm4,
+ fpu_zmm5,
+ fpu_zmm6,
+ fpu_zmm7,
k_num_fpu_regs,
// Aliases
@@ -205,6 +221,22 @@ enum {
dwarf_ymm5 = dwarf_xmm5,
dwarf_ymm6 = dwarf_xmm6,
dwarf_ymm7 = dwarf_xmm7,
+ dwarf_zmm0 = dwarf_xmm0,
+ dwarf_zmm1 = dwarf_xmm1,
+ dwarf_zmm2 = dwarf_xmm2,
+ dwarf_zmm3 = dwarf_xmm3,
+ dwarf_zmm4 = dwarf_xmm4,
+ dwarf_zmm5 = dwarf_xmm5,
+ dwarf_zmm6 = dwarf_xmm6,
+ dwarf_zmm7 = dwarf_xmm7,
+ dwarf_k0 = 118,
+ dwarf_k1,
+ dwarf_k2,
+ dwarf_k3,
+ dwarf_k4,
+ dwarf_k5,
+ dwarf_k6,
+ dwarf_k7,
};
enum {
@@ -271,7 +303,23 @@ enum {
debugserver_ymm4 = debugserver_xmm4,
debugserver_ymm5 = debugserver_xmm5,
debugserver_ymm6 = debugserver_xmm6,
- debugserver_ymm7 = debugserver_xmm7
+ debugserver_ymm7 = debugserver_xmm7,
+ debugserver_zmm0 = debugserver_xmm0,
+ debugserver_zmm1 = debugserver_xmm1,
+ debugserver_zmm2 = debugserver_xmm2,
+ debugserver_zmm3 = debugserver_xmm3,
+ debugserver_zmm4 = debugserver_xmm4,
+ debugserver_zmm5 = debugserver_xmm5,
+ debugserver_zmm6 = debugserver_xmm6,
+ debugserver_zmm7 = debugserver_xmm7,
+ debugserver_k0 = 118,
+ debugserver_k1 = 119,
+ debugserver_k2 = 120,
+ debugserver_k3 = 121,
+ debugserver_k4 = 122,
+ debugserver_k5 = 123,
+ debugserver_k6 = 124,
+ debugserver_k7 = 125,
};
uint64_t DNBArchImplI386::GetPC(uint64_t failValue) {
@@ -390,7 +438,8 @@ kern_return_t DNBArchImplI386::GetFPUSta
m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
if (CPUHasAVX() || FORCE_AVX_REGS) {
- for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
+ for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1);
+ ++i)
m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
for (int i = 0; i < 16; ++i) {
@@ -404,12 +453,54 @@ kern_return_t DNBArchImplI386::GetFPUSta
m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
}
}
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (int i = 0; i < 8; ++i) {
+ m_state.context.fpu.avx512f.__fpu_k0.__opmask_reg[i] = '0';
+ m_state.context.fpu.avx512f.__fpu_k1.__opmask_reg[i] = '1';
+ m_state.context.fpu.avx512f.__fpu_k2.__opmask_reg[i] = '2';
+ m_state.context.fpu.avx512f.__fpu_k3.__opmask_reg[i] = '3';
+ m_state.context.fpu.avx512f.__fpu_k4.__opmask_reg[i] = '4';
+ m_state.context.fpu.avx512f.__fpu_k5.__opmask_reg[i] = '5';
+ m_state.context.fpu.avx512f.__fpu_k6.__opmask_reg[i] = '6';
+ m_state.context.fpu.avx512f.__fpu_k7.__opmask_reg[i] = '7';
+ }
+
+ for (int i = 0; i < 32; ++i) {
+ m_state.context.fpu.avx512f.__fpu_zmmh0.__ymm_reg[i] = '0';
+ m_state.context.fpu.avx512f.__fpu_zmmh1.__ymm_reg[i] = '1';
+ m_state.context.fpu.avx512f.__fpu_zmmh2.__ymm_reg[i] = '2';
+ m_state.context.fpu.avx512f.__fpu_zmmh3.__ymm_reg[i] = '3';
+ m_state.context.fpu.avx512f.__fpu_zmmh4.__ymm_reg[i] = '4';
+ m_state.context.fpu.avx512f.__fpu_zmmh5.__ymm_reg[i] = '5';
+ m_state.context.fpu.avx512f.__fpu_zmmh6.__ymm_reg[i] = '6';
+ m_state.context.fpu.avx512f.__fpu_zmmh7.__ymm_reg[i] = '7';
+ }
+ }
m_state.SetError(e_regSetFPU, Read, 0);
} else {
mach_msg_type_number_t count = e_regSetWordSizeFPU;
int flavor = __i386_FLOAT_STATE;
- if (CPUHasAVX() || FORCE_AVX_REGS) {
+ // On a machine with the AVX512 register set, a process only gets a
+ // full AVX512 register context after it uses the AVX512 registers;
+ // if the process has not yet triggered this change, trying to fetch
+ // the AVX512 registers will fail. Fall through to fetching the AVX
+ // registers.
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ count = e_regSetWordSizeAVX512f;
+ flavor = __i386_AVX512F_STATE;
+ m_state.SetError(e_regSetFPU, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), flavor,
+ (thread_state_t)&m_state.context.fpu,
+ &count));
+ DNBLogThreadedIf(LOG_THREAD,
+ "::thread_get_state (0x%4.4x, %u, &fpu, %u => 0x%8.8x",
+ m_thread->MachPortNumber(), flavor, (uint32_t)count,
+ m_state.GetError(e_regSetFPU, Read));
+ if (m_state.GetError(e_regSetFPU, Read) == KERN_SUCCESS)
+ return m_state.GetError(e_regSetFPU, Read);
+ }
+ if (CPUHasAVX()) {
count = e_regSetWordSizeAVX;
flavor = __i386_AVX_STATE;
}
@@ -457,18 +548,21 @@ kern_return_t DNBArchImplI386::SetFPUSta
m_state.SetError(e_regSetFPU, Write, 0);
return m_state.GetError(e_regSetFPU, Write);
} else {
- if (CPUHasAVX() || FORCE_AVX_REGS)
- m_state.SetError(
- e_regSetFPU, Write,
- ::thread_set_state(m_thread->MachPortNumber(), __i386_AVX_STATE,
- (thread_state_t)&m_state.context.fpu.avx,
- e_regSetWordSizeAVX));
- else
- m_state.SetError(
- e_regSetFPU, Write,
- ::thread_set_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE,
- (thread_state_t)&m_state.context.fpu.no_avx,
- e_regSetWordSizeFPU));
+ int flavor = __i386_FLOAT_STATE;
+ mach_msg_type_number_t count = e_regSetWordSizeFPU;
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ flavor = __i386_AVX512F_STATE;
+ count = e_regSetWordSizeAVX512f;
+ } else
+ if (CPUHasAVX()) {
+ flavor = __i386_AVX_STATE;
+ count = e_regSetWordSizeAVX;
+ }
+
+ m_state.SetError(e_regSetFPU, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), flavor,
+ (thread_state_t)&m_state.context.fpu,
+ count));
return m_state.GetError(e_regSetFPU, Write);
}
}
@@ -965,6 +1059,9 @@ kern_return_t DNBArchImplI386::EnableHar
#define AVX_OFFSET(reg) \
(offsetof(DNBArchImplI386::AVX, __fpu_##reg) + \
offsetof(DNBArchImplI386::Context, fpu.avx))
+#define AVX512F_OFFSET(reg) \
+ (offsetof(DNBArchImplI386::AVX512F, __fpu_##reg) + \
+ offsetof(DNBArchImplI386::Context, fpu.avx512f))
#define EXC_OFFSET(reg) \
(offsetof(DNBArchImplI386::EXC, __##reg) + \
offsetof(DNBArchImplI386::Context, exc))
@@ -976,6 +1073,7 @@ kern_return_t DNBArchImplI386::EnableHar
#define FPU_SIZE_XMM(reg) \
(sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__xmm_reg))
#define FPU_SIZE_YMM(reg) (32)
+#define FPU_SIZE_ZMM(reg) (64)
#define EXC_SIZE(reg) (sizeof(((DNBArchImplI386::EXC *)NULL)->__##reg))
// This does not accurately identify the location of ymm0...7 in
@@ -985,6 +1083,9 @@ kern_return_t DNBArchImplI386::EnableHar
// -- not to interpret the thread_get_state info.
#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n))
+// TODO: Test this and come back.
+#define AVX512F_OFFSET_ZMM(n) (AVX_OFFSET_YMM(7) + FPU_SIZE_XMM(xmm7) + (64 * n))
+
// These macros will auto define the register name, alt name, register size,
// register offset, encoding, format and native register. This ensures that
// the register state structures are defined correctly and have the correct
@@ -1279,6 +1380,141 @@ const DNBRegisterInfo DNBArchImplI386::g
};
+
+#define STR(s) #s
+
+#define ZMM_REG_DEF(reg) \
+ { \
+ e_regSetFPU, fpu_zmm##reg, STR(zmm##reg), NULL, Vector, VectorOfUInt8, \
+ FPU_SIZE_ZMM(zmm##reg), AVX512F_OFFSET_ZMM(reg), INVALID_NUB_REGNUM, \
+ dwarf_zmm##reg, INVALID_NUB_REGNUM, debugserver_zmm##reg, NULL, NULL \
+ }
+
+#define YMM_REG_ALIAS(reg) \
+ { \
+ e_regSetFPU, fpu_ymm##reg, STR(ymm##reg), NULL, Vector, VectorOfUInt8, \
+ FPU_SIZE_YMM(ymm##reg), 0, INVALID_NUB_REGNUM, dwarf_ymm##reg, \
+ INVALID_NUB_REGNUM, debugserver_ymm##reg, g_contained_zmm##reg, NULL \
+ }
+
+#define XMM_REG_ALIAS(reg) \
+ { \
+ e_regSetFPU, fpu_xmm##reg, STR(xmm##reg), NULL, Vector, VectorOfUInt8, \
+ FPU_SIZE_XMM(xmm##reg), 0, INVALID_NUB_REGNUM, dwarf_xmm##reg, \
+ INVALID_NUB_REGNUM, debugserver_xmm##reg, g_contained_zmm##reg, NULL \
+ }
+
+#define AVX512_K_REG_DEF(reg) \
+ { \
+ e_regSetFPU, fpu_k##reg, STR(k##reg), NULL, Vector, VectorOfUInt8, 8, \
+ AVX512F_OFFSET(k##reg), dwarf_k##reg, dwarf_k##reg, -1U, \
+ debugserver_k##reg, NULL, NULL \
+ }
+
+static const char *g_contained_zmm0[] = {"zmm0", NULL};
+static const char *g_contained_zmm1[] = {"zmm1", NULL};
+static const char *g_contained_zmm2[] = {"zmm2", NULL};
+static const char *g_contained_zmm3[] = {"zmm3", NULL};
+static const char *g_contained_zmm4[] = {"zmm4", NULL};
+static const char *g_contained_zmm5[] = {"zmm5", NULL};
+static const char *g_contained_zmm6[] = {"zmm6", NULL};
+static const char *g_contained_zmm7[] = {"zmm7", NULL};
+
+const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx512f[] = {
+ {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
+ AVX_OFFSET(fcw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
+ AVX_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
+ FPU_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
+ AVX_OFFSET(fop), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
+ AVX_OFFSET(ip), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
+ AVX_OFFSET(cs), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
+ AVX_OFFSET(dp), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
+ AVX_OFFSET(ds), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
+ AVX_OFFSET(mxcsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
+ FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+
+ {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
+ INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
+ {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
+ INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
+ {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
+ INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
+ {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
+ INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
+ {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
+ INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
+ {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
+ INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
+ {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
+ INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
+ {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
+ INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
+
+ AVX512_K_REG_DEF(0),
+ AVX512_K_REG_DEF(1),
+ AVX512_K_REG_DEF(2),
+ AVX512_K_REG_DEF(3),
+ AVX512_K_REG_DEF(4),
+ AVX512_K_REG_DEF(5),
+ AVX512_K_REG_DEF(6),
+ AVX512_K_REG_DEF(7),
+
+ ZMM_REG_DEF(0),
+ ZMM_REG_DEF(1),
+ ZMM_REG_DEF(2),
+ ZMM_REG_DEF(3),
+ ZMM_REG_DEF(4),
+ ZMM_REG_DEF(5),
+ ZMM_REG_DEF(6),
+ ZMM_REG_DEF(7),
+
+ YMM_REG_ALIAS(0),
+ YMM_REG_ALIAS(1),
+ YMM_REG_ALIAS(2),
+ YMM_REG_ALIAS(3),
+ YMM_REG_ALIAS(4),
+ YMM_REG_ALIAS(5),
+ YMM_REG_ALIAS(6),
+ YMM_REG_ALIAS(7),
+
+ XMM_REG_ALIAS(0),
+ XMM_REG_ALIAS(1),
+ XMM_REG_ALIAS(2),
+ XMM_REG_ALIAS(3),
+ XMM_REG_ALIAS(4),
+ XMM_REG_ALIAS(5),
+ XMM_REG_ALIAS(6),
+ XMM_REG_ALIAS(7)
+
+};
+
const DNBRegisterInfo DNBArchImplI386::g_exc_registers[] = {
{e_regSetEXC, exc_trapno, "trapno", NULL, Uint, Hex, EXC_SIZE(trapno),
EXC_OFFSET(trapno), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
@@ -1297,12 +1533,16 @@ const size_t DNBArchImplI386::k_num_fpu_
sizeof(g_fpu_registers_no_avx) / sizeof(DNBRegisterInfo);
const size_t DNBArchImplI386::k_num_fpu_registers_avx =
sizeof(g_fpu_registers_avx) / sizeof(DNBRegisterInfo);
+const size_t DNBArchImplI386::k_num_fpu_registers_avx512f =
+ sizeof(g_fpu_registers_avx512f) / sizeof(DNBRegisterInfo);
const size_t DNBArchImplI386::k_num_exc_registers =
sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
const size_t DNBArchImplI386::k_num_all_registers_no_avx =
k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers;
const size_t DNBArchImplI386::k_num_all_registers_avx =
k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers;
+const size_t DNBArchImplI386::k_num_all_registers_avx512f =
+ k_num_gpr_registers + k_num_fpu_registers_avx512f + k_num_exc_registers;
//----------------------------------------------------------------------
// Register set definitions. The first definitions at register set index
@@ -1322,9 +1562,16 @@ const DNBRegisterSetInfo DNBArchImplI386
{"Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx},
{"Exception State Registers", g_exc_registers, k_num_exc_registers}};
+const DNBRegisterSetInfo DNBArchImplI386::g_reg_sets_avx512f[] = {
+ {"i386 Registers", NULL, k_num_all_registers_avx512f},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_fpu_registers_avx512f,
+ k_num_fpu_registers_avx512f},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
+
// Total number of register sets for this architecture
const size_t DNBArchImplI386::k_num_register_sets =
- sizeof(g_reg_sets_no_avx) / sizeof(DNBRegisterSetInfo);
+ sizeof(g_reg_sets_avx) / sizeof(DNBRegisterSetInfo);
DNBArchProtocol *DNBArchImplI386::Create(MachThread *thread) {
DNBArchImplI386 *obj = new DNBArchImplI386(thread);
@@ -1341,7 +1588,9 @@ const uint8_t *DNBArchImplI386::Software
const DNBRegisterSetInfo *
DNBArchImplI386::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
*num_reg_sets = k_num_register_sets;
- if (CPUHasAVX() || FORCE_AVX_REGS)
+ if (CPUHasAVX512f() || FORCE_AVX_REGS)
+ return g_reg_sets_avx512f;
+ if (CPUHasAVX())
return g_reg_sets_avx;
else
return g_reg_sets_no_avx;
@@ -1404,6 +1653,8 @@ bool DNBArchImplI386::GetRegisterValue(u
case e_regSetFPU:
if (reg > fpu_xmm7 && !(CPUHasAVX() || FORCE_AVX_REGS))
return false;
+ if (reg > fpu_ymm7 && !(CPUHasAVX512f() || FORCE_AVX_REGS))
+ return false;
switch (reg) {
case fpu_fcw:
value->value.uint16 =
@@ -1534,6 +1785,33 @@ bool DNBArchImplI386::GetRegisterValue(u
MEMCPY_YMM(7);
return true;
#undef MEMCPY_YMM
+
+ case fpu_k0:
+ case fpu_k1:
+ case fpu_k2:
+ case fpu_k3:
+ case fpu_k4:
+ case fpu_k5:
+ case fpu_k6:
+ case fpu_k7:
+ memcpy((&value->value.uint8),
+ &m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0), 8);
+ return true;
+ case fpu_zmm0:
+ case fpu_zmm1:
+ case fpu_zmm2:
+ case fpu_zmm3:
+ case fpu_zmm4:
+ case fpu_zmm5:
+ case fpu_zmm6:
+ case fpu_zmm7:
+ memcpy(&value->value.uint8,
+ &m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0), 16);
+ memcpy(&value->value.uint8 + 16,
+ &m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0), 16);
+ memcpy(&value->value.uint8 + 32,
+ &m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0), 32);
+ return true;
}
break;
@@ -1595,6 +1873,8 @@ bool DNBArchImplI386::SetRegisterValue(u
case e_regSetFPU:
if (reg > fpu_xmm7 && !(CPUHasAVX() || FORCE_AVX_REGS))
return false;
+ if (reg > fpu_ymm7 && !(CPUHasAVX512f() || FORCE_AVX_REGS))
+ return false;
switch (reg) {
case fpu_fcw:
*((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) =
@@ -1751,6 +2031,33 @@ bool DNBArchImplI386::SetRegisterValue(u
MEMCPY_YMM(7);
return true;
#undef MEMCPY_YMM
+
+ case fpu_k0:
+ case fpu_k1:
+ case fpu_k2:
+ case fpu_k3:
+ case fpu_k4:
+ case fpu_k5:
+ case fpu_k6:
+ case fpu_k7:
+ memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0),
+ &value->value.uint8, 8);
+ return true;
+ case fpu_zmm0:
+ case fpu_zmm1:
+ case fpu_zmm2:
+ case fpu_zmm3:
+ case fpu_zmm4:
+ case fpu_zmm5:
+ case fpu_zmm6:
+ case fpu_zmm7:
+ memcpy(&m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0),
+ &value->value.uint8, 16);
+ memcpy(&m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0),
+ &value->value.uint8 + 16, 16);
+ memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0),
+ &value->value.uint8 + 32, 32);
+ return true;
}
break;
@@ -1771,7 +2078,13 @@ bool DNBArchImplI386::SetRegisterValue(u
uint32_t DNBArchImplI386::GetRegisterContextSize() {
static uint32_t g_cached_size = 0;
if (g_cached_size == 0) {
- if (CPUHasAVX() || FORCE_AVX_REGS) {
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < k_num_fpu_registers_avx512f; ++i) {
+ if (g_fpu_registers_avx512f[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_avx512f[i].size;
+ }
+ } else
+ if (CPUHasAVX()) {
for (size_t i = 0; i < k_num_fpu_registers_avx; ++i) {
if (g_fpu_registers_avx[i].value_regs == NULL)
g_cached_size += g_fpu_registers_avx[i].size;
@@ -1844,6 +2157,13 @@ nub_size_t DNBArchImplI386::GetRegisterC
p += 10;
}
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(p, &m_state.context.fpu.avx512f.__fpu_k0 + i, 8);
+ p += 8;
+ }
+ }
+
if (CPUHasAVX() || FORCE_AVX_REGS) {
// Interleave the XMM and YMMH registers to make the YMM registers
for (size_t i = 0; i < 8; ++i) {
@@ -1852,6 +2172,12 @@ nub_size_t DNBArchImplI386::GetRegisterC
memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16);
p += 16;
}
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(p, &m_state.context.fpu.avx512f.__fpu_zmmh0 + i, 32);
+ p += 32;
+ }
+ }
} else {
// Copy the XMM registers in a single block
memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 8 * 16);
@@ -1908,6 +2234,13 @@ nub_size_t DNBArchImplI386::SetRegisterC
p += 10;
}
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + i, p, 8);
+ p += 8;
+ }
+ }
+
if (CPUHasAVX() || FORCE_AVX_REGS) {
// Interleave the XMM and YMMH registers to make the YMM registers
for (size_t i = 0; i < 8; ++i) {
@@ -1916,6 +2249,13 @@ nub_size_t DNBArchImplI386::SetRegisterC
memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16);
p += 16;
}
+
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + i, p, 32);
+ p += 32;
+ }
+ }
} else {
// Copy the XMM registers in a single block
memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 8 * 16);
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h Mon Mar 5 16:27:41 2018
@@ -83,6 +83,12 @@ protected:
static const size_t k_num_all_registers_avx;
static const size_t k_num_register_sets;
+ typedef __i386_avx512f_state_t AVX512F;
+ static const DNBRegisterInfo g_fpu_registers_avx512f[];
+ static const DNBRegisterSetInfo g_reg_sets_avx512f[];
+ static const size_t k_num_fpu_registers_avx512f;
+ static const size_t k_num_all_registers_avx512f;
+
typedef enum RegisterSetTag {
e_regSetALL = REGISTER_SET_ALL,
e_regSetGPR,
@@ -97,6 +103,7 @@ protected:
e_regSetWordSizeFPU = sizeof(FPU) / sizeof(int),
e_regSetWordSizeEXC = sizeof(EXC) / sizeof(int),
e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
+ e_regSetWordSizeAVX512f = sizeof(AVX512F) / sizeof(int),
e_regSetWordSizeDBG = sizeof(DBG) / sizeof(int)
} RegisterSetWordSize;
@@ -107,6 +114,7 @@ protected:
union {
FPU no_avx;
AVX avx;
+ AVX512F avx512f;
} fpu;
EXC exc;
DBG dbg;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h Mon Mar 5 16:27:41 2018
@@ -21,6 +21,7 @@
#define __i386_EXCEPTION_STATE 3
#define __i386_DEBUG_STATE 10
#define __i386_AVX_STATE 16
+#define __i386_AVX512F_STATE 19
typedef struct {
uint32_t __eax;
@@ -158,6 +159,69 @@ typedef struct {
__i386_xmm_reg __fpu_ymmh7;
} __i386_avx_state_t;
+typedef struct { uint8_t __ymm_reg[32]; } __i386_ymm_reg;
+typedef struct { uint8_t __opmask_reg[8]; } __i386_opmask_reg;
+
+typedef struct {
+ uint32_t __fpu_reserved[2];
+ __i386_fp_control_t __fpu_fcw;
+ __i386_fp_status_t __fpu_fsw;
+ uint8_t __fpu_ftw;
+ uint8_t __fpu_rsrv1;
+ uint16_t __fpu_fop;
+ uint32_t __fpu_ip;
+ uint16_t __fpu_cs;
+ uint16_t __fpu_rsrv2;
+ uint32_t __fpu_dp;
+ uint16_t __fpu_ds;
+ uint16_t __fpu_rsrv3;
+ uint32_t __fpu_mxcsr;
+ uint32_t __fpu_mxcsrmask;
+ __i386_mmst_reg __fpu_stmm0;
+ __i386_mmst_reg __fpu_stmm1;
+ __i386_mmst_reg __fpu_stmm2;
+ __i386_mmst_reg __fpu_stmm3;
+ __i386_mmst_reg __fpu_stmm4;
+ __i386_mmst_reg __fpu_stmm5;
+ __i386_mmst_reg __fpu_stmm6;
+ __i386_mmst_reg __fpu_stmm7;
+ __i386_xmm_reg __fpu_xmm0;
+ __i386_xmm_reg __fpu_xmm1;
+ __i386_xmm_reg __fpu_xmm2;
+ __i386_xmm_reg __fpu_xmm3;
+ __i386_xmm_reg __fpu_xmm4;
+ __i386_xmm_reg __fpu_xmm5;
+ __i386_xmm_reg __fpu_xmm6;
+ __i386_xmm_reg __fpu_xmm7;
+ uint8_t __fpu_rsrv4[14 * 16];
+ uint32_t __fpu_reserved1;
+ uint8_t __avx_reserved1[64];
+ __i386_xmm_reg __fpu_ymmh0;
+ __i386_xmm_reg __fpu_ymmh1;
+ __i386_xmm_reg __fpu_ymmh2;
+ __i386_xmm_reg __fpu_ymmh3;
+ __i386_xmm_reg __fpu_ymmh4;
+ __i386_xmm_reg __fpu_ymmh5;
+ __i386_xmm_reg __fpu_ymmh6;
+ __i386_xmm_reg __fpu_ymmh7;
+ __i386_opmask_reg __fpu_k0;
+ __i386_opmask_reg __fpu_k1;
+ __i386_opmask_reg __fpu_k2;
+ __i386_opmask_reg __fpu_k3;
+ __i386_opmask_reg __fpu_k4;
+ __i386_opmask_reg __fpu_k5;
+ __i386_opmask_reg __fpu_k6;
+ __i386_opmask_reg __fpu_k7;
+ __i386_ymm_reg __fpu_zmmh0;
+ __i386_ymm_reg __fpu_zmmh1;
+ __i386_ymm_reg __fpu_zmmh2;
+ __i386_ymm_reg __fpu_zmmh3;
+ __i386_ymm_reg __fpu_zmmh4;
+ __i386_ymm_reg __fpu_zmmh5;
+ __i386_ymm_reg __fpu_zmmh6;
+ __i386_ymm_reg __fpu_zmmh7;
+} __i386_avx512f_state_t;
+
typedef struct {
uint32_t __trapno;
uint32_t __err;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp Mon Mar 5 16:27:41 2018
@@ -119,6 +119,17 @@ extern "C" bool CPUHasAVX() {
return LogAVXAndReturn(g_has_avx, err, buffer);
}
+extern "C" bool CPUHasAVX512f() {
+ static AVXPresence g_has_avx512f = eAVXUnknown;
+ if (g_has_avx512f != eAVXUnknown)
+ return g_has_avx512f == eAVXPresent;
+
+ g_has_avx512f = DetectHardwareFeature("hw.optional.avx512f") ? eAVXPresent
+ : eAVXNotPresent;
+
+ return (g_has_avx512f == eAVXPresent);
+}
+
uint64_t DNBArchImplX86_64::GetPC(uint64_t failValue) {
// Get program counter
if (GetGPRState(false) == KERN_SUCCESS)
@@ -338,10 +349,82 @@ kern_return_t DNBArchImplX86_64::GetFPUS
for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
}
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (int i = 0; i < 8; ++i) {
+ m_state.context.fpu.avx512f.__fpu_k0.__opmask_reg[i] = '0';
+ m_state.context.fpu.avx512f.__fpu_k1.__opmask_reg[i] = '1';
+ m_state.context.fpu.avx512f.__fpu_k2.__opmask_reg[i] = '2';
+ m_state.context.fpu.avx512f.__fpu_k3.__opmask_reg[i] = '3';
+ m_state.context.fpu.avx512f.__fpu_k4.__opmask_reg[i] = '4';
+ m_state.context.fpu.avx512f.__fpu_k5.__opmask_reg[i] = '5';
+ m_state.context.fpu.avx512f.__fpu_k6.__opmask_reg[i] = '6';
+ m_state.context.fpu.avx512f.__fpu_k7.__opmask_reg[i] = '7';
+ }
+
+ for (int i = 0; i < 32; ++i) {
+ m_state.context.fpu.avx512f.__fpu_zmmh0.__ymm_reg[i] = '0';
+ m_state.context.fpu.avx512f.__fpu_zmmh1.__ymm_reg[i] = '1';
+ m_state.context.fpu.avx512f.__fpu_zmmh2.__ymm_reg[i] = '2';
+ m_state.context.fpu.avx512f.__fpu_zmmh3.__ymm_reg[i] = '3';
+ m_state.context.fpu.avx512f.__fpu_zmmh4.__ymm_reg[i] = '4';
+ m_state.context.fpu.avx512f.__fpu_zmmh5.__ymm_reg[i] = '5';
+ m_state.context.fpu.avx512f.__fpu_zmmh6.__ymm_reg[i] = '6';
+ m_state.context.fpu.avx512f.__fpu_zmmh7.__ymm_reg[i] = '7';
+ m_state.context.fpu.avx512f.__fpu_zmmh8.__ymm_reg[i] = '8';
+ m_state.context.fpu.avx512f.__fpu_zmmh9.__ymm_reg[i] = '9';
+ m_state.context.fpu.avx512f.__fpu_zmmh10.__ymm_reg[i] = 'A';
+ m_state.context.fpu.avx512f.__fpu_zmmh11.__ymm_reg[i] = 'B';
+ m_state.context.fpu.avx512f.__fpu_zmmh12.__ymm_reg[i] = 'C';
+ m_state.context.fpu.avx512f.__fpu_zmmh13.__ymm_reg[i] = 'D';
+ m_state.context.fpu.avx512f.__fpu_zmmh14.__ymm_reg[i] = 'E';
+ m_state.context.fpu.avx512f.__fpu_zmmh15.__ymm_reg[i] = 'F';
+ }
+ for (int i = 0; i < 64; ++i) {
+ m_state.context.fpu.avx512f.__fpu_zmm16.__zmm_reg[i] = 'G';
+ m_state.context.fpu.avx512f.__fpu_zmm17.__zmm_reg[i] = 'H';
+ m_state.context.fpu.avx512f.__fpu_zmm18.__zmm_reg[i] = 'I';
+ m_state.context.fpu.avx512f.__fpu_zmm19.__zmm_reg[i] = 'J';
+ m_state.context.fpu.avx512f.__fpu_zmm20.__zmm_reg[i] = 'K';
+ m_state.context.fpu.avx512f.__fpu_zmm21.__zmm_reg[i] = 'L';
+ m_state.context.fpu.avx512f.__fpu_zmm22.__zmm_reg[i] = 'M';
+ m_state.context.fpu.avx512f.__fpu_zmm23.__zmm_reg[i] = 'N';
+ m_state.context.fpu.avx512f.__fpu_zmm24.__zmm_reg[i] = 'O';
+ m_state.context.fpu.avx512f.__fpu_zmm25.__zmm_reg[i] = 'P';
+ m_state.context.fpu.avx512f.__fpu_zmm26.__zmm_reg[i] = 'Q';
+ m_state.context.fpu.avx512f.__fpu_zmm27.__zmm_reg[i] = 'R';
+ m_state.context.fpu.avx512f.__fpu_zmm28.__zmm_reg[i] = 'S';
+ m_state.context.fpu.avx512f.__fpu_zmm29.__zmm_reg[i] = 'T';
+ m_state.context.fpu.avx512f.__fpu_zmm30.__zmm_reg[i] = 'U';
+ m_state.context.fpu.avx512f.__fpu_zmm31.__zmm_reg[i] = 'V';
+ }
+ }
m_state.SetError(e_regSetFPU, Read, 0);
} else {
mach_msg_type_number_t count = e_regSetWordSizeFPU;
int flavor = __x86_64_FLOAT_STATE;
+ // On a machine with the AVX512 register set, a process only gets a
+ // full AVX512 register context after it uses the AVX512 registers;
+ // if the process has not yet triggered this change, trying to fetch
+ // the AVX512 registers will fail. Fall through to fetching the AVX
+ // registers.
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ count = e_regSetWordSizeAVX512f;
+ flavor = __x86_64_AVX512F_STATE;
+ m_state.SetError(e_regSetFPU, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), flavor,
+ (thread_state_t)&m_state.context.fpu,
+ &count));
+ DNBLogThreadedIf(LOG_THREAD,
+ "::thread_get_state (0x%4.4x, %u, &fpu, %u => 0x%8.8x",
+ m_thread->MachPortNumber(), flavor, (uint32_t)count,
+ m_state.GetError(e_regSetFPU, Read));
+
+ if (m_state.GetError(e_regSetFPU, Read) == KERN_SUCCESS)
+ return m_state.GetError(e_regSetFPU, Read);
+ else
+ DNBLogThreadedIf(LOG_THREAD,
+ "::thread_get_state attempted fetch of avx512 fpu regctx failed, will try fetching avx");
+ }
if (CPUHasAVX() || FORCE_AVX_REGS) {
count = e_regSetWordSizeAVX;
flavor = __x86_64_AVX_STATE;
@@ -413,6 +496,20 @@ kern_return_t DNBArchImplX86_64::SetFPUS
} else {
int flavor = __x86_64_FLOAT_STATE;
mach_msg_type_number_t count = e_regSetWordSizeFPU;
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ count = e_regSetWordSizeAVX512f;
+ flavor = __x86_64_AVX512F_STATE;
+ m_state.SetError(
+ e_regSetFPU, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), flavor,
+ (thread_state_t)&m_state.context.fpu, count));
+ if (m_state.GetError(e_regSetFPU, Write) == KERN_SUCCESS)
+ return m_state.GetError(e_regSetFPU, Write);
+ else
+ DNBLogThreadedIf(LOG_THREAD,
+ "::thread_get_state attempted save of avx512 fpu regctx failed, will try saving avx regctx");
+ }
+
if (CPUHasAVX() || FORCE_AVX_REGS) {
flavor = __x86_64_AVX_STATE;
count = e_regSetWordSizeAVX;
@@ -1019,6 +1116,46 @@ enum {
fpu_ymm13,
fpu_ymm14,
fpu_ymm15,
+ fpu_k0,
+ fpu_k1,
+ fpu_k2,
+ fpu_k3,
+ fpu_k4,
+ fpu_k5,
+ fpu_k6,
+ fpu_k7,
+ fpu_zmm0,
+ fpu_zmm1,
+ fpu_zmm2,
+ fpu_zmm3,
+ fpu_zmm4,
+ fpu_zmm5,
+ fpu_zmm6,
+ fpu_zmm7,
+ fpu_zmm8,
+ fpu_zmm9,
+ fpu_zmm10,
+ fpu_zmm11,
+ fpu_zmm12,
+ fpu_zmm13,
+ fpu_zmm14,
+ fpu_zmm15,
+ fpu_zmm16,
+ fpu_zmm17,
+ fpu_zmm18,
+ fpu_zmm19,
+ fpu_zmm20,
+ fpu_zmm21,
+ fpu_zmm22,
+ fpu_zmm23,
+ fpu_zmm24,
+ fpu_zmm25,
+ fpu_zmm26,
+ fpu_zmm27,
+ fpu_zmm28,
+ fpu_zmm29,
+ fpu_zmm30,
+ fpu_zmm31,
k_num_fpu_regs,
// Aliases
@@ -1095,7 +1232,47 @@ enum ehframe_dwarf_regnums {
ehframe_dwarf_ymm12 = ehframe_dwarf_xmm12,
ehframe_dwarf_ymm13 = ehframe_dwarf_xmm13,
ehframe_dwarf_ymm14 = ehframe_dwarf_xmm14,
- ehframe_dwarf_ymm15 = ehframe_dwarf_xmm15
+ ehframe_dwarf_ymm15 = ehframe_dwarf_xmm15,
+ ehframe_dwarf_zmm0 = ehframe_dwarf_xmm0,
+ ehframe_dwarf_zmm1 = ehframe_dwarf_xmm1,
+ ehframe_dwarf_zmm2 = ehframe_dwarf_xmm2,
+ ehframe_dwarf_zmm3 = ehframe_dwarf_xmm3,
+ ehframe_dwarf_zmm4 = ehframe_dwarf_xmm4,
+ ehframe_dwarf_zmm5 = ehframe_dwarf_xmm5,
+ ehframe_dwarf_zmm6 = ehframe_dwarf_xmm6,
+ ehframe_dwarf_zmm7 = ehframe_dwarf_xmm7,
+ ehframe_dwarf_zmm8 = ehframe_dwarf_xmm8,
+ ehframe_dwarf_zmm9 = ehframe_dwarf_xmm9,
+ ehframe_dwarf_zmm10 = ehframe_dwarf_xmm10,
+ ehframe_dwarf_zmm11 = ehframe_dwarf_xmm11,
+ ehframe_dwarf_zmm12 = ehframe_dwarf_xmm12,
+ ehframe_dwarf_zmm13 = ehframe_dwarf_xmm13,
+ ehframe_dwarf_zmm14 = ehframe_dwarf_xmm14,
+ ehframe_dwarf_zmm15 = ehframe_dwarf_xmm15,
+ ehframe_dwarf_zmm16 = 67,
+ ehframe_dwarf_zmm17,
+ ehframe_dwarf_zmm18,
+ ehframe_dwarf_zmm19,
+ ehframe_dwarf_zmm20,
+ ehframe_dwarf_zmm21,
+ ehframe_dwarf_zmm22,
+ ehframe_dwarf_zmm23,
+ ehframe_dwarf_zmm24,
+ ehframe_dwarf_zmm25,
+ ehframe_dwarf_zmm26,
+ ehframe_dwarf_zmm27,
+ ehframe_dwarf_zmm28,
+ ehframe_dwarf_zmm29,
+ ehframe_dwarf_zmm30,
+ ehframe_dwarf_zmm31,
+ ehframe_dwarf_k0 = 118,
+ ehframe_dwarf_k1,
+ ehframe_dwarf_k2,
+ ehframe_dwarf_k3,
+ ehframe_dwarf_k4,
+ ehframe_dwarf_k5,
+ ehframe_dwarf_k6,
+ ehframe_dwarf_k7,
};
enum debugserver_regnums {
@@ -1178,7 +1355,47 @@ enum debugserver_regnums {
debugserver_ymm12 = debugserver_xmm12,
debugserver_ymm13 = debugserver_xmm13,
debugserver_ymm14 = debugserver_xmm14,
- debugserver_ymm15 = debugserver_xmm15
+ debugserver_ymm15 = debugserver_xmm15,
+ debugserver_zmm0 = debugserver_xmm0,
+ debugserver_zmm1 = debugserver_xmm1,
+ debugserver_zmm2 = debugserver_xmm2,
+ debugserver_zmm3 = debugserver_xmm3,
+ debugserver_zmm4 = debugserver_xmm4,
+ debugserver_zmm5 = debugserver_xmm5,
+ debugserver_zmm6 = debugserver_xmm6,
+ debugserver_zmm7 = debugserver_xmm7,
+ debugserver_zmm8 = debugserver_xmm8,
+ debugserver_zmm9 = debugserver_xmm9,
+ debugserver_zmm10 = debugserver_xmm10,
+ debugserver_zmm11 = debugserver_xmm11,
+ debugserver_zmm12 = debugserver_xmm12,
+ debugserver_zmm13 = debugserver_xmm13,
+ debugserver_zmm14 = debugserver_xmm14,
+ debugserver_zmm15 = debugserver_xmm15,
+ debugserver_zmm16 = 67,
+ debugserver_zmm17 = 68,
+ debugserver_zmm18 = 69,
+ debugserver_zmm19 = 70,
+ debugserver_zmm20 = 71,
+ debugserver_zmm21 = 72,
+ debugserver_zmm22 = 73,
+ debugserver_zmm23 = 74,
+ debugserver_zmm24 = 75,
+ debugserver_zmm25 = 76,
+ debugserver_zmm26 = 77,
+ debugserver_zmm27 = 78,
+ debugserver_zmm28 = 79,
+ debugserver_zmm29 = 80,
+ debugserver_zmm30 = 81,
+ debugserver_zmm31 = 82,
+ debugserver_k0 = 118,
+ debugserver_k1 = 119,
+ debugserver_k2 = 120,
+ debugserver_k3 = 121,
+ debugserver_k4 = 122,
+ debugserver_k5 = 123,
+ debugserver_k6 = 124,
+ debugserver_k7 = 125,
};
#define GPR_OFFSET(reg) (offsetof(DNBArchImplX86_64::GPR, __##reg))
@@ -1188,10 +1405,14 @@ enum debugserver_regnums {
#define AVX_OFFSET(reg) \
(offsetof(DNBArchImplX86_64::AVX, __fpu_##reg) + \
offsetof(DNBArchImplX86_64::Context, fpu.avx))
+#define AVX512F_OFFSET(reg) \
+ (offsetof(DNBArchImplX86_64::AVX512F, __fpu_##reg) + \
+ offsetof(DNBArchImplX86_64::Context, fpu.avx512f))
#define EXC_OFFSET(reg) \
(offsetof(DNBArchImplX86_64::EXC, __##reg) + \
offsetof(DNBArchImplX86_64::Context, exc))
#define AVX_OFFSET_YMM(n) (AVX_OFFSET(ymmh0) + (32 * n))
+#define AVX512F_OFFSET_ZMM(n) (AVX512F_OFFSET(zmmh0) + (64 * n))
#define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg))
#define FPU_SIZE_UINT(reg) \
@@ -1201,6 +1422,7 @@ enum debugserver_regnums {
#define FPU_SIZE_XMM(reg) \
(sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg))
#define FPU_SIZE_YMM(reg) (32)
+#define FPU_SIZE_ZMM(reg) (64)
#define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg))
// These macros will auto define the register name, alt name, register size,
@@ -1638,6 +1860,183 @@ const DNBRegisterInfo DNBArchImplX86_64:
};
+static const char *g_contained_zmm0[] = {"zmm0", NULL};
+static const char *g_contained_zmm1[] = {"zmm1", NULL};
+static const char *g_contained_zmm2[] = {"zmm2", NULL};
+static const char *g_contained_zmm3[] = {"zmm3", NULL};
+static const char *g_contained_zmm4[] = {"zmm4", NULL};
+static const char *g_contained_zmm5[] = {"zmm5", NULL};
+static const char *g_contained_zmm6[] = {"zmm6", NULL};
+static const char *g_contained_zmm7[] = {"zmm7", NULL};
+static const char *g_contained_zmm8[] = {"zmm8", NULL};
+static const char *g_contained_zmm9[] = {"zmm9", NULL};
+static const char *g_contained_zmm10[] = {"zmm10", NULL};
+static const char *g_contained_zmm11[] = {"zmm11", NULL};
+static const char *g_contained_zmm12[] = {"zmm12", NULL};
+static const char *g_contained_zmm13[] = {"zmm13", NULL};
+static const char *g_contained_zmm14[] = {"zmm14", NULL};
+static const char *g_contained_zmm15[] = {"zmm15", NULL};
+
+#define STR(s) #s
+
+#define ZMM_REG_DEF(reg) \
+ { \
+ e_regSetFPU, fpu_zmm##reg, STR(zmm##reg), NULL, Vector, VectorOfUInt8, \
+ FPU_SIZE_ZMM(zmm##reg), AVX512F_OFFSET_ZMM(reg), \
+ ehframe_dwarf_zmm##reg, ehframe_dwarf_zmm##reg, -1U, \
+ debugserver_zmm##reg, NULL, NULL \
+ }
+
+#define YMM_REG_ALIAS(reg) \
+ { \
+ e_regSetFPU, fpu_ymm##reg, STR(ymm##reg), NULL, Vector, VectorOfUInt8, \
+ FPU_SIZE_YMM(ymm##reg), 0, ehframe_dwarf_ymm##reg, \
+ ehframe_dwarf_ymm##reg, -1U, debugserver_ymm##reg, \
+ g_contained_zmm##reg, NULL \
+ }
+
+#define XMM_REG_ALIAS(reg) \
+ { \
+ e_regSetFPU, fpu_xmm##reg, STR(xmm##reg), NULL, Vector, VectorOfUInt8, \
+ FPU_SIZE_XMM(xmm##reg), 0, ehframe_dwarf_xmm##reg, \
+ ehframe_dwarf_xmm##reg, -1U, debugserver_xmm##reg, \
+ g_contained_zmm##reg, NULL \
+ }
+
+#define AVX512_K_REG_DEF(reg) \
+ { \
+ e_regSetFPU, fpu_k##reg, STR(k##reg), NULL, Vector, VectorOfUInt8, 8, \
+ AVX512F_OFFSET(k##reg), ehframe_dwarf_k##reg, ehframe_dwarf_k##reg, \
+ -1U, debugserver_k##reg, NULL, NULL \
+ }
+
+const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_avx512f[] = {
+ {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
+ AVX_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
+ AVX_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
+ AVX_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
+ AVX_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
+ AVX_OFFSET(ip), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
+ AVX_OFFSET(cs), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
+ AVX_OFFSET(dp), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
+ AVX_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
+ AVX_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
+ FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
+ NULL},
+
+ {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), ehframe_dwarf_stmm0,
+ ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
+ {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), ehframe_dwarf_stmm1,
+ ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
+ {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), ehframe_dwarf_stmm2,
+ ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
+ {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), ehframe_dwarf_stmm3,
+ ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
+ {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), ehframe_dwarf_stmm4,
+ ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
+ {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), ehframe_dwarf_stmm5,
+ ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
+ {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), ehframe_dwarf_stmm6,
+ ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
+ {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), ehframe_dwarf_stmm7,
+ ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
+
+ AVX512_K_REG_DEF(0),
+ AVX512_K_REG_DEF(1),
+ AVX512_K_REG_DEF(2),
+ AVX512_K_REG_DEF(3),
+ AVX512_K_REG_DEF(4),
+ AVX512_K_REG_DEF(5),
+ AVX512_K_REG_DEF(6),
+ AVX512_K_REG_DEF(7),
+
+ ZMM_REG_DEF(0),
+ ZMM_REG_DEF(1),
+ ZMM_REG_DEF(2),
+ ZMM_REG_DEF(3),
+ ZMM_REG_DEF(4),
+ ZMM_REG_DEF(5),
+ ZMM_REG_DEF(6),
+ ZMM_REG_DEF(7),
+ ZMM_REG_DEF(8),
+ ZMM_REG_DEF(9),
+ ZMM_REG_DEF(10),
+ ZMM_REG_DEF(11),
+ ZMM_REG_DEF(12),
+ ZMM_REG_DEF(13),
+ ZMM_REG_DEF(14),
+ ZMM_REG_DEF(15),
+ ZMM_REG_DEF(16),
+ ZMM_REG_DEF(17),
+ ZMM_REG_DEF(18),
+ ZMM_REG_DEF(19),
+ ZMM_REG_DEF(20),
+ ZMM_REG_DEF(21),
+ ZMM_REG_DEF(22),
+ ZMM_REG_DEF(23),
+ ZMM_REG_DEF(24),
+ ZMM_REG_DEF(25),
+ ZMM_REG_DEF(26),
+ ZMM_REG_DEF(27),
+ ZMM_REG_DEF(28),
+ ZMM_REG_DEF(29),
+ ZMM_REG_DEF(30),
+ ZMM_REG_DEF(31),
+
+ YMM_REG_ALIAS(0),
+ YMM_REG_ALIAS(1),
+ YMM_REG_ALIAS(2),
+ YMM_REG_ALIAS(3),
+ YMM_REG_ALIAS(4),
+ YMM_REG_ALIAS(5),
+ YMM_REG_ALIAS(6),
+ YMM_REG_ALIAS(7),
+ YMM_REG_ALIAS(8),
+ YMM_REG_ALIAS(9),
+ YMM_REG_ALIAS(10),
+ YMM_REG_ALIAS(11),
+ YMM_REG_ALIAS(12),
+ YMM_REG_ALIAS(13),
+ YMM_REG_ALIAS(14),
+ YMM_REG_ALIAS(15),
+
+ XMM_REG_ALIAS(0),
+ XMM_REG_ALIAS(1),
+ XMM_REG_ALIAS(2),
+ XMM_REG_ALIAS(3),
+ XMM_REG_ALIAS(4),
+ XMM_REG_ALIAS(5),
+ XMM_REG_ALIAS(6),
+ XMM_REG_ALIAS(7),
+ XMM_REG_ALIAS(8),
+ XMM_REG_ALIAS(9),
+ XMM_REG_ALIAS(10),
+ XMM_REG_ALIAS(11),
+ XMM_REG_ALIAS(12),
+ XMM_REG_ALIAS(13),
+ XMM_REG_ALIAS(14),
+ XMM_REG_ALIAS(15),
+
+};
+
+
// Exception registers
const DNBRegisterInfo DNBArchImplX86_64::g_exc_registers[] = {
@@ -1662,6 +2061,10 @@ const size_t DNBArchImplX86_64::k_num_al
k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers;
const size_t DNBArchImplX86_64::k_num_all_registers_avx =
k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers;
+const size_t DNBArchImplX86_64::k_num_fpu_registers_avx512f =
+ sizeof(g_fpu_registers_avx512f) / sizeof(DNBRegisterInfo);
+const size_t DNBArchImplX86_64::k_num_all_registers_avx512f =
+ k_num_gpr_registers + k_num_fpu_registers_avx512f + k_num_exc_registers;
//----------------------------------------------------------------------
// Register set definitions. The first definitions at register set index
@@ -1681,6 +2084,13 @@ const DNBRegisterSetInfo DNBArchImplX86_
{"Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx},
{"Exception State Registers", g_exc_registers, k_num_exc_registers}};
+const DNBRegisterSetInfo DNBArchImplX86_64::g_reg_sets_avx512f[] = {
+ {"x86_64 Registers", NULL, k_num_all_registers_avx},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_fpu_registers_avx512f,
+ k_num_fpu_registers_avx512f},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
+
// Total number of register sets for this architecture
const size_t DNBArchImplX86_64::k_num_register_sets =
sizeof(g_reg_sets_avx) / sizeof(DNBRegisterSetInfo);
@@ -1702,6 +2112,8 @@ const DNBRegisterSetInfo *
DNBArchImplX86_64::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
*num_reg_sets = k_num_register_sets;
+ if (CPUHasAVX512f() || FORCE_AVX_REGS)
+ return g_reg_sets_avx512f;
if (CPUHasAVX() || FORCE_AVX_REGS)
return g_reg_sets_avx;
else
@@ -1765,6 +2177,8 @@ bool DNBArchImplX86_64::GetRegisterValue
case e_regSetFPU:
if (reg > fpu_xmm15 && !(CPUHasAVX() || FORCE_AVX_REGS))
return false;
+ if (reg > fpu_ymm15 && !(CPUHasAVX512f() || FORCE_AVX_REGS))
+ return false;
switch (reg) {
case fpu_fcw:
@@ -1853,6 +2267,59 @@ bool DNBArchImplX86_64::GetRegisterValue
memcpy((&value->value.uint8) + 16,
&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16);
return true;
+ case fpu_k0:
+ case fpu_k1:
+ case fpu_k2:
+ case fpu_k3:
+ case fpu_k4:
+ case fpu_k5:
+ case fpu_k6:
+ case fpu_k7:
+ memcpy((&value->value.uint8),
+ &m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0), 8);
+ return true;
+ case fpu_zmm0:
+ case fpu_zmm1:
+ case fpu_zmm2:
+ case fpu_zmm3:
+ case fpu_zmm4:
+ case fpu_zmm5:
+ case fpu_zmm6:
+ case fpu_zmm7:
+ case fpu_zmm8:
+ case fpu_zmm9:
+ case fpu_zmm10:
+ case fpu_zmm11:
+ case fpu_zmm12:
+ case fpu_zmm13:
+ case fpu_zmm14:
+ case fpu_zmm15:
+ memcpy(&value->value.uint8,
+ &m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0), 16);
+ memcpy((&value->value.uint8) + 16,
+ &m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0), 16);
+ memcpy((&value->value.uint8) + 32,
+ &m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0), 32);
+ return true;
+ case fpu_zmm16:
+ case fpu_zmm17:
+ case fpu_zmm18:
+ case fpu_zmm19:
+ case fpu_zmm20:
+ case fpu_zmm21:
+ case fpu_zmm22:
+ case fpu_zmm23:
+ case fpu_zmm24:
+ case fpu_zmm25:
+ case fpu_zmm26:
+ case fpu_zmm27:
+ case fpu_zmm28:
+ case fpu_zmm29:
+ case fpu_zmm30:
+ case fpu_zmm31:
+ memcpy(&value->value.uint8,
+ &m_state.context.fpu.avx512f.__fpu_zmm16 + (reg - fpu_zmm16), 64);
+ return true;
}
break;
@@ -1919,6 +2386,8 @@ bool DNBArchImplX86_64::SetRegisterValue
break;
if (reg > fpu_xmm15 && !(CPUHasAVX() || FORCE_AVX_REGS))
return false;
+ if (reg > fpu_ymm15 && !(CPUHasAVX512f() || FORCE_AVX_REGS))
+ return false;
case e_regSetFPU:
switch (reg) {
case fpu_fcw:
@@ -2019,6 +2488,59 @@ bool DNBArchImplX86_64::SetRegisterValue
memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0),
(&value->value.uint8) + 16, 16);
return true;
+ case fpu_k0:
+ case fpu_k1:
+ case fpu_k2:
+ case fpu_k3:
+ case fpu_k4:
+ case fpu_k5:
+ case fpu_k6:
+ case fpu_k7:
+ memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0),
+ &value->value.uint8, 8);
+ return true;
+ case fpu_zmm0:
+ case fpu_zmm1:
+ case fpu_zmm2:
+ case fpu_zmm3:
+ case fpu_zmm4:
+ case fpu_zmm5:
+ case fpu_zmm6:
+ case fpu_zmm7:
+ case fpu_zmm8:
+ case fpu_zmm9:
+ case fpu_zmm10:
+ case fpu_zmm11:
+ case fpu_zmm12:
+ case fpu_zmm13:
+ case fpu_zmm14:
+ case fpu_zmm15:
+ memcpy(&m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0),
+ &value->value.uint8, 16);
+ memcpy(&m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0),
+ &value->value.uint8 + 16, 16);
+ memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0),
+ &value->value.uint8 + 32, 32);
+ return true;
+ case fpu_zmm16:
+ case fpu_zmm17:
+ case fpu_zmm18:
+ case fpu_zmm19:
+ case fpu_zmm20:
+ case fpu_zmm21:
+ case fpu_zmm22:
+ case fpu_zmm23:
+ case fpu_zmm24:
+ case fpu_zmm25:
+ case fpu_zmm26:
+ case fpu_zmm27:
+ case fpu_zmm28:
+ case fpu_zmm29:
+ case fpu_zmm30:
+ case fpu_zmm31:
+ memcpy(&m_state.context.fpu.avx512f.__fpu_zmm16 + (reg - fpu_zmm16),
+ &value->value.uint8, 64);
+ return true;
}
break;
@@ -2049,7 +2571,12 @@ bool DNBArchImplX86_64::SetRegisterValue
uint32_t DNBArchImplX86_64::GetRegisterContextSize() {
static uint32_t g_cached_size = 0;
if (g_cached_size == 0) {
- if (CPUHasAVX() || FORCE_AVX_REGS) {
+ if (CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < k_num_fpu_registers_avx512f; ++i) {
+ if (g_fpu_registers_avx512f[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_avx512f[i].size;
+ }
+ } else if (CPUHasAVX() || FORCE_AVX_REGS) {
for (size_t i = 0; i < k_num_fpu_registers_avx; ++i) {
if (g_fpu_registers_avx[i].value_regs == NULL)
g_cached_size += g_fpu_registers_avx[i].size;
@@ -2121,6 +2648,13 @@ nub_size_t DNBArchImplX86_64::GetRegiste
p += 10;
}
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(p, &m_state.context.fpu.avx512f.__fpu_k0 + i, 8);
+ p += 8;
+ }
+ }
+
if (CPUHasAVX() || FORCE_AVX_REGS) {
// Interleave the XMM and YMMH registers to make the YMM registers
for (size_t i = 0; i < 16; ++i) {
@@ -2129,6 +2663,16 @@ nub_size_t DNBArchImplX86_64::GetRegiste
memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16);
p += 16;
}
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 16; ++i) {
+ memcpy(p, &m_state.context.fpu.avx512f.__fpu_zmmh0 + i, 32);
+ p += 32;
+ }
+ for (size_t i = 0; i < 16; ++i) {
+ memcpy(p, &m_state.context.fpu.avx512f.__fpu_zmm16 + i, 64);
+ p += 64;
+ }
+ }
} else {
// Copy the XMM registers in a single block
memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 16 * 16);
@@ -2186,6 +2730,13 @@ nub_size_t DNBArchImplX86_64::SetRegiste
p += 10;
}
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + i, p, 8);
+ p += 8;
+ }
+ }
+
if (CPUHasAVX() || FORCE_AVX_REGS) {
// Interleave the XMM and YMMH registers to make the YMM registers
for (size_t i = 0; i < 16; ++i) {
@@ -2194,6 +2745,16 @@ nub_size_t DNBArchImplX86_64::SetRegiste
memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16);
p += 16;
}
+ if(CPUHasAVX512f() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < 16; ++i) {
+ memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + i, p, 32);
+ p += 32;
+ }
+ for (size_t i = 0; i < 16; ++i) {
+ memcpy(&m_state.context.fpu.avx512f.__fpu_zmm16 + i, p, 64);
+ p += 64;
+ }
+ }
} else {
// Copy the XMM registers in a single block
memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 16 * 16);
Modified: lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h Mon Mar 5 16:27:41 2018
@@ -82,6 +82,12 @@ protected:
static const size_t k_num_all_registers_avx;
static const size_t k_num_register_sets;
+ typedef __x86_64_avx512f_state_t AVX512F;
+ static const DNBRegisterInfo g_fpu_registers_avx512f[];
+ static const DNBRegisterSetInfo g_reg_sets_avx512f[];
+ static const size_t k_num_fpu_registers_avx512f;
+ static const size_t k_num_all_registers_avx512f;
+
typedef enum RegisterSetTag {
e_regSetALL = REGISTER_SET_ALL,
e_regSetGPR,
@@ -96,6 +102,7 @@ protected:
e_regSetWordSizeFPU = sizeof(FPU) / sizeof(int),
e_regSetWordSizeEXC = sizeof(EXC) / sizeof(int),
e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
+ e_regSetWordSizeAVX512f = sizeof(AVX512F) / sizeof(int),
e_regSetWordSizeDBG = sizeof(DBG) / sizeof(int)
} RegisterSetWordSize;
@@ -106,6 +113,7 @@ protected:
union {
FPU no_avx;
AVX avx;
+ AVX512F avx512f;
} fpu;
EXC exc;
DBG dbg;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h Mon Mar 5 16:27:41 2018
@@ -22,6 +22,7 @@
#define __x86_64_EXCEPTION_STATE 6
#define __x86_64_DEBUG_STATE 11
#define __x86_64_AVX_STATE 17
+#define __x86_64_AVX512F_STATE 20
typedef struct {
uint64_t __rax;
@@ -188,6 +189,111 @@ typedef struct {
__x86_64_xmm_reg __fpu_ymmh15;
} __x86_64_avx_state_t;
+typedef struct { uint8_t __ymm_reg[32]; } __x86_64_ymm_reg;
+typedef struct { uint8_t __zmm_reg[64]; } __x86_64_zmm_reg;
+typedef struct { uint8_t __opmask_reg[8]; } __x86_64_opmask_reg;
+
+typedef struct {
+ uint32_t __fpu_reserved[2];
+ __x86_64_fp_control_t __fpu_fcw;
+ __x86_64_fp_status_t __fpu_fsw;
+ uint8_t __fpu_ftw;
+ uint8_t __fpu_rsrv1;
+ uint16_t __fpu_fop;
+ uint32_t __fpu_ip;
+ uint16_t __fpu_cs;
+ uint16_t __fpu_rsrv2;
+ uint32_t __fpu_dp;
+ uint16_t __fpu_ds;
+ uint16_t __fpu_rsrv3;
+ uint32_t __fpu_mxcsr;
+ uint32_t __fpu_mxcsrmask;
+ __x86_64_mmst_reg __fpu_stmm0;
+ __x86_64_mmst_reg __fpu_stmm1;
+ __x86_64_mmst_reg __fpu_stmm2;
+ __x86_64_mmst_reg __fpu_stmm3;
+ __x86_64_mmst_reg __fpu_stmm4;
+ __x86_64_mmst_reg __fpu_stmm5;
+ __x86_64_mmst_reg __fpu_stmm6;
+ __x86_64_mmst_reg __fpu_stmm7;
+ __x86_64_xmm_reg __fpu_xmm0;
+ __x86_64_xmm_reg __fpu_xmm1;
+ __x86_64_xmm_reg __fpu_xmm2;
+ __x86_64_xmm_reg __fpu_xmm3;
+ __x86_64_xmm_reg __fpu_xmm4;
+ __x86_64_xmm_reg __fpu_xmm5;
+ __x86_64_xmm_reg __fpu_xmm6;
+ __x86_64_xmm_reg __fpu_xmm7;
+ __x86_64_xmm_reg __fpu_xmm8;
+ __x86_64_xmm_reg __fpu_xmm9;
+ __x86_64_xmm_reg __fpu_xmm10;
+ __x86_64_xmm_reg __fpu_xmm11;
+ __x86_64_xmm_reg __fpu_xmm12;
+ __x86_64_xmm_reg __fpu_xmm13;
+ __x86_64_xmm_reg __fpu_xmm14;
+ __x86_64_xmm_reg __fpu_xmm15;
+ uint8_t __fpu_rsrv4[6 * 16];
+ uint32_t __fpu_reserved1;
+ uint8_t __avx_reserved1[64];
+ __x86_64_xmm_reg __fpu_ymmh0;
+ __x86_64_xmm_reg __fpu_ymmh1;
+ __x86_64_xmm_reg __fpu_ymmh2;
+ __x86_64_xmm_reg __fpu_ymmh3;
+ __x86_64_xmm_reg __fpu_ymmh4;
+ __x86_64_xmm_reg __fpu_ymmh5;
+ __x86_64_xmm_reg __fpu_ymmh6;
+ __x86_64_xmm_reg __fpu_ymmh7;
+ __x86_64_xmm_reg __fpu_ymmh8;
+ __x86_64_xmm_reg __fpu_ymmh9;
+ __x86_64_xmm_reg __fpu_ymmh10;
+ __x86_64_xmm_reg __fpu_ymmh11;
+ __x86_64_xmm_reg __fpu_ymmh12;
+ __x86_64_xmm_reg __fpu_ymmh13;
+ __x86_64_xmm_reg __fpu_ymmh14;
+ __x86_64_xmm_reg __fpu_ymmh15;
+ __x86_64_opmask_reg __fpu_k0;
+ __x86_64_opmask_reg __fpu_k1;
+ __x86_64_opmask_reg __fpu_k2;
+ __x86_64_opmask_reg __fpu_k3;
+ __x86_64_opmask_reg __fpu_k4;
+ __x86_64_opmask_reg __fpu_k5;
+ __x86_64_opmask_reg __fpu_k6;
+ __x86_64_opmask_reg __fpu_k7;
+ __x86_64_ymm_reg __fpu_zmmh0;
+ __x86_64_ymm_reg __fpu_zmmh1;
+ __x86_64_ymm_reg __fpu_zmmh2;
+ __x86_64_ymm_reg __fpu_zmmh3;
+ __x86_64_ymm_reg __fpu_zmmh4;
+ __x86_64_ymm_reg __fpu_zmmh5;
+ __x86_64_ymm_reg __fpu_zmmh6;
+ __x86_64_ymm_reg __fpu_zmmh7;
+ __x86_64_ymm_reg __fpu_zmmh8;
+ __x86_64_ymm_reg __fpu_zmmh9;
+ __x86_64_ymm_reg __fpu_zmmh10;
+ __x86_64_ymm_reg __fpu_zmmh11;
+ __x86_64_ymm_reg __fpu_zmmh12;
+ __x86_64_ymm_reg __fpu_zmmh13;
+ __x86_64_ymm_reg __fpu_zmmh14;
+ __x86_64_ymm_reg __fpu_zmmh15;
+ __x86_64_zmm_reg __fpu_zmm16;
+ __x86_64_zmm_reg __fpu_zmm17;
+ __x86_64_zmm_reg __fpu_zmm18;
+ __x86_64_zmm_reg __fpu_zmm19;
+ __x86_64_zmm_reg __fpu_zmm20;
+ __x86_64_zmm_reg __fpu_zmm21;
+ __x86_64_zmm_reg __fpu_zmm22;
+ __x86_64_zmm_reg __fpu_zmm23;
+ __x86_64_zmm_reg __fpu_zmm24;
+ __x86_64_zmm_reg __fpu_zmm25;
+ __x86_64_zmm_reg __fpu_zmm26;
+ __x86_64_zmm_reg __fpu_zmm27;
+ __x86_64_zmm_reg __fpu_zmm28;
+ __x86_64_zmm_reg __fpu_zmm29;
+ __x86_64_zmm_reg __fpu_zmm30;
+ __x86_64_zmm_reg __fpu_zmm31;
+
+} __x86_64_avx512f_state_t;
+
typedef struct {
uint32_t __trapno;
uint32_t __err;
Modified: lldb/trunk/tools/debugserver/source/RNBRemote.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/RNBRemote.cpp?rev=326756&r1=326755&r2=326756&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/RNBRemote.cpp (original)
+++ lldb/trunk/tools/debugserver/source/RNBRemote.cpp Mon Mar 5 16:27:41 2018
@@ -4651,6 +4651,8 @@ rnb_err_t RNBRemote::HandlePacket_qHostI
strm << "ostype:tvos;";
#elif defined(TARGET_OS_WATCH) && TARGET_OS_WATCH == 1
strm << "ostype:watchos;";
+#elif defined(TARGET_OS_BRIDGE) && TARGET_OS_BRIDGE == 1
+ strm << "ostype:bridgeos;";
#else
strm << "ostype:ios;";
#endif
@@ -6130,8 +6132,61 @@ rnb_err_t RNBRemote::HandlePacket_qProce
}
load_command_addr = load_command_addr + lc.cmdsize;
}
+
+// Test that the PLATFORM_* defines are available from mach-o/loader.h
+#if defined (PLATFORM_MACOS)
+ for (uint32_t i = 0; i < mh.ncmds && !os_handled; ++i)
+ {
+ nub_size_t bytes_read =
+ DNBProcessMemoryRead(pid, load_command_addr, sizeof(lc), &lc);
+ uint32_t raw_cmd = lc.cmd & ~LC_REQ_DYLD;
+ if (bytes_read != sizeof(lc))
+ break;
+
+ if (raw_cmd == LC_BUILD_VERSION)
+ {
+ uint32_t platform; // first field of 'struct build_version_command'
+ bytes_read = DNBProcessMemoryRead(pid, load_command_addr + 8, sizeof(platform), &platform);
+ if (bytes_read != sizeof (platform))
+ break;
+ switch (platform)
+ {
+ case PLATFORM_MACOS:
+ os_handled = true;
+ rep << "ostype:macosx;";
+ DNBLogThreadedIf(LOG_RNB_PROC,
+ "LC_BUILD_VERSION PLATFORM_MACOS -> 'ostype:macosx;'");
+ break;
+ case PLATFORM_IOS:
+ os_handled = true;
+ rep << "ostype:ios;";
+ DNBLogThreadedIf(LOG_RNB_PROC,
+ "LC_BUILD_VERSION PLATFORM_IOS -> 'ostype:ios;'");
+ break;
+ case PLATFORM_TVOS:
+ os_handled = true;
+ rep << "ostype:tvos;";
+ DNBLogThreadedIf(LOG_RNB_PROC,
+ "LC_BUILD_VERSION PLATFORM_TVOS -> 'ostype:tvos;'");
+ break;
+ case PLATFORM_WATCHOS:
+ os_handled = true;
+ rep << "ostype:watchos;";
+ DNBLogThreadedIf(LOG_RNB_PROC,
+ "LC_BUILD_VERSION PLATFORM_WATCHOS -> 'ostype:watchos;'");
+ break;
+ case PLATFORM_BRIDGEOS:
+ os_handled = true;
+ rep << "ostype:bridgeos;";
+ DNBLogThreadedIf(LOG_RNB_PROC,
+ "LC_BUILD_VERSION PLATFORM_BRIDGEOS -> 'ostype:bridgeos;'");
+ break;
+ }
}
-#endif
+ }
+#endif // PLATFORM_MACOS
+ }
+#endif // when compiling this on x86 targets
}
// If we weren't able to find the OS in a LC_VERSION_MIN load command, try
@@ -6145,6 +6200,8 @@ rnb_err_t RNBRemote::HandlePacket_qProce
rep << "ostype:tvos;";
#elif defined(TARGET_OS_WATCH) && TARGET_OS_WATCH == 1
rep << "ostype:watchos;";
+#elif defined(TARGET_OS_BRIDGE) && TARGET_OS_BRIDGE == 1
+ rep << "ostype:bridgeos;";
#else
rep << "ostype:ios;";
#endif
@@ -6196,6 +6253,8 @@ rnb_err_t RNBRemote::HandlePacket_qProce
rep << "ostype:tvos;";
#elif defined(TARGET_OS_WATCH) && TARGET_OS_WATCH == 1
rep << "ostype:watchos;";
+#elif defined(TARGET_OS_BRIDGE) && TARGET_OS_BRIDGE == 1
+ rep << "ostype:bridgeos;";
#else
rep << "ostype:ios;";
#endif
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