[Lldb-commits] [PATCH] D27088: [LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

[Nitesh Jain via Phabricator via lldb-commits]

nitesh.jain updated this revision to Diff 79881.
nitesh.jain added a comment.

Update diff as per suggestion.


https://reviews.llvm.org/D27088

Files:
  packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py


Index: packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
===================================================================
--- packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
+++ packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
@@ -12,7 +12,7 @@
 
 from __future__ import print_function
 
-
+import struct
 import unittest2
 import gdbremote_testcase
 import lldbgdbserverutils
@@ -26,6 +26,8 @@
 class LldbGdbServerTestCase(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
+    # Indicating SR.FR bit status
+    fr_flag = 1
 
     @debugserver_test
     def test_exe_starts_debugserver(self):
@@ -528,6 +530,25 @@
         self.set_inferior_startup_attach()
         self.qThreadInfo_matches_qC()
 
+    def updateRegInfoBitsize(self, reg_info, p_response):
+        if reg_info["name"] == "sr":
+            split_triple = self.triple.split("--",1)
+            if split_triple[0] == "mips64el" or split_triple == "mipsel":
+                # In case of little endian
+                # first decode the HEX ASCII bytes and then reverse it
+                # to get actual value of SR register
+                p_response = "".join(reversed([p_response[i:i+2] for i in range(0,
+                                    len(p_response),2)]))
+            # Check for SR.FR bit
+            # if SR.FR(26) == 0 && reg_info["format"] == "float"
+            # then reg_info["bitsize"] = 32
+            sr_value = int(p_response,16)
+            self.fr_flag = 1
+            self.fr_flag = (sr_value >> 26) & self.fr_flag
+
+        if reg_info["format"] == "float" and (self.fr_flag != 1):
+            reg_info["bitsize"] = 32
+
     def p_returns_correct_data_size_for_each_qRegisterInfo(self):
         procs = self.prep_debug_monitor_and_inferior()
         self.add_register_info_collection_packets()
@@ -565,6 +586,11 @@
             # Verify the response length.
             p_response = context.get("p_response")
             self.assertIsNotNone(p_response)
+            self.triple = lldb.DBG.GetSelectedPlatform().GetTriple()
+
+            if re.match("^mips",self.triple):
+                self.updateRegInfoBitsize(reg_info, p_response)
+
             self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
 
             # Increment loop


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