[Lldb-commits] [lldb] r280751 - *** This commit represents a complete reformatting of the LLDB source code
Kate Stone via lldb-commits
lldb-commits at lists.llvm.org
Tue Sep 6 13:58:36 PDT 2016
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachTask.mm
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachTask.mm?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachTask.mm (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachTask.mm Tue Sep 6 15:57:50 2016
@@ -23,7 +23,7 @@
#include <mach/mach_vm.h>
#import <sys/sysctl.h>
-#if defined (__APPLE__)
+#if defined(__APPLE__)
#include <pthread.h>
#include <sched.h>
#endif
@@ -36,25 +36,24 @@
// Project includes
#include "CFUtils.h"
#include "DNB.h"
+#include "DNBDataRef.h"
#include "DNBError.h"
#include "DNBLog.h"
#include "MachProcess.h"
-#include "DNBDataRef.h"
#ifdef WITH_SPRINGBOARD
#include <CoreFoundation/CoreFoundation.h>
-#include <SpringBoardServices/SpringBoardServer.h>
#include <SpringBoardServices/SBSWatchdogAssertion.h>
+#include <SpringBoardServices/SpringBoardServer.h>
#endif
#ifdef WITH_BKS
-extern "C"
-{
- #import <Foundation/Foundation.h>
- #import <BackBoardServices/BackBoardServices.h>
- #import <BackBoardServices/BKSWatchdogAssertion.h>
+extern "C" {
+#import <BackBoardServices/BKSWatchdogAssertion.h>
+#import <BackBoardServices/BackBoardServices.h>
+#import <Foundation/Foundation.h>
}
#endif
@@ -66,994 +65,922 @@ extern "C"
#include <pmsample.h>
#endif
-
//----------------------------------------------------------------------
// MachTask constructor
//----------------------------------------------------------------------
-MachTask::MachTask(MachProcess *process) :
- m_process (process),
- m_task (TASK_NULL),
- m_vm_memory (),
- m_exception_thread (0),
- m_exception_port (MACH_PORT_NULL)
-{
- memset(&m_exc_port_info, 0, sizeof(m_exc_port_info));
+MachTask::MachTask(MachProcess *process)
+ : m_process(process), m_task(TASK_NULL), m_vm_memory(),
+ m_exception_thread(0), m_exception_port(MACH_PORT_NULL) {
+ memset(&m_exc_port_info, 0, sizeof(m_exc_port_info));
}
//----------------------------------------------------------------------
// Destructor
//----------------------------------------------------------------------
-MachTask::~MachTask()
-{
- Clear();
-}
-
+MachTask::~MachTask() { Clear(); }
//----------------------------------------------------------------------
// MachTask::Suspend
//----------------------------------------------------------------------
-kern_return_t
-MachTask::Suspend()
-{
- DNBError err;
- task_t task = TaskPort();
- err = ::task_suspend (task);
- if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
- err.LogThreaded("::task_suspend ( target_task = 0x%4.4x )", task);
- return err.Error();
+kern_return_t MachTask::Suspend() {
+ DNBError err;
+ task_t task = TaskPort();
+ err = ::task_suspend(task);
+ if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
+ err.LogThreaded("::task_suspend ( target_task = 0x%4.4x )", task);
+ return err.Error();
}
-
//----------------------------------------------------------------------
// MachTask::Resume
//----------------------------------------------------------------------
-kern_return_t
-MachTask::Resume()
-{
- struct task_basic_info task_info;
- task_t task = TaskPort();
- if (task == TASK_NULL)
- return KERN_INVALID_ARGUMENT;
-
- DNBError err;
- err = BasicInfo(task, &task_info);
-
- if (err.Success())
- {
- // task_resume isn't counted like task_suspend calls are, are, so if the
- // task is not suspended, don't try and resume it since it is already
- // running
- if (task_info.suspend_count > 0)
- {
- err = ::task_resume (task);
- if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
- err.LogThreaded("::task_resume ( target_task = 0x%4.4x )", task);
- }
+kern_return_t MachTask::Resume() {
+ struct task_basic_info task_info;
+ task_t task = TaskPort();
+ if (task == TASK_NULL)
+ return KERN_INVALID_ARGUMENT;
+
+ DNBError err;
+ err = BasicInfo(task, &task_info);
+
+ if (err.Success()) {
+ // task_resume isn't counted like task_suspend calls are, are, so if the
+ // task is not suspended, don't try and resume it since it is already
+ // running
+ if (task_info.suspend_count > 0) {
+ err = ::task_resume(task);
+ if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
+ err.LogThreaded("::task_resume ( target_task = 0x%4.4x )", task);
}
- return err.Error();
+ }
+ return err.Error();
}
//----------------------------------------------------------------------
// MachTask::ExceptionPort
//----------------------------------------------------------------------
-mach_port_t
-MachTask::ExceptionPort() const
-{
- return m_exception_port;
-}
+mach_port_t MachTask::ExceptionPort() const { return m_exception_port; }
//----------------------------------------------------------------------
// MachTask::ExceptionPortIsValid
//----------------------------------------------------------------------
-bool
-MachTask::ExceptionPortIsValid() const
-{
- return MACH_PORT_VALID(m_exception_port);
+bool MachTask::ExceptionPortIsValid() const {
+ return MACH_PORT_VALID(m_exception_port);
}
-
//----------------------------------------------------------------------
// MachTask::Clear
//----------------------------------------------------------------------
-void
-MachTask::Clear()
-{
- // Do any cleanup needed for this task
- m_task = TASK_NULL;
- m_exception_thread = 0;
- m_exception_port = MACH_PORT_NULL;
-
+void MachTask::Clear() {
+ // Do any cleanup needed for this task
+ m_task = TASK_NULL;
+ m_exception_thread = 0;
+ m_exception_port = MACH_PORT_NULL;
}
-
//----------------------------------------------------------------------
// MachTask::SaveExceptionPortInfo
//----------------------------------------------------------------------
-kern_return_t
-MachTask::SaveExceptionPortInfo()
-{
- return m_exc_port_info.Save(TaskPort());
+kern_return_t MachTask::SaveExceptionPortInfo() {
+ return m_exc_port_info.Save(TaskPort());
}
//----------------------------------------------------------------------
// MachTask::RestoreExceptionPortInfo
//----------------------------------------------------------------------
-kern_return_t
-MachTask::RestoreExceptionPortInfo()
-{
- return m_exc_port_info.Restore(TaskPort());
+kern_return_t MachTask::RestoreExceptionPortInfo() {
+ return m_exc_port_info.Restore(TaskPort());
}
-
//----------------------------------------------------------------------
// MachTask::ReadMemory
//----------------------------------------------------------------------
-nub_size_t
-MachTask::ReadMemory (nub_addr_t addr, nub_size_t size, void *buf)
-{
- nub_size_t n = 0;
- task_t task = TaskPort();
- if (task != TASK_NULL)
- {
- n = m_vm_memory.Read(task, addr, buf, size);
-
- DNBLogThreadedIf(LOG_MEMORY, "MachTask::ReadMemory ( addr = 0x%8.8llx, size = %llu, buf = %p) => %llu bytes read", (uint64_t)addr, (uint64_t)size, buf, (uint64_t)n);
- if (DNBLogCheckLogBit(LOG_MEMORY_DATA_LONG) || (DNBLogCheckLogBit(LOG_MEMORY_DATA_SHORT) && size <= 8))
- {
- DNBDataRef data((uint8_t*)buf, n, false);
- data.Dump(0, static_cast<DNBDataRef::offset_t>(n), addr, DNBDataRef::TypeUInt8, 16);
- }
+nub_size_t MachTask::ReadMemory(nub_addr_t addr, nub_size_t size, void *buf) {
+ nub_size_t n = 0;
+ task_t task = TaskPort();
+ if (task != TASK_NULL) {
+ n = m_vm_memory.Read(task, addr, buf, size);
+
+ DNBLogThreadedIf(LOG_MEMORY, "MachTask::ReadMemory ( addr = 0x%8.8llx, "
+ "size = %llu, buf = %p) => %llu bytes read",
+ (uint64_t)addr, (uint64_t)size, buf, (uint64_t)n);
+ if (DNBLogCheckLogBit(LOG_MEMORY_DATA_LONG) ||
+ (DNBLogCheckLogBit(LOG_MEMORY_DATA_SHORT) && size <= 8)) {
+ DNBDataRef data((uint8_t *)buf, n, false);
+ data.Dump(0, static_cast<DNBDataRef::offset_t>(n), addr,
+ DNBDataRef::TypeUInt8, 16);
}
- return n;
+ }
+ return n;
}
-
//----------------------------------------------------------------------
// MachTask::WriteMemory
//----------------------------------------------------------------------
-nub_size_t
-MachTask::WriteMemory (nub_addr_t addr, nub_size_t size, const void *buf)
-{
- nub_size_t n = 0;
- task_t task = TaskPort();
- if (task != TASK_NULL)
- {
- n = m_vm_memory.Write(task, addr, buf, size);
- DNBLogThreadedIf(LOG_MEMORY, "MachTask::WriteMemory ( addr = 0x%8.8llx, size = %llu, buf = %p) => %llu bytes written", (uint64_t)addr, (uint64_t)size, buf, (uint64_t)n);
- if (DNBLogCheckLogBit(LOG_MEMORY_DATA_LONG) || (DNBLogCheckLogBit(LOG_MEMORY_DATA_SHORT) && size <= 8))
- {
- DNBDataRef data((uint8_t*)buf, n, false);
- data.Dump(0, static_cast<DNBDataRef::offset_t>(n), addr, DNBDataRef::TypeUInt8, 16);
- }
+nub_size_t MachTask::WriteMemory(nub_addr_t addr, nub_size_t size,
+ const void *buf) {
+ nub_size_t n = 0;
+ task_t task = TaskPort();
+ if (task != TASK_NULL) {
+ n = m_vm_memory.Write(task, addr, buf, size);
+ DNBLogThreadedIf(LOG_MEMORY, "MachTask::WriteMemory ( addr = 0x%8.8llx, "
+ "size = %llu, buf = %p) => %llu bytes written",
+ (uint64_t)addr, (uint64_t)size, buf, (uint64_t)n);
+ if (DNBLogCheckLogBit(LOG_MEMORY_DATA_LONG) ||
+ (DNBLogCheckLogBit(LOG_MEMORY_DATA_SHORT) && size <= 8)) {
+ DNBDataRef data((uint8_t *)buf, n, false);
+ data.Dump(0, static_cast<DNBDataRef::offset_t>(n), addr,
+ DNBDataRef::TypeUInt8, 16);
}
- return n;
+ }
+ return n;
}
//----------------------------------------------------------------------
// MachTask::MemoryRegionInfo
//----------------------------------------------------------------------
-int
-MachTask::GetMemoryRegionInfo (nub_addr_t addr, DNBRegionInfo *region_info)
-{
- task_t task = TaskPort();
- if (task == TASK_NULL)
- return -1;
-
- int ret = m_vm_memory.GetMemoryRegionInfo(task, addr, region_info);
- DNBLogThreadedIf(LOG_MEMORY, "MachTask::MemoryRegionInfo ( addr = 0x%8.8llx ) => %i (start = 0x%8.8llx, size = 0x%8.8llx, permissions = %u)",
- (uint64_t)addr,
- ret,
- (uint64_t)region_info->addr,
- (uint64_t)region_info->size,
- region_info->permissions);
- return ret;
-}
-
-#define TIME_VALUE_TO_TIMEVAL(a, r) do { \
-(r)->tv_sec = (a)->seconds; \
-(r)->tv_usec = (a)->microseconds; \
-} while (0)
+int MachTask::GetMemoryRegionInfo(nub_addr_t addr, DNBRegionInfo *region_info) {
+ task_t task = TaskPort();
+ if (task == TASK_NULL)
+ return -1;
+
+ int ret = m_vm_memory.GetMemoryRegionInfo(task, addr, region_info);
+ DNBLogThreadedIf(LOG_MEMORY, "MachTask::MemoryRegionInfo ( addr = 0x%8.8llx "
+ ") => %i (start = 0x%8.8llx, size = 0x%8.8llx, "
+ "permissions = %u)",
+ (uint64_t)addr, ret, (uint64_t)region_info->addr,
+ (uint64_t)region_info->size, region_info->permissions);
+ return ret;
+}
+
+#define TIME_VALUE_TO_TIMEVAL(a, r) \
+ do { \
+ (r)->tv_sec = (a)->seconds; \
+ (r)->tv_usec = (a)->microseconds; \
+ } while (0)
// We should consider moving this into each MacThread.
-static void get_threads_profile_data(DNBProfileDataScanType scanType, task_t task, nub_process_t pid, std::vector<uint64_t> &threads_id, std::vector<std::string> &threads_name, std::vector<uint64_t> &threads_used_usec)
-{
- kern_return_t kr;
- thread_act_array_t threads;
- mach_msg_type_number_t tcnt;
-
- kr = task_threads(task, &threads, &tcnt);
+static void get_threads_profile_data(DNBProfileDataScanType scanType,
+ task_t task, nub_process_t pid,
+ std::vector<uint64_t> &threads_id,
+ std::vector<std::string> &threads_name,
+ std::vector<uint64_t> &threads_used_usec) {
+ kern_return_t kr;
+ thread_act_array_t threads;
+ mach_msg_type_number_t tcnt;
+
+ kr = task_threads(task, &threads, &tcnt);
+ if (kr != KERN_SUCCESS)
+ return;
+
+ for (mach_msg_type_number_t i = 0; i < tcnt; i++) {
+ thread_identifier_info_data_t identifier_info;
+ mach_msg_type_number_t count = THREAD_IDENTIFIER_INFO_COUNT;
+ kr = ::thread_info(threads[i], THREAD_IDENTIFIER_INFO,
+ (thread_info_t)&identifier_info, &count);
if (kr != KERN_SUCCESS)
- return;
-
- for (mach_msg_type_number_t i = 0; i < tcnt; i++)
- {
- thread_identifier_info_data_t identifier_info;
- mach_msg_type_number_t count = THREAD_IDENTIFIER_INFO_COUNT;
- kr = ::thread_info(threads[i], THREAD_IDENTIFIER_INFO, (thread_info_t)&identifier_info, &count);
- if (kr != KERN_SUCCESS) continue;
-
- thread_basic_info_data_t basic_info;
- count = THREAD_BASIC_INFO_COUNT;
- kr = ::thread_info(threads[i], THREAD_BASIC_INFO, (thread_info_t)&basic_info, &count);
- if (kr != KERN_SUCCESS) continue;
-
- if ((basic_info.flags & TH_FLAGS_IDLE) == 0)
- {
- nub_thread_t tid = MachThread::GetGloballyUniqueThreadIDForMachPortID (threads[i]);
- threads_id.push_back(tid);
-
- if ((scanType & eProfileThreadName) && (identifier_info.thread_handle != 0))
- {
- struct proc_threadinfo proc_threadinfo;
- int len = ::proc_pidinfo(pid, PROC_PIDTHREADINFO, identifier_info.thread_handle, &proc_threadinfo, PROC_PIDTHREADINFO_SIZE);
- if (len && proc_threadinfo.pth_name[0])
- {
- threads_name.push_back(proc_threadinfo.pth_name);
- }
- else
- {
- threads_name.push_back("");
- }
- }
- else
- {
- threads_name.push_back("");
- }
- struct timeval tv;
- struct timeval thread_tv;
- TIME_VALUE_TO_TIMEVAL(&basic_info.user_time, &thread_tv);
- TIME_VALUE_TO_TIMEVAL(&basic_info.system_time, &tv);
- timeradd(&thread_tv, &tv, &thread_tv);
- uint64_t used_usec = thread_tv.tv_sec * 1000000ULL + thread_tv.tv_usec;
- threads_used_usec.push_back(used_usec);
- }
-
- mach_port_deallocate(mach_task_self(), threads[i]);
- }
- mach_vm_deallocate(mach_task_self(), (mach_vm_address_t)(uintptr_t)threads, tcnt * sizeof(*threads));
-}
+ continue;
-#define RAW_HEXBASE std::setfill('0') << std::hex << std::right
-#define DECIMAL std::dec << std::setfill(' ')
-std::string
-MachTask::GetProfileData (DNBProfileDataScanType scanType)
-{
- std::string result;
-
- static int32_t numCPU = -1;
- struct host_cpu_load_info host_info;
- if (scanType & eProfileHostCPU)
- {
- int32_t mib[] = {CTL_HW, HW_AVAILCPU};
- size_t len = sizeof(numCPU);
- if (numCPU == -1)
- {
- if (sysctl(mib, sizeof(mib) / sizeof(int32_t), &numCPU, &len, NULL, 0) != 0)
- return result;
- }
-
- mach_port_t localHost = mach_host_self();
- mach_msg_type_number_t count = HOST_CPU_LOAD_INFO_COUNT;
- kern_return_t kr = host_statistics(localHost, HOST_CPU_LOAD_INFO, (host_info_t)&host_info, &count);
- if (kr != KERN_SUCCESS)
- return result;
- }
-
- task_t task = TaskPort();
- if (task == TASK_NULL)
- return result;
-
- pid_t pid = m_process->ProcessID();
-
- struct task_basic_info task_info;
- DNBError err;
- err = BasicInfo(task, &task_info);
-
- if (!err.Success())
+ thread_basic_info_data_t basic_info;
+ count = THREAD_BASIC_INFO_COUNT;
+ kr = ::thread_info(threads[i], THREAD_BASIC_INFO,
+ (thread_info_t)&basic_info, &count);
+ if (kr != KERN_SUCCESS)
+ continue;
+
+ if ((basic_info.flags & TH_FLAGS_IDLE) == 0) {
+ nub_thread_t tid =
+ MachThread::GetGloballyUniqueThreadIDForMachPortID(threads[i]);
+ threads_id.push_back(tid);
+
+ if ((scanType & eProfileThreadName) &&
+ (identifier_info.thread_handle != 0)) {
+ struct proc_threadinfo proc_threadinfo;
+ int len = ::proc_pidinfo(pid, PROC_PIDTHREADINFO,
+ identifier_info.thread_handle,
+ &proc_threadinfo, PROC_PIDTHREADINFO_SIZE);
+ if (len && proc_threadinfo.pth_name[0]) {
+ threads_name.push_back(proc_threadinfo.pth_name);
+ } else {
+ threads_name.push_back("");
+ }
+ } else {
+ threads_name.push_back("");
+ }
+ struct timeval tv;
+ struct timeval thread_tv;
+ TIME_VALUE_TO_TIMEVAL(&basic_info.user_time, &thread_tv);
+ TIME_VALUE_TO_TIMEVAL(&basic_info.system_time, &tv);
+ timeradd(&thread_tv, &tv, &thread_tv);
+ uint64_t used_usec = thread_tv.tv_sec * 1000000ULL + thread_tv.tv_usec;
+ threads_used_usec.push_back(used_usec);
+ }
+
+ mach_port_deallocate(mach_task_self(), threads[i]);
+ }
+ mach_vm_deallocate(mach_task_self(), (mach_vm_address_t)(uintptr_t)threads,
+ tcnt * sizeof(*threads));
+}
+
+#define RAW_HEXBASE std::setfill('0') << std::hex << std::right
+#define DECIMAL std::dec << std::setfill(' ')
+std::string MachTask::GetProfileData(DNBProfileDataScanType scanType) {
+ std::string result;
+
+ static int32_t numCPU = -1;
+ struct host_cpu_load_info host_info;
+ if (scanType & eProfileHostCPU) {
+ int32_t mib[] = {CTL_HW, HW_AVAILCPU};
+ size_t len = sizeof(numCPU);
+ if (numCPU == -1) {
+ if (sysctl(mib, sizeof(mib) / sizeof(int32_t), &numCPU, &len, NULL, 0) !=
+ 0)
return result;
-
- uint64_t elapsed_usec = 0;
- uint64_t task_used_usec = 0;
- if (scanType & eProfileCPU)
- {
- // Get current used time.
- struct timeval current_used_time;
- struct timeval tv;
- TIME_VALUE_TO_TIMEVAL(&task_info.user_time, ¤t_used_time);
- TIME_VALUE_TO_TIMEVAL(&task_info.system_time, &tv);
- timeradd(¤t_used_time, &tv, ¤t_used_time);
- task_used_usec = current_used_time.tv_sec * 1000000ULL + current_used_time.tv_usec;
-
- struct timeval current_elapsed_time;
- int res = gettimeofday(¤t_elapsed_time, NULL);
- if (res == 0)
- {
- elapsed_usec = current_elapsed_time.tv_sec * 1000000ULL + current_elapsed_time.tv_usec;
- }
- }
-
- std::vector<uint64_t> threads_id;
- std::vector<std::string> threads_name;
- std::vector<uint64_t> threads_used_usec;
-
- if (scanType & eProfileThreadsCPU)
- {
- get_threads_profile_data(scanType, task, pid, threads_id, threads_name, threads_used_usec);
}
-
-#if defined (HOST_VM_INFO64_COUNT)
- vm_statistics64_data_t vminfo;
+
+ mach_port_t localHost = mach_host_self();
+ mach_msg_type_number_t count = HOST_CPU_LOAD_INFO_COUNT;
+ kern_return_t kr = host_statistics(localHost, HOST_CPU_LOAD_INFO,
+ (host_info_t)&host_info, &count);
+ if (kr != KERN_SUCCESS)
+ return result;
+ }
+
+ task_t task = TaskPort();
+ if (task == TASK_NULL)
+ return result;
+
+ pid_t pid = m_process->ProcessID();
+
+ struct task_basic_info task_info;
+ DNBError err;
+ err = BasicInfo(task, &task_info);
+
+ if (!err.Success())
+ return result;
+
+ uint64_t elapsed_usec = 0;
+ uint64_t task_used_usec = 0;
+ if (scanType & eProfileCPU) {
+ // Get current used time.
+ struct timeval current_used_time;
+ struct timeval tv;
+ TIME_VALUE_TO_TIMEVAL(&task_info.user_time, ¤t_used_time);
+ TIME_VALUE_TO_TIMEVAL(&task_info.system_time, &tv);
+ timeradd(¤t_used_time, &tv, ¤t_used_time);
+ task_used_usec =
+ current_used_time.tv_sec * 1000000ULL + current_used_time.tv_usec;
+
+ struct timeval current_elapsed_time;
+ int res = gettimeofday(¤t_elapsed_time, NULL);
+ if (res == 0) {
+ elapsed_usec = current_elapsed_time.tv_sec * 1000000ULL +
+ current_elapsed_time.tv_usec;
+ }
+ }
+
+ std::vector<uint64_t> threads_id;
+ std::vector<std::string> threads_name;
+ std::vector<uint64_t> threads_used_usec;
+
+ if (scanType & eProfileThreadsCPU) {
+ get_threads_profile_data(scanType, task, pid, threads_id, threads_name,
+ threads_used_usec);
+ }
+
+#if defined(HOST_VM_INFO64_COUNT)
+ vm_statistics64_data_t vminfo;
#else
- struct vm_statistics vminfo;
+ struct vm_statistics vminfo;
#endif
- uint64_t physical_memory;
- mach_vm_size_t rprvt = 0;
- mach_vm_size_t rsize = 0;
- mach_vm_size_t vprvt = 0;
- mach_vm_size_t vsize = 0;
- mach_vm_size_t dirty_size = 0;
- mach_vm_size_t purgeable = 0;
- mach_vm_size_t anonymous = 0;
- if (m_vm_memory.GetMemoryProfile(scanType, task, task_info, m_process->GetCPUType(), pid, vminfo, physical_memory, rprvt, rsize, vprvt, vsize, dirty_size, purgeable, anonymous))
- {
- std::ostringstream profile_data_stream;
-
- if (scanType & eProfileHostCPU)
- {
- profile_data_stream << "num_cpu:" << numCPU << ';';
- profile_data_stream << "host_user_ticks:" << host_info.cpu_ticks[CPU_STATE_USER] << ';';
- profile_data_stream << "host_sys_ticks:" << host_info.cpu_ticks[CPU_STATE_SYSTEM] << ';';
- profile_data_stream << "host_idle_ticks:" << host_info.cpu_ticks[CPU_STATE_IDLE] << ';';
- }
-
- if (scanType & eProfileCPU)
- {
- profile_data_stream << "elapsed_usec:" << elapsed_usec << ';';
- profile_data_stream << "task_used_usec:" << task_used_usec << ';';
- }
-
- if (scanType & eProfileThreadsCPU)
- {
- const size_t num_threads = threads_id.size();
- for (size_t i=0; i<num_threads; i++)
- {
- profile_data_stream << "thread_used_id:" << std::hex << threads_id[i] << std::dec << ';';
- profile_data_stream << "thread_used_usec:" << threads_used_usec[i] << ';';
-
- if (scanType & eProfileThreadName)
- {
- profile_data_stream << "thread_used_name:";
- const size_t len = threads_name[i].size();
- if (len)
- {
- const char *thread_name = threads_name[i].c_str();
- // Make sure that thread name doesn't interfere with our delimiter.
- profile_data_stream << RAW_HEXBASE << std::setw(2);
- const uint8_t *ubuf8 = (const uint8_t *)(thread_name);
- for (size_t j=0; j<len; j++)
- {
- profile_data_stream << (uint32_t)(ubuf8[j]);
- }
- // Reset back to DECIMAL.
- profile_data_stream << DECIMAL;
- }
- profile_data_stream << ';';
- }
- }
- }
-
- if (scanType & eProfileHostMemory)
- profile_data_stream << "total:" << physical_memory << ';';
-
- if (scanType & eProfileMemory)
- {
-#if defined (HOST_VM_INFO64_COUNT) && defined (_VM_PAGE_SIZE_H_)
- static vm_size_t pagesize = vm_kernel_page_size;
+ uint64_t physical_memory;
+ mach_vm_size_t rprvt = 0;
+ mach_vm_size_t rsize = 0;
+ mach_vm_size_t vprvt = 0;
+ mach_vm_size_t vsize = 0;
+ mach_vm_size_t dirty_size = 0;
+ mach_vm_size_t purgeable = 0;
+ mach_vm_size_t anonymous = 0;
+ if (m_vm_memory.GetMemoryProfile(scanType, task, task_info,
+ m_process->GetCPUType(), pid, vminfo,
+ physical_memory, rprvt, rsize, vprvt, vsize,
+ dirty_size, purgeable, anonymous)) {
+ std::ostringstream profile_data_stream;
+
+ if (scanType & eProfileHostCPU) {
+ profile_data_stream << "num_cpu:" << numCPU << ';';
+ profile_data_stream << "host_user_ticks:"
+ << host_info.cpu_ticks[CPU_STATE_USER] << ';';
+ profile_data_stream << "host_sys_ticks:"
+ << host_info.cpu_ticks[CPU_STATE_SYSTEM] << ';';
+ profile_data_stream << "host_idle_ticks:"
+ << host_info.cpu_ticks[CPU_STATE_IDLE] << ';';
+ }
+
+ if (scanType & eProfileCPU) {
+ profile_data_stream << "elapsed_usec:" << elapsed_usec << ';';
+ profile_data_stream << "task_used_usec:" << task_used_usec << ';';
+ }
+
+ if (scanType & eProfileThreadsCPU) {
+ const size_t num_threads = threads_id.size();
+ for (size_t i = 0; i < num_threads; i++) {
+ profile_data_stream << "thread_used_id:" << std::hex << threads_id[i]
+ << std::dec << ';';
+ profile_data_stream << "thread_used_usec:" << threads_used_usec[i]
+ << ';';
+
+ if (scanType & eProfileThreadName) {
+ profile_data_stream << "thread_used_name:";
+ const size_t len = threads_name[i].size();
+ if (len) {
+ const char *thread_name = threads_name[i].c_str();
+ // Make sure that thread name doesn't interfere with our delimiter.
+ profile_data_stream << RAW_HEXBASE << std::setw(2);
+ const uint8_t *ubuf8 = (const uint8_t *)(thread_name);
+ for (size_t j = 0; j < len; j++) {
+ profile_data_stream << (uint32_t)(ubuf8[j]);
+ }
+ // Reset back to DECIMAL.
+ profile_data_stream << DECIMAL;
+ }
+ profile_data_stream << ';';
+ }
+ }
+ }
+
+ if (scanType & eProfileHostMemory)
+ profile_data_stream << "total:" << physical_memory << ';';
+
+ if (scanType & eProfileMemory) {
+#if defined(HOST_VM_INFO64_COUNT) && defined(_VM_PAGE_SIZE_H_)
+ static vm_size_t pagesize = vm_kernel_page_size;
#else
- static vm_size_t pagesize;
- static bool calculated = false;
- if (!calculated)
- {
- calculated = true;
- pagesize = PageSize();
- }
-#endif
-
- /* Unused values. Optimized out for transfer performance.
- profile_data_stream << "wired:" << vminfo.wire_count * pagesize << ';';
- profile_data_stream << "active:" << vminfo.active_count * pagesize << ';';
- profile_data_stream << "inactive:" << vminfo.inactive_count * pagesize << ';';
- */
-#if defined (HOST_VM_INFO64_COUNT)
- // This mimicks Activity Monitor.
- uint64_t total_used_count = (physical_memory / pagesize) - (vminfo.free_count - vminfo.speculative_count) - vminfo.external_page_count - vminfo.purgeable_count;
+ static vm_size_t pagesize;
+ static bool calculated = false;
+ if (!calculated) {
+ calculated = true;
+ pagesize = PageSize();
+ }
+#endif
+
+/* Unused values. Optimized out for transfer performance.
+profile_data_stream << "wired:" << vminfo.wire_count * pagesize << ';';
+profile_data_stream << "active:" << vminfo.active_count * pagesize << ';';
+profile_data_stream << "inactive:" << vminfo.inactive_count * pagesize << ';';
+ */
+#if defined(HOST_VM_INFO64_COUNT)
+ // This mimicks Activity Monitor.
+ uint64_t total_used_count =
+ (physical_memory / pagesize) -
+ (vminfo.free_count - vminfo.speculative_count) -
+ vminfo.external_page_count - vminfo.purgeable_count;
#else
- uint64_t total_used_count = vminfo.wire_count + vminfo.inactive_count + vminfo.active_count;
+ uint64_t total_used_count =
+ vminfo.wire_count + vminfo.inactive_count + vminfo.active_count;
#endif
- profile_data_stream << "used:" << total_used_count * pagesize << ';';
- /* Unused values. Optimized out for transfer performance.
- profile_data_stream << "free:" << vminfo.free_count * pagesize << ';';
- */
-
- profile_data_stream << "rprvt:" << rprvt << ';';
- /* Unused values. Optimized out for transfer performance.
- profile_data_stream << "rsize:" << rsize << ';';
- profile_data_stream << "vprvt:" << vprvt << ';';
- profile_data_stream << "vsize:" << vsize << ';';
- */
-
- if (scanType & eProfileMemoryDirtyPage)
- profile_data_stream << "dirty:" << dirty_size << ';';
-
- if (scanType & eProfileMemoryAnonymous)
- {
- profile_data_stream << "purgeable:" << purgeable << ';';
- profile_data_stream << "anonymous:" << anonymous << ';';
- }
- }
-
- // proc_pid_rusage pm_sample_task_and_pid pm_energy_impact needs to be tested for weakness in Cab
+ profile_data_stream << "used:" << total_used_count * pagesize << ';';
+ /* Unused values. Optimized out for transfer performance.
+ profile_data_stream << "free:" << vminfo.free_count * pagesize << ';';
+ */
+
+ profile_data_stream << "rprvt:" << rprvt << ';';
+ /* Unused values. Optimized out for transfer performance.
+ profile_data_stream << "rsize:" << rsize << ';';
+ profile_data_stream << "vprvt:" << vprvt << ';';
+ profile_data_stream << "vsize:" << vsize << ';';
+ */
+
+ if (scanType & eProfileMemoryDirtyPage)
+ profile_data_stream << "dirty:" << dirty_size << ';';
+
+ if (scanType & eProfileMemoryAnonymous) {
+ profile_data_stream << "purgeable:" << purgeable << ';';
+ profile_data_stream << "anonymous:" << anonymous << ';';
+ }
+ }
+
+// proc_pid_rusage pm_sample_task_and_pid pm_energy_impact needs to be tested
+// for weakness in Cab
#ifdef LLDB_ENERGY
- if ((scanType & eProfileEnergy) && (pm_sample_task_and_pid != NULL))
- {
- struct rusage_info_v2 info;
- int rc = proc_pid_rusage(pid, RUSAGE_INFO_V2, (rusage_info_t *)&info);
- if (rc == 0)
- {
- uint64_t now = mach_absolute_time();
- pm_task_energy_data_t pm_energy;
- memset(&pm_energy, 0, sizeof(pm_energy));
- /*
- * Disable most features of pm_sample_pid. It will gather
- * network/GPU/WindowServer information; fill in the rest.
- */
- pm_sample_task_and_pid(task, pid, &pm_energy, now, PM_SAMPLE_ALL & ~PM_SAMPLE_NAME & ~PM_SAMPLE_INTERVAL & ~PM_SAMPLE_CPU & ~PM_SAMPLE_DISK);
- pm_energy.sti.total_user = info.ri_user_time;
- pm_energy.sti.total_system = info.ri_system_time;
- pm_energy.sti.task_interrupt_wakeups = info.ri_interrupt_wkups;
- pm_energy.sti.task_platform_idle_wakeups = info.ri_pkg_idle_wkups;
- pm_energy.diskio_bytesread = info.ri_diskio_bytesread;
- pm_energy.diskio_byteswritten = info.ri_diskio_byteswritten;
- pm_energy.pageins = info.ri_pageins;
-
- uint64_t total_energy = (uint64_t)(pm_energy_impact(&pm_energy) * NSEC_PER_SEC);
- //uint64_t process_age = now - info.ri_proc_start_abstime;
- //uint64_t avg_energy = 100.0 * (double)total_energy / (double)process_age;
-
- profile_data_stream << "energy:" << total_energy << ';';
- }
- }
-#endif
-
- profile_data_stream << "--end--;";
-
- result = profile_data_stream.str();
+ if ((scanType & eProfileEnergy) && (pm_sample_task_and_pid != NULL)) {
+ struct rusage_info_v2 info;
+ int rc = proc_pid_rusage(pid, RUSAGE_INFO_V2, (rusage_info_t *)&info);
+ if (rc == 0) {
+ uint64_t now = mach_absolute_time();
+ pm_task_energy_data_t pm_energy;
+ memset(&pm_energy, 0, sizeof(pm_energy));
+ /*
+ * Disable most features of pm_sample_pid. It will gather
+ * network/GPU/WindowServer information; fill in the rest.
+ */
+ pm_sample_task_and_pid(task, pid, &pm_energy, now,
+ PM_SAMPLE_ALL & ~PM_SAMPLE_NAME &
+ ~PM_SAMPLE_INTERVAL & ~PM_SAMPLE_CPU &
+ ~PM_SAMPLE_DISK);
+ pm_energy.sti.total_user = info.ri_user_time;
+ pm_energy.sti.total_system = info.ri_system_time;
+ pm_energy.sti.task_interrupt_wakeups = info.ri_interrupt_wkups;
+ pm_energy.sti.task_platform_idle_wakeups = info.ri_pkg_idle_wkups;
+ pm_energy.diskio_bytesread = info.ri_diskio_bytesread;
+ pm_energy.diskio_byteswritten = info.ri_diskio_byteswritten;
+ pm_energy.pageins = info.ri_pageins;
+
+ uint64_t total_energy =
+ (uint64_t)(pm_energy_impact(&pm_energy) * NSEC_PER_SEC);
+ // uint64_t process_age = now - info.ri_proc_start_abstime;
+ // uint64_t avg_energy = 100.0 * (double)total_energy /
+ // (double)process_age;
+
+ profile_data_stream << "energy:" << total_energy << ';';
+ }
}
-
- return result;
-}
+#endif
+ profile_data_stream << "--end--;";
+
+ result = profile_data_stream.str();
+ }
+
+ return result;
+}
//----------------------------------------------------------------------
// MachTask::TaskPortForProcessID
//----------------------------------------------------------------------
-task_t
-MachTask::TaskPortForProcessID (DNBError &err, bool force)
-{
- if (((m_task == TASK_NULL) || force) && m_process != NULL)
- m_task = MachTask::TaskPortForProcessID(m_process->ProcessID(), err);
- return m_task;
+task_t MachTask::TaskPortForProcessID(DNBError &err, bool force) {
+ if (((m_task == TASK_NULL) || force) && m_process != NULL)
+ m_task = MachTask::TaskPortForProcessID(m_process->ProcessID(), err);
+ return m_task;
}
//----------------------------------------------------------------------
// MachTask::TaskPortForProcessID
//----------------------------------------------------------------------
-task_t
-MachTask::TaskPortForProcessID (pid_t pid, DNBError &err, uint32_t num_retries, uint32_t usec_interval)
-{
- if (pid != INVALID_NUB_PROCESS)
- {
- DNBError err;
- mach_port_t task_self = mach_task_self ();
- task_t task = TASK_NULL;
- for (uint32_t i=0; i<num_retries; i++)
- {
- err = ::task_for_pid ( task_self, pid, &task);
-
- if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
- {
- char str[1024];
- ::snprintf (str,
- sizeof(str),
- "::task_for_pid ( target_tport = 0x%4.4x, pid = %d, &task ) => err = 0x%8.8x (%s)",
- task_self,
- pid,
- err.Error(),
- err.AsString() ? err.AsString() : "success");
- if (err.Fail())
- err.SetErrorString(str);
- err.LogThreaded(str);
- }
+task_t MachTask::TaskPortForProcessID(pid_t pid, DNBError &err,
+ uint32_t num_retries,
+ uint32_t usec_interval) {
+ if (pid != INVALID_NUB_PROCESS) {
+ DNBError err;
+ mach_port_t task_self = mach_task_self();
+ task_t task = TASK_NULL;
+ for (uint32_t i = 0; i < num_retries; i++) {
+ err = ::task_for_pid(task_self, pid, &task);
+
+ if (DNBLogCheckLogBit(LOG_TASK) || err.Fail()) {
+ char str[1024];
+ ::snprintf(str, sizeof(str), "::task_for_pid ( target_tport = 0x%4.4x, "
+ "pid = %d, &task ) => err = 0x%8.8x (%s)",
+ task_self, pid, err.Error(),
+ err.AsString() ? err.AsString() : "success");
+ if (err.Fail())
+ err.SetErrorString(str);
+ err.LogThreaded(str);
+ }
- if (err.Success())
- return task;
+ if (err.Success())
+ return task;
- // Sleep a bit and try again
- ::usleep (usec_interval);
- }
+ // Sleep a bit and try again
+ ::usleep(usec_interval);
}
- return TASK_NULL;
+ }
+ return TASK_NULL;
}
-
//----------------------------------------------------------------------
// MachTask::BasicInfo
//----------------------------------------------------------------------
-kern_return_t
-MachTask::BasicInfo(struct task_basic_info *info)
-{
- return BasicInfo (TaskPort(), info);
+kern_return_t MachTask::BasicInfo(struct task_basic_info *info) {
+ return BasicInfo(TaskPort(), info);
}
//----------------------------------------------------------------------
// MachTask::BasicInfo
//----------------------------------------------------------------------
-kern_return_t
-MachTask::BasicInfo(task_t task, struct task_basic_info *info)
-{
- if (info == NULL)
- return KERN_INVALID_ARGUMENT;
-
- DNBError err;
- mach_msg_type_number_t count = TASK_BASIC_INFO_COUNT;
- err = ::task_info (task, TASK_BASIC_INFO, (task_info_t)info, &count);
- const bool log_process = DNBLogCheckLogBit(LOG_TASK);
- if (log_process || err.Fail())
- err.LogThreaded("::task_info ( target_task = 0x%4.4x, flavor = TASK_BASIC_INFO, task_info_out => %p, task_info_outCnt => %u )", task, info, count);
- if (DNBLogCheckLogBit(LOG_TASK) && DNBLogCheckLogBit(LOG_VERBOSE) && err.Success())
- {
- float user = (float)info->user_time.seconds + (float)info->user_time.microseconds / 1000000.0f;
- float system = (float)info->user_time.seconds + (float)info->user_time.microseconds / 1000000.0f;
- DNBLogThreaded ("task_basic_info = { suspend_count = %i, virtual_size = 0x%8.8llx, resident_size = 0x%8.8llx, user_time = %f, system_time = %f }",
- info->suspend_count,
- (uint64_t)info->virtual_size,
- (uint64_t)info->resident_size,
- user,
- system);
- }
- return err.Error();
+kern_return_t MachTask::BasicInfo(task_t task, struct task_basic_info *info) {
+ if (info == NULL)
+ return KERN_INVALID_ARGUMENT;
+
+ DNBError err;
+ mach_msg_type_number_t count = TASK_BASIC_INFO_COUNT;
+ err = ::task_info(task, TASK_BASIC_INFO, (task_info_t)info, &count);
+ const bool log_process = DNBLogCheckLogBit(LOG_TASK);
+ if (log_process || err.Fail())
+ err.LogThreaded("::task_info ( target_task = 0x%4.4x, flavor = "
+ "TASK_BASIC_INFO, task_info_out => %p, task_info_outCnt => "
+ "%u )",
+ task, info, count);
+ if (DNBLogCheckLogBit(LOG_TASK) && DNBLogCheckLogBit(LOG_VERBOSE) &&
+ err.Success()) {
+ float user = (float)info->user_time.seconds +
+ (float)info->user_time.microseconds / 1000000.0f;
+ float system = (float)info->user_time.seconds +
+ (float)info->user_time.microseconds / 1000000.0f;
+ DNBLogThreaded("task_basic_info = { suspend_count = %i, virtual_size = "
+ "0x%8.8llx, resident_size = 0x%8.8llx, user_time = %f, "
+ "system_time = %f }",
+ info->suspend_count, (uint64_t)info->virtual_size,
+ (uint64_t)info->resident_size, user, system);
+ }
+ return err.Error();
}
-
//----------------------------------------------------------------------
// MachTask::IsValid
//
// Returns true if a task is a valid task port for a current process.
//----------------------------------------------------------------------
-bool
-MachTask::IsValid () const
-{
- return MachTask::IsValid(TaskPort());
-}
+bool MachTask::IsValid() const { return MachTask::IsValid(TaskPort()); }
//----------------------------------------------------------------------
// MachTask::IsValid
//
// Returns true if a task is a valid task port for a current process.
//----------------------------------------------------------------------
-bool
-MachTask::IsValid (task_t task)
-{
- if (task != TASK_NULL)
- {
- struct task_basic_info task_info;
- return BasicInfo(task, &task_info) == KERN_SUCCESS;
- }
- return false;
-}
-
-
-bool
-MachTask::StartExceptionThread(DNBError &err)
-{
- DNBLogThreadedIf(LOG_EXCEPTIONS, "MachTask::%s ( )", __FUNCTION__);
-
- task_t task = TaskPortForProcessID(err);
- if (MachTask::IsValid(task))
- {
- // Got the mach port for the current process
- mach_port_t task_self = mach_task_self ();
-
- // Allocate an exception port that we will use to track our child process
- err = ::mach_port_allocate (task_self, MACH_PORT_RIGHT_RECEIVE, &m_exception_port);
- if (err.Fail())
- return false;
-
- // Add the ability to send messages on the new exception port
- err = ::mach_port_insert_right (task_self, m_exception_port, m_exception_port, MACH_MSG_TYPE_MAKE_SEND);
- if (err.Fail())
- return false;
-
- // Save the original state of the exception ports for our child process
- SaveExceptionPortInfo();
-
- // We weren't able to save the info for our exception ports, we must stop...
- if (m_exc_port_info.mask == 0)
- {
- err.SetErrorString("failed to get exception port info");
- return false;
- }
-
- // Set the ability to get all exceptions on this port
- err = ::task_set_exception_ports (task, m_exc_port_info.mask, m_exception_port, EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES, THREAD_STATE_NONE);
- if (DNBLogCheckLogBit(LOG_EXCEPTIONS) || err.Fail())
- {
- err.LogThreaded("::task_set_exception_ports ( task = 0x%4.4x, exception_mask = 0x%8.8x, new_port = 0x%4.4x, behavior = 0x%8.8x, new_flavor = 0x%8.8x )",
- task,
- m_exc_port_info.mask,
- m_exception_port,
- (EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES),
- THREAD_STATE_NONE);
- }
-
- if (err.Fail())
- return false;
-
- // Create the exception thread
- err = ::pthread_create (&m_exception_thread, NULL, MachTask::ExceptionThread, this);
- return err.Success();
- }
- else
- {
- DNBLogError("MachTask::%s (): task invalid, exception thread start failed.", __FUNCTION__);
- }
- return false;
-}
-
-kern_return_t
-MachTask::ShutDownExcecptionThread()
-{
- DNBError err;
-
- err = RestoreExceptionPortInfo();
+bool MachTask::IsValid(task_t task) {
+ if (task != TASK_NULL) {
+ struct task_basic_info task_info;
+ return BasicInfo(task, &task_info) == KERN_SUCCESS;
+ }
+ return false;
+}
+
+bool MachTask::StartExceptionThread(DNBError &err) {
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "MachTask::%s ( )", __FUNCTION__);
+
+ task_t task = TaskPortForProcessID(err);
+ if (MachTask::IsValid(task)) {
+ // Got the mach port for the current process
+ mach_port_t task_self = mach_task_self();
+
+ // Allocate an exception port that we will use to track our child process
+ err = ::mach_port_allocate(task_self, MACH_PORT_RIGHT_RECEIVE,
+ &m_exception_port);
+ if (err.Fail())
+ return false;
+
+ // Add the ability to send messages on the new exception port
+ err = ::mach_port_insert_right(task_self, m_exception_port,
+ m_exception_port, MACH_MSG_TYPE_MAKE_SEND);
+ if (err.Fail())
+ return false;
+
+ // Save the original state of the exception ports for our child process
+ SaveExceptionPortInfo();
+
+ // We weren't able to save the info for our exception ports, we must stop...
+ if (m_exc_port_info.mask == 0) {
+ err.SetErrorString("failed to get exception port info");
+ return false;
+ }
+
+ // Set the ability to get all exceptions on this port
+ err = ::task_set_exception_ports(
+ task, m_exc_port_info.mask, m_exception_port,
+ EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES, THREAD_STATE_NONE);
+ if (DNBLogCheckLogBit(LOG_EXCEPTIONS) || err.Fail()) {
+ err.LogThreaded("::task_set_exception_ports ( task = 0x%4.4x, "
+ "exception_mask = 0x%8.8x, new_port = 0x%4.4x, behavior "
+ "= 0x%8.8x, new_flavor = 0x%8.8x )",
+ task, m_exc_port_info.mask, m_exception_port,
+ (EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES),
+ THREAD_STATE_NONE);
+ }
+
+ if (err.Fail())
+ return false;
+
+ // Create the exception thread
+ err = ::pthread_create(&m_exception_thread, NULL, MachTask::ExceptionThread,
+ this);
+ return err.Success();
+ } else {
+ DNBLogError("MachTask::%s (): task invalid, exception thread start failed.",
+ __FUNCTION__);
+ }
+ return false;
+}
+
+kern_return_t MachTask::ShutDownExcecptionThread() {
+ DNBError err;
+
+ err = RestoreExceptionPortInfo();
+
+ // NULL our our exception port and let our exception thread exit
+ mach_port_t exception_port = m_exception_port;
+ m_exception_port = 0;
+
+ err.SetError(::pthread_cancel(m_exception_thread), DNBError::POSIX);
+ if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
+ err.LogThreaded("::pthread_cancel ( thread = %p )", m_exception_thread);
+
+ err.SetError(::pthread_join(m_exception_thread, NULL), DNBError::POSIX);
+ if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
+ err.LogThreaded("::pthread_join ( thread = %p, value_ptr = NULL)",
+ m_exception_thread);
+
+ // Deallocate our exception port that we used to track our child process
+ mach_port_t task_self = mach_task_self();
+ err = ::mach_port_deallocate(task_self, exception_port);
+ if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
+ err.LogThreaded("::mach_port_deallocate ( task = 0x%4.4x, name = 0x%4.4x )",
+ task_self, exception_port);
- // NULL our our exception port and let our exception thread exit
- mach_port_t exception_port = m_exception_port;
- m_exception_port = 0;
-
- err.SetError(::pthread_cancel(m_exception_thread), DNBError::POSIX);
- if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
- err.LogThreaded("::pthread_cancel ( thread = %p )", m_exception_thread);
-
- err.SetError(::pthread_join(m_exception_thread, NULL), DNBError::POSIX);
- if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
- err.LogThreaded("::pthread_join ( thread = %p, value_ptr = NULL)", m_exception_thread);
-
- // Deallocate our exception port that we used to track our child process
- mach_port_t task_self = mach_task_self ();
- err = ::mach_port_deallocate (task_self, exception_port);
- if (DNBLogCheckLogBit(LOG_TASK) || err.Fail())
- err.LogThreaded("::mach_port_deallocate ( task = 0x%4.4x, name = 0x%4.4x )", task_self, exception_port);
-
- return err.Error();
+ return err.Error();
}
+void *MachTask::ExceptionThread(void *arg) {
+ if (arg == NULL)
+ return NULL;
-void *
-MachTask::ExceptionThread (void *arg)
-{
- if (arg == NULL)
- return NULL;
-
- MachTask *mach_task = (MachTask*) arg;
- MachProcess *mach_proc = mach_task->Process();
- DNBLogThreadedIf(LOG_EXCEPTIONS, "MachTask::%s ( arg = %p ) starting thread...", __FUNCTION__, arg);
-
-#if defined (__APPLE__)
- pthread_setname_np ("exception monitoring thread");
-#if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
- struct sched_param thread_param;
- int thread_sched_policy;
- if (pthread_getschedparam(pthread_self(), &thread_sched_policy, &thread_param) == 0)
- {
- thread_param.sched_priority = 47;
- pthread_setschedparam(pthread_self(), thread_sched_policy, &thread_param);
- }
-#endif
-#endif
-
- // We keep a count of the number of consecutive exceptions received so
- // we know to grab all exceptions without a timeout. We do this to get a
- // bunch of related exceptions on our exception port so we can process
- // then together. When we have multiple threads, we can get an exception
- // per thread and they will come in consecutively. The main loop in this
- // thread can stop periodically if needed to service things related to this
- // process.
- // flag set in the options, so we will wait forever for an exception on
- // our exception port. After we get one exception, we then will use the
- // MACH_RCV_TIMEOUT option with a zero timeout to grab all other current
- // exceptions for our process. After we have received the last pending
- // exception, we will get a timeout which enables us to then notify
- // our main thread that we have an exception bundle available. We then wait
- // for the main thread to tell this exception thread to start trying to get
- // exceptions messages again and we start again with a mach_msg read with
- // infinite timeout.
- uint32_t num_exceptions_received = 0;
- DNBError err;
- task_t task = mach_task->TaskPort();
- mach_msg_timeout_t periodic_timeout = 0;
-
-#if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
- mach_msg_timeout_t watchdog_elapsed = 0;
- mach_msg_timeout_t watchdog_timeout = 60 * 1000;
- pid_t pid = mach_proc->ProcessID();
- CFReleaser<SBSWatchdogAssertionRef> watchdog;
-
- if (mach_proc->ProcessUsingSpringBoard())
- {
- // Request a renewal for every 60 seconds if we attached using SpringBoard
- watchdog.reset(::SBSWatchdogAssertionCreateForPID(NULL, pid, 60));
- DNBLogThreadedIf(LOG_TASK, "::SBSWatchdogAssertionCreateForPID (NULL, %4.4x, 60 ) => %p", pid, watchdog.get());
-
- if (watchdog.get())
- {
- ::SBSWatchdogAssertionRenew (watchdog.get());
-
- CFTimeInterval watchdogRenewalInterval = ::SBSWatchdogAssertionGetRenewalInterval (watchdog.get());
- DNBLogThreadedIf(LOG_TASK, "::SBSWatchdogAssertionGetRenewalInterval ( %p ) => %g seconds", watchdog.get(), watchdogRenewalInterval);
- if (watchdogRenewalInterval > 0.0)
- {
- watchdog_timeout = (mach_msg_timeout_t)watchdogRenewalInterval * 1000;
- if (watchdog_timeout > 3000)
- watchdog_timeout -= 1000; // Give us a second to renew our timeout
- else if (watchdog_timeout > 1000)
- watchdog_timeout -= 250; // Give us a quarter of a second to renew our timeout
- }
- }
- if (periodic_timeout == 0 || periodic_timeout > watchdog_timeout)
- periodic_timeout = watchdog_timeout;
- }
-#endif // #if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
+ MachTask *mach_task = (MachTask *)arg;
+ MachProcess *mach_proc = mach_task->Process();
+ DNBLogThreadedIf(LOG_EXCEPTIONS,
+ "MachTask::%s ( arg = %p ) starting thread...", __FUNCTION__,
+ arg);
+
+#if defined(__APPLE__)
+ pthread_setname_np("exception monitoring thread");
+#if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
+ struct sched_param thread_param;
+ int thread_sched_policy;
+ if (pthread_getschedparam(pthread_self(), &thread_sched_policy,
+ &thread_param) == 0) {
+ thread_param.sched_priority = 47;
+ pthread_setschedparam(pthread_self(), thread_sched_policy, &thread_param);
+ }
+#endif
+#endif
+
+ // We keep a count of the number of consecutive exceptions received so
+ // we know to grab all exceptions without a timeout. We do this to get a
+ // bunch of related exceptions on our exception port so we can process
+ // then together. When we have multiple threads, we can get an exception
+ // per thread and they will come in consecutively. The main loop in this
+ // thread can stop periodically if needed to service things related to this
+ // process.
+ // flag set in the options, so we will wait forever for an exception on
+ // our exception port. After we get one exception, we then will use the
+ // MACH_RCV_TIMEOUT option with a zero timeout to grab all other current
+ // exceptions for our process. After we have received the last pending
+ // exception, we will get a timeout which enables us to then notify
+ // our main thread that we have an exception bundle available. We then wait
+ // for the main thread to tell this exception thread to start trying to get
+ // exceptions messages again and we start again with a mach_msg read with
+ // infinite timeout.
+ uint32_t num_exceptions_received = 0;
+ DNBError err;
+ task_t task = mach_task->TaskPort();
+ mach_msg_timeout_t periodic_timeout = 0;
+
+#if defined(WITH_SPRINGBOARD) && !defined(WITH_BKS)
+ mach_msg_timeout_t watchdog_elapsed = 0;
+ mach_msg_timeout_t watchdog_timeout = 60 * 1000;
+ pid_t pid = mach_proc->ProcessID();
+ CFReleaser<SBSWatchdogAssertionRef> watchdog;
+
+ if (mach_proc->ProcessUsingSpringBoard()) {
+ // Request a renewal for every 60 seconds if we attached using SpringBoard
+ watchdog.reset(::SBSWatchdogAssertionCreateForPID(NULL, pid, 60));
+ DNBLogThreadedIf(
+ LOG_TASK, "::SBSWatchdogAssertionCreateForPID (NULL, %4.4x, 60 ) => %p",
+ pid, watchdog.get());
+
+ if (watchdog.get()) {
+ ::SBSWatchdogAssertionRenew(watchdog.get());
+
+ CFTimeInterval watchdogRenewalInterval =
+ ::SBSWatchdogAssertionGetRenewalInterval(watchdog.get());
+ DNBLogThreadedIf(
+ LOG_TASK,
+ "::SBSWatchdogAssertionGetRenewalInterval ( %p ) => %g seconds",
+ watchdog.get(), watchdogRenewalInterval);
+ if (watchdogRenewalInterval > 0.0) {
+ watchdog_timeout = (mach_msg_timeout_t)watchdogRenewalInterval * 1000;
+ if (watchdog_timeout > 3000)
+ watchdog_timeout -= 1000; // Give us a second to renew our timeout
+ else if (watchdog_timeout > 1000)
+ watchdog_timeout -=
+ 250; // Give us a quarter of a second to renew our timeout
+ }
+ }
+ if (periodic_timeout == 0 || periodic_timeout > watchdog_timeout)
+ periodic_timeout = watchdog_timeout;
+ }
+#endif // #if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
#ifdef WITH_BKS
- CFReleaser<BKSWatchdogAssertionRef> watchdog;
- if (mach_proc->ProcessUsingBackBoard())
- {
- pid_t pid = mach_proc->ProcessID();
- CFAllocatorRef alloc = kCFAllocatorDefault;
- watchdog.reset(::BKSWatchdogAssertionCreateForPID(alloc, pid));
- }
+ CFReleaser<BKSWatchdogAssertionRef> watchdog;
+ if (mach_proc->ProcessUsingBackBoard()) {
+ pid_t pid = mach_proc->ProcessID();
+ CFAllocatorRef alloc = kCFAllocatorDefault;
+ watchdog.reset(::BKSWatchdogAssertionCreateForPID(alloc, pid));
+ }
#endif // #ifdef WITH_BKS
- while (mach_task->ExceptionPortIsValid())
- {
- ::pthread_testcancel ();
-
- MachException::Message exception_message;
+ while (mach_task->ExceptionPortIsValid()) {
+ ::pthread_testcancel();
+ MachException::Message exception_message;
- if (num_exceptions_received > 0)
- {
- // No timeout, just receive as many exceptions as we can since we already have one and we want
- // to get all currently available exceptions for this task
- err = exception_message.Receive(mach_task->ExceptionPort(), MACH_RCV_MSG | MACH_RCV_INTERRUPT | MACH_RCV_TIMEOUT, 0);
- }
- else if (periodic_timeout > 0)
- {
- // We need to stop periodically in this loop, so try and get a mach message with a valid timeout (ms)
- err = exception_message.Receive(mach_task->ExceptionPort(), MACH_RCV_MSG | MACH_RCV_INTERRUPT | MACH_RCV_TIMEOUT, periodic_timeout);
- }
- else
- {
- // We don't need to parse all current exceptions or stop periodically,
- // just wait for an exception forever.
- err = exception_message.Receive(mach_task->ExceptionPort(), MACH_RCV_MSG | MACH_RCV_INTERRUPT, 0);
- }
-
- if (err.Error() == MACH_RCV_INTERRUPTED)
- {
- // If we have no task port we should exit this thread
- if (!mach_task->ExceptionPortIsValid())
- {
- DNBLogThreadedIf(LOG_EXCEPTIONS, "thread cancelled...");
- break;
- }
-
- // Make sure our task is still valid
- if (MachTask::IsValid(task))
- {
- // Task is still ok
- DNBLogThreadedIf(LOG_EXCEPTIONS, "interrupted, but task still valid, continuing...");
- continue;
- }
- else
- {
- DNBLogThreadedIf(LOG_EXCEPTIONS, "task has exited...");
- mach_proc->SetState(eStateExited);
- // Our task has died, exit the thread.
- break;
- }
- }
- else if (err.Error() == MACH_RCV_TIMED_OUT)
- {
- if (num_exceptions_received > 0)
- {
- // We were receiving all current exceptions with a timeout of zero
- // it is time to go back to our normal looping mode
- num_exceptions_received = 0;
-
- // Notify our main thread we have a complete exception message
- // bundle available and get the possibly updated task port back
- // from the process in case we exec'ed and our task port changed
- task = mach_proc->ExceptionMessageBundleComplete();
-
- // in case we use a timeout value when getting exceptions...
- // Make sure our task is still valid
- if (MachTask::IsValid(task))
- {
- // Task is still ok
- DNBLogThreadedIf(LOG_EXCEPTIONS, "got a timeout, continuing...");
- continue;
- }
- else
- {
- DNBLogThreadedIf(LOG_EXCEPTIONS, "task has exited...");
- mach_proc->SetState(eStateExited);
- // Our task has died, exit the thread.
- break;
- }
- }
-
-#if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
- if (watchdog.get())
- {
- watchdog_elapsed += periodic_timeout;
- if (watchdog_elapsed >= watchdog_timeout)
- {
- DNBLogThreadedIf(LOG_TASK, "SBSWatchdogAssertionRenew ( %p )", watchdog.get());
- ::SBSWatchdogAssertionRenew (watchdog.get());
- watchdog_elapsed = 0;
- }
- }
-#endif
- }
- else if (err.Error() != KERN_SUCCESS)
- {
- DNBLogThreadedIf(LOG_EXCEPTIONS, "got some other error, do something about it??? nah, continuing for now...");
- // TODO: notify of error?
- }
- else
- {
- if (exception_message.CatchExceptionRaise(task))
- {
- ++num_exceptions_received;
- mach_proc->ExceptionMessageReceived(exception_message);
- }
- }
- }
-
-#if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
- if (watchdog.get())
- {
- // TODO: change SBSWatchdogAssertionRelease to SBSWatchdogAssertionCancel when we
- // all are up and running on systems that support it. The SBS framework has a #define
- // that will forward SBSWatchdogAssertionRelease to SBSWatchdogAssertionCancel for now
- // so it should still build either way.
- DNBLogThreadedIf(LOG_TASK, "::SBSWatchdogAssertionRelease(%p)", watchdog.get());
- ::SBSWatchdogAssertionRelease (watchdog.get());
- }
-#endif // #if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
-
- DNBLogThreadedIf(LOG_EXCEPTIONS, "MachTask::%s (%p): thread exiting...", __FUNCTION__, arg);
- return NULL;
+ if (num_exceptions_received > 0) {
+ // No timeout, just receive as many exceptions as we can since we already
+ // have one and we want
+ // to get all currently available exceptions for this task
+ err = exception_message.Receive(
+ mach_task->ExceptionPort(),
+ MACH_RCV_MSG | MACH_RCV_INTERRUPT | MACH_RCV_TIMEOUT, 0);
+ } else if (periodic_timeout > 0) {
+ // We need to stop periodically in this loop, so try and get a mach
+ // message with a valid timeout (ms)
+ err = exception_message.Receive(mach_task->ExceptionPort(),
+ MACH_RCV_MSG | MACH_RCV_INTERRUPT |
+ MACH_RCV_TIMEOUT,
+ periodic_timeout);
+ } else {
+ // We don't need to parse all current exceptions or stop periodically,
+ // just wait for an exception forever.
+ err = exception_message.Receive(mach_task->ExceptionPort(),
+ MACH_RCV_MSG | MACH_RCV_INTERRUPT, 0);
+ }
+
+ if (err.Error() == MACH_RCV_INTERRUPTED) {
+ // If we have no task port we should exit this thread
+ if (!mach_task->ExceptionPortIsValid()) {
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "thread cancelled...");
+ break;
+ }
+
+ // Make sure our task is still valid
+ if (MachTask::IsValid(task)) {
+ // Task is still ok
+ DNBLogThreadedIf(LOG_EXCEPTIONS,
+ "interrupted, but task still valid, continuing...");
+ continue;
+ } else {
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "task has exited...");
+ mach_proc->SetState(eStateExited);
+ // Our task has died, exit the thread.
+ break;
+ }
+ } else if (err.Error() == MACH_RCV_TIMED_OUT) {
+ if (num_exceptions_received > 0) {
+ // We were receiving all current exceptions with a timeout of zero
+ // it is time to go back to our normal looping mode
+ num_exceptions_received = 0;
+
+ // Notify our main thread we have a complete exception message
+ // bundle available and get the possibly updated task port back
+ // from the process in case we exec'ed and our task port changed
+ task = mach_proc->ExceptionMessageBundleComplete();
+
+ // in case we use a timeout value when getting exceptions...
+ // Make sure our task is still valid
+ if (MachTask::IsValid(task)) {
+ // Task is still ok
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "got a timeout, continuing...");
+ continue;
+ } else {
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "task has exited...");
+ mach_proc->SetState(eStateExited);
+ // Our task has died, exit the thread.
+ break;
+ }
+ }
+
+#if defined(WITH_SPRINGBOARD) && !defined(WITH_BKS)
+ if (watchdog.get()) {
+ watchdog_elapsed += periodic_timeout;
+ if (watchdog_elapsed >= watchdog_timeout) {
+ DNBLogThreadedIf(LOG_TASK, "SBSWatchdogAssertionRenew ( %p )",
+ watchdog.get());
+ ::SBSWatchdogAssertionRenew(watchdog.get());
+ watchdog_elapsed = 0;
+ }
+ }
+#endif
+ } else if (err.Error() != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "got some other error, do something "
+ "about it??? nah, continuing for "
+ "now...");
+ // TODO: notify of error?
+ } else {
+ if (exception_message.CatchExceptionRaise(task)) {
+ ++num_exceptions_received;
+ mach_proc->ExceptionMessageReceived(exception_message);
+ }
+ }
+ }
+
+#if defined(WITH_SPRINGBOARD) && !defined(WITH_BKS)
+ if (watchdog.get()) {
+ // TODO: change SBSWatchdogAssertionRelease to SBSWatchdogAssertionCancel
+ // when we
+ // all are up and running on systems that support it. The SBS framework has
+ // a #define
+ // that will forward SBSWatchdogAssertionRelease to
+ // SBSWatchdogAssertionCancel for now
+ // so it should still build either way.
+ DNBLogThreadedIf(LOG_TASK, "::SBSWatchdogAssertionRelease(%p)",
+ watchdog.get());
+ ::SBSWatchdogAssertionRelease(watchdog.get());
+ }
+#endif // #if defined (WITH_SPRINGBOARD) && !defined (WITH_BKS)
+
+ DNBLogThreadedIf(LOG_EXCEPTIONS, "MachTask::%s (%p): thread exiting...",
+ __FUNCTION__, arg);
+ return NULL;
}
-
// So the TASK_DYLD_INFO used to just return the address of the all image infos
// as a single member called "all_image_info". Then someone decided it would be
// a good idea to rename this first member to "all_image_info_addr" and add a
// size member called "all_image_info_size". This of course can not be detected
// using code or #defines. So to hack around this problem, we define our own
-// version of the TASK_DYLD_INFO structure so we can guarantee what is inside it.
+// version of the TASK_DYLD_INFO structure so we can guarantee what is inside
+// it.
struct hack_task_dyld_info {
- mach_vm_address_t all_image_info_addr;
- mach_vm_size_t all_image_info_size;
+ mach_vm_address_t all_image_info_addr;
+ mach_vm_size_t all_image_info_size;
};
-nub_addr_t
-MachTask::GetDYLDAllImageInfosAddress (DNBError& err)
-{
- struct hack_task_dyld_info dyld_info;
- mach_msg_type_number_t count = TASK_DYLD_INFO_COUNT;
- // Make sure that COUNT isn't bigger than our hacked up struct hack_task_dyld_info.
- // If it is, then make COUNT smaller to match.
- if (count > (sizeof(struct hack_task_dyld_info) / sizeof(natural_t)))
- count = (sizeof(struct hack_task_dyld_info) / sizeof(natural_t));
-
- task_t task = TaskPortForProcessID (err);
- if (err.Success())
- {
- err = ::task_info (task, TASK_DYLD_INFO, (task_info_t)&dyld_info, &count);
- if (err.Success())
- {
- // We now have the address of the all image infos structure
- return dyld_info.all_image_info_addr;
- }
+nub_addr_t MachTask::GetDYLDAllImageInfosAddress(DNBError &err) {
+ struct hack_task_dyld_info dyld_info;
+ mach_msg_type_number_t count = TASK_DYLD_INFO_COUNT;
+ // Make sure that COUNT isn't bigger than our hacked up struct
+ // hack_task_dyld_info.
+ // If it is, then make COUNT smaller to match.
+ if (count > (sizeof(struct hack_task_dyld_info) / sizeof(natural_t)))
+ count = (sizeof(struct hack_task_dyld_info) / sizeof(natural_t));
+
+ task_t task = TaskPortForProcessID(err);
+ if (err.Success()) {
+ err = ::task_info(task, TASK_DYLD_INFO, (task_info_t)&dyld_info, &count);
+ if (err.Success()) {
+ // We now have the address of the all image infos structure
+ return dyld_info.all_image_info_addr;
}
- return INVALID_NUB_ADDRESS;
+ }
+ return INVALID_NUB_ADDRESS;
}
-
//----------------------------------------------------------------------
// MachTask::AllocateMemory
//----------------------------------------------------------------------
-nub_addr_t
-MachTask::AllocateMemory (size_t size, uint32_t permissions)
-{
- mach_vm_address_t addr;
- task_t task = TaskPort();
- if (task == TASK_NULL)
- return INVALID_NUB_ADDRESS;
-
- DNBError err;
- err = ::mach_vm_allocate (task, &addr, size, TRUE);
- if (err.Error() == KERN_SUCCESS)
- {
- // Set the protections:
- vm_prot_t mach_prot = VM_PROT_NONE;
- if (permissions & eMemoryPermissionsReadable)
- mach_prot |= VM_PROT_READ;
- if (permissions & eMemoryPermissionsWritable)
- mach_prot |= VM_PROT_WRITE;
- if (permissions & eMemoryPermissionsExecutable)
- mach_prot |= VM_PROT_EXECUTE;
-
-
- err = ::mach_vm_protect (task, addr, size, 0, mach_prot);
- if (err.Error() == KERN_SUCCESS)
- {
- m_allocations.insert (std::make_pair(addr, size));
- return addr;
- }
- ::mach_vm_deallocate (task, addr, size);
- }
+nub_addr_t MachTask::AllocateMemory(size_t size, uint32_t permissions) {
+ mach_vm_address_t addr;
+ task_t task = TaskPort();
+ if (task == TASK_NULL)
return INVALID_NUB_ADDRESS;
+
+ DNBError err;
+ err = ::mach_vm_allocate(task, &addr, size, TRUE);
+ if (err.Error() == KERN_SUCCESS) {
+ // Set the protections:
+ vm_prot_t mach_prot = VM_PROT_NONE;
+ if (permissions & eMemoryPermissionsReadable)
+ mach_prot |= VM_PROT_READ;
+ if (permissions & eMemoryPermissionsWritable)
+ mach_prot |= VM_PROT_WRITE;
+ if (permissions & eMemoryPermissionsExecutable)
+ mach_prot |= VM_PROT_EXECUTE;
+
+ err = ::mach_vm_protect(task, addr, size, 0, mach_prot);
+ if (err.Error() == KERN_SUCCESS) {
+ m_allocations.insert(std::make_pair(addr, size));
+ return addr;
+ }
+ ::mach_vm_deallocate(task, addr, size);
+ }
+ return INVALID_NUB_ADDRESS;
}
//----------------------------------------------------------------------
// MachTask::DeallocateMemory
//----------------------------------------------------------------------
-nub_bool_t
-MachTask::DeallocateMemory (nub_addr_t addr)
-{
- task_t task = TaskPort();
- if (task == TASK_NULL)
- return false;
-
- // We have to stash away sizes for the allocations...
- allocation_collection::iterator pos, end = m_allocations.end();
- for (pos = m_allocations.begin(); pos != end; pos++)
- {
- if ((*pos).first == addr)
- {
- m_allocations.erase(pos);
+nub_bool_t MachTask::DeallocateMemory(nub_addr_t addr) {
+ task_t task = TaskPort();
+ if (task == TASK_NULL)
+ return false;
+
+ // We have to stash away sizes for the allocations...
+ allocation_collection::iterator pos, end = m_allocations.end();
+ for (pos = m_allocations.begin(); pos != end; pos++) {
+ if ((*pos).first == addr) {
+ m_allocations.erase(pos);
#define ALWAYS_ZOMBIE_ALLOCATIONS 0
- if (ALWAYS_ZOMBIE_ALLOCATIONS || getenv ("DEBUGSERVER_ZOMBIE_ALLOCATIONS"))
- {
- ::mach_vm_protect (task, (*pos).first, (*pos).second, 0, VM_PROT_NONE);
- return true;
- }
- else
- return ::mach_vm_deallocate (task, (*pos).first, (*pos).second) == KERN_SUCCESS;
- }
-
+ if (ALWAYS_ZOMBIE_ALLOCATIONS ||
+ getenv("DEBUGSERVER_ZOMBIE_ALLOCATIONS")) {
+ ::mach_vm_protect(task, (*pos).first, (*pos).second, 0, VM_PROT_NONE);
+ return true;
+ } else
+ return ::mach_vm_deallocate(task, (*pos).first, (*pos).second) ==
+ KERN_SUCCESS;
}
- return false;
+ }
+ return false;
}
-nub_size_t
-MachTask::PageSize ()
-{
- return m_vm_memory.PageSize (m_task);
-}
+nub_size_t MachTask::PageSize() { return m_vm_memory.PageSize(m_task); }
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachThread.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachThread.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachThread.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachThread.cpp Tue Sep 6 15:57:50 2016
@@ -11,912 +11,773 @@
//
//===----------------------------------------------------------------------===//
-#include <inttypes.h>
-#include <mach/thread_policy.h>
-#include <dlfcn.h>
#include "MachThread.h"
-#include "MachProcess.h"
-#include "DNBLog.h"
#include "DNB.h"
+#include "DNBLog.h"
+#include "MachProcess.h"
#include "ThreadInfo.h"
+#include <dlfcn.h>
+#include <inttypes.h>
+#include <mach/thread_policy.h>
-static uint32_t
-GetSequenceID()
-{
- static uint32_t g_nextID = 0;
- return ++g_nextID;
-}
-
-MachThread::MachThread (MachProcess *process, bool is_64_bit, uint64_t unique_thread_id, thread_t mach_port_num) :
- m_process (process),
- m_unique_id (unique_thread_id),
- m_mach_port_number (mach_port_num),
- m_seq_id (GetSequenceID()),
- m_state (eStateUnloaded),
- m_state_mutex (PTHREAD_MUTEX_RECURSIVE),
- m_suspend_count (0),
- m_stop_exception (),
- m_arch_ap (DNBArchProtocol::Create (this)),
- m_reg_sets (NULL),
- m_num_reg_sets (0),
- m_ident_info(),
- m_proc_threadinfo(),
- m_dispatch_queue_name(),
- m_is_64_bit(is_64_bit),
- m_pthread_qos_class_decode (nullptr)
-{
- nub_size_t num_reg_sets = 0;
- m_reg_sets = m_arch_ap->GetRegisterSetInfo (&num_reg_sets);
- m_num_reg_sets = num_reg_sets;
-
- m_pthread_qos_class_decode = (unsigned int (*)(unsigned long, int*, unsigned long*)) dlsym (RTLD_DEFAULT, "_pthread_qos_class_decode");
-
- // Get the thread state so we know if a thread is in a state where we can't
- // muck with it and also so we get the suspend count correct in case it was
- // already suspended
- GetBasicInfo();
- DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::MachThread ( process = %p, tid = 0x%8.8" PRIx64 ", seq_id = %u )", &m_process, m_unique_id, m_seq_id);
-}
-
-MachThread::~MachThread()
-{
- DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::~MachThread() for tid = 0x%8.8" PRIx64 " (%u)", m_unique_id, m_seq_id);
-}
-
-
-
-void
-MachThread::Suspend()
-{
- DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )", __FUNCTION__);
- if (MachPortNumberIsValid(m_mach_port_number))
- {
- DNBError err(::thread_suspend (m_mach_port_number), DNBError::MachKernel);
- if (err.Success())
- m_suspend_count++;
- if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
- err.LogThreaded("::thread_suspend (%4.4" PRIx32 ")", m_mach_port_number);
- }
-}
+static uint32_t GetSequenceID() {
+ static uint32_t g_nextID = 0;
+ return ++g_nextID;
+}
+
+MachThread::MachThread(MachProcess *process, bool is_64_bit,
+ uint64_t unique_thread_id, thread_t mach_port_num)
+ : m_process(process), m_unique_id(unique_thread_id),
+ m_mach_port_number(mach_port_num), m_seq_id(GetSequenceID()),
+ m_state(eStateUnloaded), m_state_mutex(PTHREAD_MUTEX_RECURSIVE),
+ m_suspend_count(0), m_stop_exception(),
+ m_arch_ap(DNBArchProtocol::Create(this)), m_reg_sets(NULL),
+ m_num_reg_sets(0), m_ident_info(), m_proc_threadinfo(),
+ m_dispatch_queue_name(), m_is_64_bit(is_64_bit),
+ m_pthread_qos_class_decode(nullptr) {
+ nub_size_t num_reg_sets = 0;
+ m_reg_sets = m_arch_ap->GetRegisterSetInfo(&num_reg_sets);
+ m_num_reg_sets = num_reg_sets;
+
+ m_pthread_qos_class_decode =
+ (unsigned int (*)(unsigned long, int *, unsigned long *))dlsym(
+ RTLD_DEFAULT, "_pthread_qos_class_decode");
+
+ // Get the thread state so we know if a thread is in a state where we can't
+ // muck with it and also so we get the suspend count correct in case it was
+ // already suspended
+ GetBasicInfo();
+ DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE,
+ "MachThread::MachThread ( process = %p, tid = 0x%8.8" PRIx64
+ ", seq_id = %u )",
+ &m_process, m_unique_id, m_seq_id);
+}
+
+MachThread::~MachThread() {
+ DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE,
+ "MachThread::~MachThread() for tid = 0x%8.8" PRIx64 " (%u)",
+ m_unique_id, m_seq_id);
+}
+
+void MachThread::Suspend() {
+ DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )",
+ __FUNCTION__);
+ if (MachPortNumberIsValid(m_mach_port_number)) {
+ DNBError err(::thread_suspend(m_mach_port_number), DNBError::MachKernel);
+ if (err.Success())
+ m_suspend_count++;
+ if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
+ err.LogThreaded("::thread_suspend (%4.4" PRIx32 ")", m_mach_port_number);
+ }
+}
+
+void MachThread::Resume(bool others_stopped) {
+ DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )",
+ __FUNCTION__);
+ if (MachPortNumberIsValid(m_mach_port_number)) {
+ SetSuspendCountBeforeResume(others_stopped);
+ }
+}
+
+bool MachThread::SetSuspendCountBeforeResume(bool others_stopped) {
+ DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )",
+ __FUNCTION__);
+ DNBError err;
+ if (MachPortNumberIsValid(m_mach_port_number) == false)
+ return false;
-void
-MachThread::Resume(bool others_stopped)
-{
- DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )", __FUNCTION__);
- if (MachPortNumberIsValid(m_mach_port_number))
- {
- SetSuspendCountBeforeResume(others_stopped);
- }
-}
+ integer_t times_to_resume;
-bool
-MachThread::SetSuspendCountBeforeResume(bool others_stopped)
-{
- DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )", __FUNCTION__);
- DNBError err;
- if (MachPortNumberIsValid(m_mach_port_number) == false)
- return false;
-
- integer_t times_to_resume;
-
- if (others_stopped)
- {
+ if (others_stopped) {
+ if (GetBasicInfo()) {
+ times_to_resume = m_basic_info.suspend_count;
+ m_suspend_count = -(times_to_resume - m_suspend_count);
+ } else
+ times_to_resume = 0;
+ } else {
+ times_to_resume = m_suspend_count;
+ m_suspend_count = 0;
+ }
+
+ if (times_to_resume > 0) {
+ while (times_to_resume > 0) {
+ err = ::thread_resume(m_mach_port_number);
+ if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
+ err.LogThreaded("::thread_resume (%4.4" PRIx32 ")", m_mach_port_number);
+ if (err.Success())
+ --times_to_resume;
+ else {
if (GetBasicInfo())
- {
- times_to_resume = m_basic_info.suspend_count;
- m_suspend_count = - (times_to_resume - m_suspend_count);
- }
+ times_to_resume = m_basic_info.suspend_count;
else
- times_to_resume = 0;
- }
- else
- {
- times_to_resume = m_suspend_count;
- m_suspend_count = 0;
- }
-
- if (times_to_resume > 0)
- {
- while (times_to_resume > 0)
- {
- err = ::thread_resume (m_mach_port_number);
- if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
- err.LogThreaded("::thread_resume (%4.4" PRIx32 ")", m_mach_port_number);
- if (err.Success())
- --times_to_resume;
- else
- {
- if (GetBasicInfo())
- times_to_resume = m_basic_info.suspend_count;
- else
- times_to_resume = 0;
- }
- }
- }
- return true;
-}
-
-bool
-MachThread::RestoreSuspendCountAfterStop ()
-{
- DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )", __FUNCTION__);
- DNBError err;
- if (MachPortNumberIsValid(m_mach_port_number) == false)
- return false;
-
- if (m_suspend_count > 0)
- {
- while (m_suspend_count > 0)
- {
- err = ::thread_resume (m_mach_port_number);
- if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
- err.LogThreaded("::thread_resume (%4.4" PRIx32 ")", m_mach_port_number);
- if (err.Success())
- --m_suspend_count;
- else
- {
- if (GetBasicInfo())
- m_suspend_count = m_basic_info.suspend_count;
- else
- m_suspend_count = 0;
- return false; // ???
- }
- }
- }
- else if (m_suspend_count < 0)
- {
- while (m_suspend_count < 0)
- {
- err = ::thread_suspend (m_mach_port_number);
- if (err.Success())
- ++m_suspend_count;
- if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
- {
- err.LogThreaded("::thread_suspend (%4.4" PRIx32 ")", m_mach_port_number);
- return false;
- }
- }
+ times_to_resume = 0;
+ }
}
- return true;
+ }
+ return true;
}
-
-const char *
-MachThread::GetBasicInfoAsString () const
-{
- static char g_basic_info_string[1024];
- struct thread_basic_info basicInfo;
-
- if (GetBasicInfo(m_mach_port_number, &basicInfo))
- {
-
-// char run_state_str[32];
-// size_t run_state_str_size = sizeof(run_state_str);
-// switch (basicInfo.run_state)
-// {
-// case TH_STATE_RUNNING: strncpy(run_state_str, "running", run_state_str_size); break;
-// case TH_STATE_STOPPED: strncpy(run_state_str, "stopped", run_state_str_size); break;
-// case TH_STATE_WAITING: strncpy(run_state_str, "waiting", run_state_str_size); break;
-// case TH_STATE_UNINTERRUPTIBLE: strncpy(run_state_str, "uninterruptible", run_state_str_size); break;
-// case TH_STATE_HALTED: strncpy(run_state_str, "halted", run_state_str_size); break;
-// default: snprintf(run_state_str, run_state_str_size, "%d", basicInfo.run_state); break; // ???
-// }
- float user = (float)basicInfo.user_time.seconds + (float)basicInfo.user_time.microseconds / 1000000.0f;
- float system = (float)basicInfo.user_time.seconds + (float)basicInfo.user_time.microseconds / 1000000.0f;
- snprintf(g_basic_info_string, sizeof(g_basic_info_string), "Thread 0x%8.8" PRIx64 ": user=%f system=%f cpu=%d sleep_time=%d",
- m_unique_id,
- user,
- system,
- basicInfo.cpu_usage,
- basicInfo.sleep_time);
-
- return g_basic_info_string;
- }
- return NULL;
-}
-
-// Finds the Mach port number for a given thread in the inferior process' port namespace.
-thread_t
-MachThread::InferiorThreadID() const
-{
- mach_msg_type_number_t i;
- mach_port_name_array_t names;
- mach_port_type_array_t types;
- mach_msg_type_number_t ncount, tcount;
- thread_t inferior_tid = INVALID_NUB_THREAD;
- task_t my_task = ::mach_task_self();
- task_t task = m_process->Task().TaskPort();
-
- kern_return_t kret = ::mach_port_names (task, &names, &ncount, &types, &tcount);
- if (kret == KERN_SUCCESS)
- {
-
- for (i = 0; i < ncount; i++)
- {
- mach_port_t my_name;
- mach_msg_type_name_t my_type;
-
- kret = ::mach_port_extract_right (task, names[i], MACH_MSG_TYPE_COPY_SEND, &my_name, &my_type);
- if (kret == KERN_SUCCESS)
- {
- ::mach_port_deallocate (my_task, my_name);
- if (my_name == m_mach_port_number)
- {
- inferior_tid = names[i];
- break;
- }
- }
- }
- // Free up the names and types
- ::vm_deallocate (my_task, (vm_address_t) names, ncount * sizeof (mach_port_name_t));
- ::vm_deallocate (my_task, (vm_address_t) types, tcount * sizeof (mach_port_type_t));
- }
- return inferior_tid;
-}
-
-bool
-MachThread::IsUserReady()
-{
- if (m_basic_info.run_state == 0)
- GetBasicInfo ();
-
- switch (m_basic_info.run_state)
- {
- default:
- case TH_STATE_UNINTERRUPTIBLE:
- break;
-
- case TH_STATE_RUNNING:
- case TH_STATE_STOPPED:
- case TH_STATE_WAITING:
- case TH_STATE_HALTED:
- return true;
- }
+bool MachThread::RestoreSuspendCountAfterStop() {
+ DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE, "MachThread::%s ( )",
+ __FUNCTION__);
+ DNBError err;
+ if (MachPortNumberIsValid(m_mach_port_number) == false)
return false;
-}
-struct thread_basic_info *
-MachThread::GetBasicInfo ()
-{
- if (MachThread::GetBasicInfo(m_mach_port_number, &m_basic_info))
- return &m_basic_info;
- return NULL;
-}
-
-
-bool
-MachThread::GetBasicInfo(thread_t thread, struct thread_basic_info *basicInfoPtr)
-{
- if (MachPortNumberIsValid(thread))
- {
- unsigned int info_count = THREAD_BASIC_INFO_COUNT;
- kern_return_t err = ::thread_info (thread, THREAD_BASIC_INFO, (thread_info_t) basicInfoPtr, &info_count);
- if (err == KERN_SUCCESS)
- return true;
+ if (m_suspend_count > 0) {
+ while (m_suspend_count > 0) {
+ err = ::thread_resume(m_mach_port_number);
+ if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
+ err.LogThreaded("::thread_resume (%4.4" PRIx32 ")", m_mach_port_number);
+ if (err.Success())
+ --m_suspend_count;
+ else {
+ if (GetBasicInfo())
+ m_suspend_count = m_basic_info.suspend_count;
+ else
+ m_suspend_count = 0;
+ return false; // ???
+ }
+ }
+ } else if (m_suspend_count < 0) {
+ while (m_suspend_count < 0) {
+ err = ::thread_suspend(m_mach_port_number);
+ if (err.Success())
+ ++m_suspend_count;
+ if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail()) {
+ err.LogThreaded("::thread_suspend (%4.4" PRIx32 ")",
+ m_mach_port_number);
+ return false;
+ }
}
- ::memset (basicInfoPtr, 0, sizeof (struct thread_basic_info));
- return false;
-}
-
-
-bool
-MachThread::ThreadIDIsValid(uint64_t thread)
-{
- return thread != 0;
-}
-
-bool
-MachThread::MachPortNumberIsValid(thread_t thread)
-{
- return thread != THREAD_NULL;
-}
-
-bool
-MachThread::GetRegisterState(int flavor, bool force)
-{
- return m_arch_ap->GetRegisterState(flavor, force) == KERN_SUCCESS;
+ }
+ return true;
}
-bool
-MachThread::SetRegisterState(int flavor)
-{
- return m_arch_ap->SetRegisterState(flavor) == KERN_SUCCESS;
+const char *MachThread::GetBasicInfoAsString() const {
+ static char g_basic_info_string[1024];
+ struct thread_basic_info basicInfo;
+
+ if (GetBasicInfo(m_mach_port_number, &basicInfo)) {
+
+ // char run_state_str[32];
+ // size_t run_state_str_size = sizeof(run_state_str);
+ // switch (basicInfo.run_state)
+ // {
+ // case TH_STATE_RUNNING: strncpy(run_state_str, "running",
+ // run_state_str_size); break;
+ // case TH_STATE_STOPPED: strncpy(run_state_str, "stopped",
+ // run_state_str_size); break;
+ // case TH_STATE_WAITING: strncpy(run_state_str, "waiting",
+ // run_state_str_size); break;
+ // case TH_STATE_UNINTERRUPTIBLE: strncpy(run_state_str,
+ // "uninterruptible", run_state_str_size); break;
+ // case TH_STATE_HALTED: strncpy(run_state_str, "halted",
+ // run_state_str_size); break;
+ // default: snprintf(run_state_str,
+ // run_state_str_size, "%d", basicInfo.run_state); break; // ???
+ // }
+ float user = (float)basicInfo.user_time.seconds +
+ (float)basicInfo.user_time.microseconds / 1000000.0f;
+ float system = (float)basicInfo.user_time.seconds +
+ (float)basicInfo.user_time.microseconds / 1000000.0f;
+ snprintf(g_basic_info_string, sizeof(g_basic_info_string),
+ "Thread 0x%8.8" PRIx64 ": user=%f system=%f cpu=%d sleep_time=%d",
+ m_unique_id, user, system, basicInfo.cpu_usage,
+ basicInfo.sleep_time);
+
+ return g_basic_info_string;
+ }
+ return NULL;
+}
+
+// Finds the Mach port number for a given thread in the inferior process' port
+// namespace.
+thread_t MachThread::InferiorThreadID() const {
+ mach_msg_type_number_t i;
+ mach_port_name_array_t names;
+ mach_port_type_array_t types;
+ mach_msg_type_number_t ncount, tcount;
+ thread_t inferior_tid = INVALID_NUB_THREAD;
+ task_t my_task = ::mach_task_self();
+ task_t task = m_process->Task().TaskPort();
+
+ kern_return_t kret =
+ ::mach_port_names(task, &names, &ncount, &types, &tcount);
+ if (kret == KERN_SUCCESS) {
+
+ for (i = 0; i < ncount; i++) {
+ mach_port_t my_name;
+ mach_msg_type_name_t my_type;
+
+ kret = ::mach_port_extract_right(task, names[i], MACH_MSG_TYPE_COPY_SEND,
+ &my_name, &my_type);
+ if (kret == KERN_SUCCESS) {
+ ::mach_port_deallocate(my_task, my_name);
+ if (my_name == m_mach_port_number) {
+ inferior_tid = names[i];
+ break;
+ }
+ }
+ }
+ // Free up the names and types
+ ::vm_deallocate(my_task, (vm_address_t)names,
+ ncount * sizeof(mach_port_name_t));
+ ::vm_deallocate(my_task, (vm_address_t)types,
+ tcount * sizeof(mach_port_type_t));
+ }
+ return inferior_tid;
}
-uint64_t
-MachThread::GetPC(uint64_t failValue)
-{
- // Get program counter
- return m_arch_ap->GetPC(failValue);
-}
+bool MachThread::IsUserReady() {
+ if (m_basic_info.run_state == 0)
+ GetBasicInfo();
-bool
-MachThread::SetPC(uint64_t value)
-{
- // Set program counter
- return m_arch_ap->SetPC(value);
+ switch (m_basic_info.run_state) {
+ default:
+ case TH_STATE_UNINTERRUPTIBLE:
+ break;
+
+ case TH_STATE_RUNNING:
+ case TH_STATE_STOPPED:
+ case TH_STATE_WAITING:
+ case TH_STATE_HALTED:
+ return true;
+ }
+ return false;
}
-uint64_t
-MachThread::GetSP(uint64_t failValue)
-{
- // Get stack pointer
- return m_arch_ap->GetSP(failValue);
-}
-
-nub_process_t
-MachThread::ProcessID() const
-{
- if (m_process)
- return m_process->ProcessID();
- return INVALID_NUB_PROCESS;
-}
-
-void
-MachThread::Dump(uint32_t index)
-{
- const char * thread_run_state = NULL;
-
- switch (m_basic_info.run_state)
- {
- case TH_STATE_RUNNING: thread_run_state = "running"; break; // 1 thread is running normally
- case TH_STATE_STOPPED: thread_run_state = "stopped"; break; // 2 thread is stopped
- case TH_STATE_WAITING: thread_run_state = "waiting"; break; // 3 thread is waiting normally
- case TH_STATE_UNINTERRUPTIBLE: thread_run_state = "uninter"; break; // 4 thread is in an uninterruptible wait
- case TH_STATE_HALTED: thread_run_state = "halted "; break; // 5 thread is halted at a
- default: thread_run_state = "???"; break;
- }
-
- DNBLogThreaded("[%3u] #%3u tid: 0x%8.8" PRIx64 ", pc: 0x%16.16" PRIx64 ", sp: 0x%16.16" PRIx64 ", user: %d.%6.6d, system: %d.%6.6d, cpu: %2d, policy: %2d, run_state: %2d (%s), flags: %2d, suspend_count: %2d (current %2d), sleep_time: %d",
- index,
- m_seq_id,
- m_unique_id,
- GetPC(INVALID_NUB_ADDRESS),
- GetSP(INVALID_NUB_ADDRESS),
- m_basic_info.user_time.seconds, m_basic_info.user_time.microseconds,
- m_basic_info.system_time.seconds, m_basic_info.system_time.microseconds,
- m_basic_info.cpu_usage,
- m_basic_info.policy,
- m_basic_info.run_state,
- thread_run_state,
- m_basic_info.flags,
- m_basic_info.suspend_count, m_suspend_count,
- m_basic_info.sleep_time);
- //DumpRegisterState(0);
-}
-
-void
-MachThread::ThreadWillResume(const DNBThreadResumeAction *thread_action, bool others_stopped)
-{
- if (thread_action->addr != INVALID_NUB_ADDRESS)
- SetPC (thread_action->addr);
-
- SetState (thread_action->state);
- switch (thread_action->state)
- {
- case eStateStopped:
- case eStateSuspended:
- assert (others_stopped == false);
- Suspend();
- break;
-
- case eStateRunning:
- case eStateStepping:
- Resume(others_stopped);
- break;
- default:
- break;
- }
- m_arch_ap->ThreadWillResume();
- m_stop_exception.Clear();
-}
-
-DNBBreakpoint *
-MachThread::CurrentBreakpoint()
-{
- return m_process->Breakpoints().FindByAddress(GetPC());
-}
-
-bool
-MachThread::ShouldStop(bool &step_more)
-{
- // See if this thread is at a breakpoint?
- DNBBreakpoint *bp = CurrentBreakpoint();
-
- if (bp)
- {
- // This thread is sitting at a breakpoint, ask the breakpoint
- // if we should be stopping here.
+struct thread_basic_info *MachThread::GetBasicInfo() {
+ if (MachThread::GetBasicInfo(m_mach_port_number, &m_basic_info))
+ return &m_basic_info;
+ return NULL;
+}
+
+bool MachThread::GetBasicInfo(thread_t thread,
+ struct thread_basic_info *basicInfoPtr) {
+ if (MachPortNumberIsValid(thread)) {
+ unsigned int info_count = THREAD_BASIC_INFO_COUNT;
+ kern_return_t err = ::thread_info(thread, THREAD_BASIC_INFO,
+ (thread_info_t)basicInfoPtr, &info_count);
+ if (err == KERN_SUCCESS)
+ return true;
+ }
+ ::memset(basicInfoPtr, 0, sizeof(struct thread_basic_info));
+ return false;
+}
+
+bool MachThread::ThreadIDIsValid(uint64_t thread) { return thread != 0; }
+
+bool MachThread::MachPortNumberIsValid(thread_t thread) {
+ return thread != THREAD_NULL;
+}
+
+bool MachThread::GetRegisterState(int flavor, bool force) {
+ return m_arch_ap->GetRegisterState(flavor, force) == KERN_SUCCESS;
+}
+
+bool MachThread::SetRegisterState(int flavor) {
+ return m_arch_ap->SetRegisterState(flavor) == KERN_SUCCESS;
+}
+
+uint64_t MachThread::GetPC(uint64_t failValue) {
+ // Get program counter
+ return m_arch_ap->GetPC(failValue);
+}
+
+bool MachThread::SetPC(uint64_t value) {
+ // Set program counter
+ return m_arch_ap->SetPC(value);
+}
+
+uint64_t MachThread::GetSP(uint64_t failValue) {
+ // Get stack pointer
+ return m_arch_ap->GetSP(failValue);
+}
+
+nub_process_t MachThread::ProcessID() const {
+ if (m_process)
+ return m_process->ProcessID();
+ return INVALID_NUB_PROCESS;
+}
+
+void MachThread::Dump(uint32_t index) {
+ const char *thread_run_state = NULL;
+
+ switch (m_basic_info.run_state) {
+ case TH_STATE_RUNNING:
+ thread_run_state = "running";
+ break; // 1 thread is running normally
+ case TH_STATE_STOPPED:
+ thread_run_state = "stopped";
+ break; // 2 thread is stopped
+ case TH_STATE_WAITING:
+ thread_run_state = "waiting";
+ break; // 3 thread is waiting normally
+ case TH_STATE_UNINTERRUPTIBLE:
+ thread_run_state = "uninter";
+ break; // 4 thread is in an uninterruptible wait
+ case TH_STATE_HALTED:
+ thread_run_state = "halted ";
+ break; // 5 thread is halted at a
+ default:
+ thread_run_state = "???";
+ break;
+ }
+
+ DNBLogThreaded(
+ "[%3u] #%3u tid: 0x%8.8" PRIx64 ", pc: 0x%16.16" PRIx64
+ ", sp: 0x%16.16" PRIx64
+ ", user: %d.%6.6d, system: %d.%6.6d, cpu: %2d, policy: %2d, run_state: "
+ "%2d (%s), flags: %2d, suspend_count: %2d (current %2d), sleep_time: %d",
+ index, m_seq_id, m_unique_id, GetPC(INVALID_NUB_ADDRESS),
+ GetSP(INVALID_NUB_ADDRESS), m_basic_info.user_time.seconds,
+ m_basic_info.user_time.microseconds, m_basic_info.system_time.seconds,
+ m_basic_info.system_time.microseconds, m_basic_info.cpu_usage,
+ m_basic_info.policy, m_basic_info.run_state, thread_run_state,
+ m_basic_info.flags, m_basic_info.suspend_count, m_suspend_count,
+ m_basic_info.sleep_time);
+ // DumpRegisterState(0);
+}
+
+void MachThread::ThreadWillResume(const DNBThreadResumeAction *thread_action,
+ bool others_stopped) {
+ if (thread_action->addr != INVALID_NUB_ADDRESS)
+ SetPC(thread_action->addr);
+
+ SetState(thread_action->state);
+ switch (thread_action->state) {
+ case eStateStopped:
+ case eStateSuspended:
+ assert(others_stopped == false);
+ Suspend();
+ break;
+
+ case eStateRunning:
+ case eStateStepping:
+ Resume(others_stopped);
+ break;
+ default:
+ break;
+ }
+ m_arch_ap->ThreadWillResume();
+ m_stop_exception.Clear();
+}
+
+DNBBreakpoint *MachThread::CurrentBreakpoint() {
+ return m_process->Breakpoints().FindByAddress(GetPC());
+}
+
+bool MachThread::ShouldStop(bool &step_more) {
+ // See if this thread is at a breakpoint?
+ DNBBreakpoint *bp = CurrentBreakpoint();
+
+ if (bp) {
+ // This thread is sitting at a breakpoint, ask the breakpoint
+ // if we should be stopping here.
+ return true;
+ } else {
+ if (m_arch_ap->StepNotComplete()) {
+ step_more = true;
+ return false;
+ }
+ // The thread state is used to let us know what the thread was
+ // trying to do. MachThread::ThreadWillResume() will set the
+ // thread state to various values depending if the thread was
+ // the current thread and if it was to be single stepped, or
+ // resumed.
+ if (GetState() == eStateRunning) {
+ // If our state is running, then we should continue as we are in
+ // the process of stepping over a breakpoint.
+ return false;
+ } else {
+ // Stop if we have any kind of valid exception for this
+ // thread.
+ if (GetStopException().IsValid())
return true;
}
- else
- {
- if (m_arch_ap->StepNotComplete())
- {
- step_more = true;
- return false;
- }
- // The thread state is used to let us know what the thread was
- // trying to do. MachThread::ThreadWillResume() will set the
- // thread state to various values depending if the thread was
- // the current thread and if it was to be single stepped, or
- // resumed.
- if (GetState() == eStateRunning)
- {
- // If our state is running, then we should continue as we are in
- // the process of stepping over a breakpoint.
- return false;
- }
- else
- {
- // Stop if we have any kind of valid exception for this
- // thread.
- if (GetStopException().IsValid())
- return true;
- }
- }
- return false;
-}
-bool
-MachThread::IsStepping()
-{
- return GetState() == eStateStepping;
+ }
+ return false;
}
+bool MachThread::IsStepping() { return GetState() == eStateStepping; }
-
-bool
-MachThread::ThreadDidStop()
-{
- // This thread has existed prior to resuming under debug nub control,
- // and has just been stopped. Do any cleanup that needs to be done
- // after running.
-
- // The thread state and breakpoint will still have the same values
- // as they had prior to resuming the thread, so it makes it easy to check
- // if we were trying to step a thread, or we tried to resume while being
- // at a breakpoint.
-
- // When this method gets called, the process state is still in the
- // state it was in while running so we can act accordingly.
- m_arch_ap->ThreadDidStop();
-
-
- // We may have suspended this thread so the primary thread could step
- // without worrying about race conditions, so lets restore our suspend
- // count.
- RestoreSuspendCountAfterStop();
-
- // Update the basic information for a thread
- MachThread::GetBasicInfo(m_mach_port_number, &m_basic_info);
-
- if (m_basic_info.suspend_count > 0)
- SetState(eStateSuspended);
- else
- SetState(eStateStopped);
- return true;
-}
-
-bool
-MachThread::NotifyException(MachException::Data& exc)
-{
- // Allow the arch specific protocol to process (MachException::Data &)exc
- // first before possible reassignment of m_stop_exception with exc.
- // See also MachThread::GetStopException().
- bool handled = m_arch_ap->NotifyException(exc);
-
- if (m_stop_exception.IsValid())
- {
- // We may have more than one exception for a thread, but we need to
- // only remember the one that we will say is the reason we stopped.
- // We may have been single stepping and also gotten a signal exception,
- // so just remember the most pertinent one.
- if (m_stop_exception.IsBreakpoint())
- m_stop_exception = exc;
- }
- else
- {
- m_stop_exception = exc;
- }
-
- return handled;
-}
-
-
-nub_state_t
-MachThread::GetState()
-{
- // If any other threads access this we will need a mutex for it
- PTHREAD_MUTEX_LOCKER (locker, m_state_mutex);
- return m_state;
-}
-
-void
-MachThread::SetState(nub_state_t state)
-{
- PTHREAD_MUTEX_LOCKER (locker, m_state_mutex);
- m_state = state;
- DNBLogThreadedIf(LOG_THREAD, "MachThread::SetState ( %s ) for tid = 0x%8.8" PRIx64 "", DNBStateAsString(state), m_unique_id);
-}
-
-nub_size_t
-MachThread::GetNumRegistersInSet(nub_size_t regSet) const
-{
- if (regSet < m_num_reg_sets)
- return m_reg_sets[regSet].num_registers;
- return 0;
-}
-
-const char *
-MachThread::GetRegisterSetName(nub_size_t regSet) const
-{
- if (regSet < m_num_reg_sets)
- return m_reg_sets[regSet].name;
- return NULL;
-}
-
-const DNBRegisterInfo *
-MachThread::GetRegisterInfo(nub_size_t regSet, nub_size_t regIndex) const
-{
- if (regSet < m_num_reg_sets)
- if (regIndex < m_reg_sets[regSet].num_registers)
- return &m_reg_sets[regSet].registers[regIndex];
- return NULL;
-}
-void
-MachThread::DumpRegisterState(nub_size_t regSet)
-{
- if (regSet == REGISTER_SET_ALL)
- {
- for (regSet = 1; regSet < m_num_reg_sets; regSet++)
- DumpRegisterState(regSet);
- }
- else
- {
- if (m_arch_ap->RegisterSetStateIsValid((int)regSet))
- {
- const size_t numRegisters = GetNumRegistersInSet(regSet);
- uint32_t regIndex = 0;
- DNBRegisterValueClass reg;
- for (regIndex = 0; regIndex < numRegisters; ++regIndex)
- {
- if (m_arch_ap->GetRegisterValue((uint32_t)regSet, regIndex, ®))
- {
- reg.Dump(NULL, NULL);
- }
- }
- }
- else
- {
- DNBLog("%s: registers are not currently valid.", GetRegisterSetName(regSet));
- }
+bool MachThread::ThreadDidStop() {
+ // This thread has existed prior to resuming under debug nub control,
+ // and has just been stopped. Do any cleanup that needs to be done
+ // after running.
+
+ // The thread state and breakpoint will still have the same values
+ // as they had prior to resuming the thread, so it makes it easy to check
+ // if we were trying to step a thread, or we tried to resume while being
+ // at a breakpoint.
+
+ // When this method gets called, the process state is still in the
+ // state it was in while running so we can act accordingly.
+ m_arch_ap->ThreadDidStop();
+
+ // We may have suspended this thread so the primary thread could step
+ // without worrying about race conditions, so lets restore our suspend
+ // count.
+ RestoreSuspendCountAfterStop();
+
+ // Update the basic information for a thread
+ MachThread::GetBasicInfo(m_mach_port_number, &m_basic_info);
+
+ if (m_basic_info.suspend_count > 0)
+ SetState(eStateSuspended);
+ else
+ SetState(eStateStopped);
+ return true;
+}
+
+bool MachThread::NotifyException(MachException::Data &exc) {
+ // Allow the arch specific protocol to process (MachException::Data &)exc
+ // first before possible reassignment of m_stop_exception with exc.
+ // See also MachThread::GetStopException().
+ bool handled = m_arch_ap->NotifyException(exc);
+
+ if (m_stop_exception.IsValid()) {
+ // We may have more than one exception for a thread, but we need to
+ // only remember the one that we will say is the reason we stopped.
+ // We may have been single stepping and also gotten a signal exception,
+ // so just remember the most pertinent one.
+ if (m_stop_exception.IsBreakpoint())
+ m_stop_exception = exc;
+ } else {
+ m_stop_exception = exc;
+ }
+
+ return handled;
+}
+
+nub_state_t MachThread::GetState() {
+ // If any other threads access this we will need a mutex for it
+ PTHREAD_MUTEX_LOCKER(locker, m_state_mutex);
+ return m_state;
+}
+
+void MachThread::SetState(nub_state_t state) {
+ PTHREAD_MUTEX_LOCKER(locker, m_state_mutex);
+ m_state = state;
+ DNBLogThreadedIf(LOG_THREAD,
+ "MachThread::SetState ( %s ) for tid = 0x%8.8" PRIx64 "",
+ DNBStateAsString(state), m_unique_id);
+}
+
+nub_size_t MachThread::GetNumRegistersInSet(nub_size_t regSet) const {
+ if (regSet < m_num_reg_sets)
+ return m_reg_sets[regSet].num_registers;
+ return 0;
+}
+
+const char *MachThread::GetRegisterSetName(nub_size_t regSet) const {
+ if (regSet < m_num_reg_sets)
+ return m_reg_sets[regSet].name;
+ return NULL;
+}
+
+const DNBRegisterInfo *MachThread::GetRegisterInfo(nub_size_t regSet,
+ nub_size_t regIndex) const {
+ if (regSet < m_num_reg_sets)
+ if (regIndex < m_reg_sets[regSet].num_registers)
+ return &m_reg_sets[regSet].registers[regIndex];
+ return NULL;
+}
+void MachThread::DumpRegisterState(nub_size_t regSet) {
+ if (regSet == REGISTER_SET_ALL) {
+ for (regSet = 1; regSet < m_num_reg_sets; regSet++)
+ DumpRegisterState(regSet);
+ } else {
+ if (m_arch_ap->RegisterSetStateIsValid((int)regSet)) {
+ const size_t numRegisters = GetNumRegistersInSet(regSet);
+ uint32_t regIndex = 0;
+ DNBRegisterValueClass reg;
+ for (regIndex = 0; regIndex < numRegisters; ++regIndex) {
+ if (m_arch_ap->GetRegisterValue((uint32_t)regSet, regIndex, ®)) {
+ reg.Dump(NULL, NULL);
+ }
+ }
+ } else {
+ DNBLog("%s: registers are not currently valid.",
+ GetRegisterSetName(regSet));
}
+ }
}
const DNBRegisterSetInfo *
-MachThread::GetRegisterSetInfo(nub_size_t *num_reg_sets ) const
-{
- *num_reg_sets = m_num_reg_sets;
- return &m_reg_sets[0];
+MachThread::GetRegisterSetInfo(nub_size_t *num_reg_sets) const {
+ *num_reg_sets = m_num_reg_sets;
+ return &m_reg_sets[0];
}
-bool
-MachThread::GetRegisterValue ( uint32_t set, uint32_t reg, DNBRegisterValue *value )
-{
- return m_arch_ap->GetRegisterValue(set, reg, value);
+bool MachThread::GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value) {
+ return m_arch_ap->GetRegisterValue(set, reg, value);
}
-bool
-MachThread::SetRegisterValue ( uint32_t set, uint32_t reg, const DNBRegisterValue *value )
-{
- return m_arch_ap->SetRegisterValue(set, reg, value);
+bool MachThread::SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value) {
+ return m_arch_ap->SetRegisterValue(set, reg, value);
}
-nub_size_t
-MachThread::GetRegisterContext (void *buf, nub_size_t buf_len)
-{
- return m_arch_ap->GetRegisterContext(buf, buf_len);
+nub_size_t MachThread::GetRegisterContext(void *buf, nub_size_t buf_len) {
+ return m_arch_ap->GetRegisterContext(buf, buf_len);
}
-nub_size_t
-MachThread::SetRegisterContext (const void *buf, nub_size_t buf_len)
-{
- return m_arch_ap->SetRegisterContext(buf, buf_len);
+nub_size_t MachThread::SetRegisterContext(const void *buf, nub_size_t buf_len) {
+ return m_arch_ap->SetRegisterContext(buf, buf_len);
}
-uint32_t
-MachThread::SaveRegisterState ()
-{
- return m_arch_ap->SaveRegisterState();
-
+uint32_t MachThread::SaveRegisterState() {
+ return m_arch_ap->SaveRegisterState();
}
-bool
-MachThread::RestoreRegisterState (uint32_t save_id)
-{
- return m_arch_ap->RestoreRegisterState(save_id);
+bool MachThread::RestoreRegisterState(uint32_t save_id) {
+ return m_arch_ap->RestoreRegisterState(save_id);
}
-uint32_t
-MachThread::EnableHardwareBreakpoint (const DNBBreakpoint *bp)
-{
- if (bp != NULL && bp->IsBreakpoint())
- return m_arch_ap->EnableHardwareBreakpoint(bp->Address(), bp->ByteSize());
- return INVALID_NUB_HW_INDEX;
+uint32_t MachThread::EnableHardwareBreakpoint(const DNBBreakpoint *bp) {
+ if (bp != NULL && bp->IsBreakpoint())
+ return m_arch_ap->EnableHardwareBreakpoint(bp->Address(), bp->ByteSize());
+ return INVALID_NUB_HW_INDEX;
}
-uint32_t
-MachThread::EnableHardwareWatchpoint (const DNBBreakpoint *wp, bool also_set_on_task)
-{
- if (wp != NULL && wp->IsWatchpoint())
- return m_arch_ap->EnableHardwareWatchpoint(wp->Address(), wp->ByteSize(), wp->WatchpointRead(), wp->WatchpointWrite(), also_set_on_task);
- return INVALID_NUB_HW_INDEX;
+uint32_t MachThread::EnableHardwareWatchpoint(const DNBBreakpoint *wp,
+ bool also_set_on_task) {
+ if (wp != NULL && wp->IsWatchpoint())
+ return m_arch_ap->EnableHardwareWatchpoint(
+ wp->Address(), wp->ByteSize(), wp->WatchpointRead(),
+ wp->WatchpointWrite(), also_set_on_task);
+ return INVALID_NUB_HW_INDEX;
}
-bool
-MachThread::RollbackTransForHWP()
-{
- return m_arch_ap->RollbackTransForHWP();
+bool MachThread::RollbackTransForHWP() {
+ return m_arch_ap->RollbackTransForHWP();
}
-bool
-MachThread::FinishTransForHWP()
-{
- return m_arch_ap->FinishTransForHWP();
-}
+bool MachThread::FinishTransForHWP() { return m_arch_ap->FinishTransForHWP(); }
-bool
-MachThread::DisableHardwareBreakpoint (const DNBBreakpoint *bp)
-{
- if (bp != NULL && bp->IsHardware())
- return m_arch_ap->DisableHardwareBreakpoint(bp->GetHardwareIndex());
- return false;
+bool MachThread::DisableHardwareBreakpoint(const DNBBreakpoint *bp) {
+ if (bp != NULL && bp->IsHardware())
+ return m_arch_ap->DisableHardwareBreakpoint(bp->GetHardwareIndex());
+ return false;
}
-bool
-MachThread::DisableHardwareWatchpoint (const DNBBreakpoint *wp, bool also_set_on_task)
-{
- if (wp != NULL && wp->IsHardware())
- return m_arch_ap->DisableHardwareWatchpoint(wp->GetHardwareIndex(), also_set_on_task);
- return false;
+bool MachThread::DisableHardwareWatchpoint(const DNBBreakpoint *wp,
+ bool also_set_on_task) {
+ if (wp != NULL && wp->IsHardware())
+ return m_arch_ap->DisableHardwareWatchpoint(wp->GetHardwareIndex(),
+ also_set_on_task);
+ return false;
}
-uint32_t
-MachThread::NumSupportedHardwareWatchpoints () const
-{
- return m_arch_ap->NumSupportedHardwareWatchpoints();
+uint32_t MachThread::NumSupportedHardwareWatchpoints() const {
+ return m_arch_ap->NumSupportedHardwareWatchpoints();
}
-bool
-MachThread::GetIdentifierInfo ()
-{
- // Don't try to get the thread info once and cache it for the life of the thread. It changes over time, for instance
- // if the thread name changes, then the thread_handle also changes... So you have to refetch it every time.
- mach_msg_type_number_t count = THREAD_IDENTIFIER_INFO_COUNT;
- kern_return_t kret = ::thread_info (m_mach_port_number, THREAD_IDENTIFIER_INFO, (thread_info_t) &m_ident_info, &count);
- return kret == KERN_SUCCESS;
+bool MachThread::GetIdentifierInfo() {
+ // Don't try to get the thread info once and cache it for the life of the
+ // thread. It changes over time, for instance
+ // if the thread name changes, then the thread_handle also changes... So you
+ // have to refetch it every time.
+ mach_msg_type_number_t count = THREAD_IDENTIFIER_INFO_COUNT;
+ kern_return_t kret = ::thread_info(m_mach_port_number, THREAD_IDENTIFIER_INFO,
+ (thread_info_t)&m_ident_info, &count);
+ return kret == KERN_SUCCESS;
- return false;
+ return false;
}
+const char *MachThread::GetName() {
+ if (GetIdentifierInfo()) {
+ int len = ::proc_pidinfo(m_process->ProcessID(), PROC_PIDTHREADINFO,
+ m_ident_info.thread_handle, &m_proc_threadinfo,
+ sizeof(m_proc_threadinfo));
-const char *
-MachThread::GetName ()
-{
- if (GetIdentifierInfo ())
- {
- int len = ::proc_pidinfo (m_process->ProcessID(), PROC_PIDTHREADINFO, m_ident_info.thread_handle, &m_proc_threadinfo, sizeof (m_proc_threadinfo));
-
- if (len && m_proc_threadinfo.pth_name[0])
- return m_proc_threadinfo.pth_name;
- }
- return NULL;
+ if (len && m_proc_threadinfo.pth_name[0])
+ return m_proc_threadinfo.pth_name;
+ }
+ return NULL;
}
+uint64_t
+MachThread::GetGloballyUniqueThreadIDForMachPortID(thread_t mach_port_id) {
+ kern_return_t kr;
+ thread_identifier_info_data_t tident;
+ mach_msg_type_number_t tident_count = THREAD_IDENTIFIER_INFO_COUNT;
+ kr = thread_info(mach_port_id, THREAD_IDENTIFIER_INFO, (thread_info_t)&tident,
+ &tident_count);
+ if (kr != KERN_SUCCESS) {
+ return mach_port_id;
+ }
+ return tident.thread_id;
+}
-uint64_t
-MachThread::GetGloballyUniqueThreadIDForMachPortID (thread_t mach_port_id)
-{
+nub_addr_t MachThread::GetPThreadT() {
+ nub_addr_t pthread_t_value = INVALID_NUB_ADDRESS;
+ if (MachPortNumberIsValid(m_mach_port_number)) {
kern_return_t kr;
thread_identifier_info_data_t tident;
mach_msg_type_number_t tident_count = THREAD_IDENTIFIER_INFO_COUNT;
- kr = thread_info (mach_port_id, THREAD_IDENTIFIER_INFO,
- (thread_info_t) &tident, &tident_count);
- if (kr != KERN_SUCCESS)
- {
- return mach_port_id;
- }
- return tident.thread_id;
-}
-
-nub_addr_t
-MachThread::GetPThreadT ()
-{
- nub_addr_t pthread_t_value = INVALID_NUB_ADDRESS;
- if (MachPortNumberIsValid (m_mach_port_number))
- {
- kern_return_t kr;
- thread_identifier_info_data_t tident;
- mach_msg_type_number_t tident_count = THREAD_IDENTIFIER_INFO_COUNT;
- kr = thread_info (m_mach_port_number, THREAD_IDENTIFIER_INFO,
- (thread_info_t) &tident, &tident_count);
- if (kr == KERN_SUCCESS)
- {
- // Dereference thread_handle to get the pthread_t value for this thread.
- if (m_is_64_bit)
- {
- uint64_t addr;
- if (m_process->ReadMemory (tident.thread_handle, 8, &addr) == 8)
- {
- if (addr != 0)
- {
- pthread_t_value = addr;
- }
- }
- }
- else
- {
- uint32_t addr;
- if (m_process->ReadMemory (tident.thread_handle, 4, &addr) == 4)
- {
- if (addr != 0)
- {
- pthread_t_value = addr;
- }
- }
- }
+ kr = thread_info(m_mach_port_number, THREAD_IDENTIFIER_INFO,
+ (thread_info_t)&tident, &tident_count);
+ if (kr == KERN_SUCCESS) {
+ // Dereference thread_handle to get the pthread_t value for this thread.
+ if (m_is_64_bit) {
+ uint64_t addr;
+ if (m_process->ReadMemory(tident.thread_handle, 8, &addr) == 8) {
+ if (addr != 0) {
+ pthread_t_value = addr;
+ }
+ }
+ } else {
+ uint32_t addr;
+ if (m_process->ReadMemory(tident.thread_handle, 4, &addr) == 4) {
+ if (addr != 0) {
+ pthread_t_value = addr;
+ }
}
+ }
}
- return pthread_t_value;
+ }
+ return pthread_t_value;
}
// Return this thread's TSD (Thread Specific Data) address.
// This is computed based on this thread's pthread_t value.
//
// We compute the TSD from the pthread_t by one of two methods.
-//
-// If plo_pthread_tsd_base_offset is non-zero, this is a simple offset that we add to
+//
+// If plo_pthread_tsd_base_offset is non-zero, this is a simple offset that we
+// add to
// the pthread_t to get the TSD base address.
//
-// Else we read a pointer from memory at pthread_t + plo_pthread_tsd_base_address_offset and
+// Else we read a pointer from memory at pthread_t +
+// plo_pthread_tsd_base_address_offset and
// that gives us the TSD address.
//
-// These plo_pthread_tsd_base values must be read out of libpthread by lldb & provided to debugserver.
-
-nub_addr_t
-MachThread::GetTSDAddressForThread (uint64_t plo_pthread_tsd_base_address_offset, uint64_t plo_pthread_tsd_base_offset, uint64_t plo_pthread_tsd_entry_size)
-{
- nub_addr_t tsd_addr = INVALID_NUB_ADDRESS;
- nub_addr_t pthread_t_value = GetPThreadT();
- if (plo_pthread_tsd_base_offset != 0 && plo_pthread_tsd_base_offset != INVALID_NUB_ADDRESS)
- {
- tsd_addr = pthread_t_value + plo_pthread_tsd_base_offset;
- }
- else
- {
- if (plo_pthread_tsd_entry_size == 4)
- {
- uint32_t addr = 0;
- if (m_process->ReadMemory (pthread_t_value + plo_pthread_tsd_base_address_offset, 4, &addr) == 4)
- {
- if (addr != 0)
- {
- tsd_addr = addr;
- }
- }
- }
- if (plo_pthread_tsd_entry_size == 4)
- {
- uint64_t addr = 0;
- if (m_process->ReadMemory (pthread_t_value + plo_pthread_tsd_base_address_offset, 8, &addr) == 8)
- {
- if (addr != 0)
- {
- tsd_addr = addr;
- }
- }
- }
- }
- return tsd_addr;
-}
-
+// These plo_pthread_tsd_base values must be read out of libpthread by lldb &
+// provided to debugserver.
nub_addr_t
-MachThread::GetDispatchQueueT ()
-{
- nub_addr_t dispatch_queue_t_value = INVALID_NUB_ADDRESS;
- if (MachPortNumberIsValid (m_mach_port_number))
- {
- kern_return_t kr;
- thread_identifier_info_data_t tident;
- mach_msg_type_number_t tident_count = THREAD_IDENTIFIER_INFO_COUNT;
- kr = thread_info (m_mach_port_number, THREAD_IDENTIFIER_INFO,
- (thread_info_t) &tident, &tident_count);
- if (kr == KERN_SUCCESS && tident.dispatch_qaddr != 0 && tident.dispatch_qaddr != INVALID_NUB_ADDRESS)
- {
- // Dereference dispatch_qaddr to get the dispatch_queue_t value for this thread's queue, if any.
- if (m_is_64_bit)
- {
- uint64_t addr;
- if (m_process->ReadMemory (tident.dispatch_qaddr, 8, &addr) == 8)
- {
- if (addr != 0)
- dispatch_queue_t_value = addr;
- }
- }
- else
- {
- uint32_t addr;
- if (m_process->ReadMemory (tident.dispatch_qaddr, 4, &addr) == 4)
- {
- if (addr != 0)
- dispatch_queue_t_value = addr;
- }
- }
- }
- }
- return dispatch_queue_t_value;
-}
-
-
-ThreadInfo::QoS
-MachThread::GetRequestedQoS (nub_addr_t tsd, uint64_t dti_qos_class_index)
-{
- ThreadInfo::QoS qos_value;
- if (MachPortNumberIsValid (m_mach_port_number) && m_pthread_qos_class_decode != nullptr)
- {
- uint64_t pthread_priority_value = 0;
- if (m_is_64_bit)
- {
- uint64_t pri;
- if (m_process->ReadMemory (tsd + (dti_qos_class_index * 8), 8, &pri) == 8)
- {
- pthread_priority_value = pri;
- }
- }
- else
- {
- uint32_t pri;
- if (m_process->ReadMemory (tsd + (dti_qos_class_index * 4), 4, &pri) == 4)
- {
- pthread_priority_value = pri;
- }
- }
-
- uint32_t requested_qos = m_pthread_qos_class_decode (pthread_priority_value, NULL, NULL);
-
- switch (requested_qos)
- {
- // These constants from <pthread/qos.h>
- case 0x21:
- qos_value.enum_value = requested_qos;
- qos_value.constant_name = "QOS_CLASS_USER_INTERACTIVE";
- qos_value.printable_name = "User Interactive";
- break;
- case 0x19:
- qos_value.enum_value = requested_qos;
- qos_value.constant_name = "QOS_CLASS_USER_INITIATED";
- qos_value.printable_name = "User Initiated";
- break;
- case 0x15:
- qos_value.enum_value = requested_qos;
- qos_value.constant_name = "QOS_CLASS_DEFAULT";
- qos_value.printable_name = "Default";
- break;
- case 0x11:
- qos_value.enum_value = requested_qos;
- qos_value.constant_name = "QOS_CLASS_UTILITY";
- qos_value.printable_name = "Utility";
- break;
- case 0x09:
- qos_value.enum_value = requested_qos;
- qos_value.constant_name = "QOS_CLASS_BACKGROUND";
- qos_value.printable_name = "Background";
- break;
- case 0x00:
- qos_value.enum_value = requested_qos;
- qos_value.constant_name = "QOS_CLASS_UNSPECIFIED";
- qos_value.printable_name = "Unspecified";
- break;
- }
+MachThread::GetTSDAddressForThread(uint64_t plo_pthread_tsd_base_address_offset,
+ uint64_t plo_pthread_tsd_base_offset,
+ uint64_t plo_pthread_tsd_entry_size) {
+ nub_addr_t tsd_addr = INVALID_NUB_ADDRESS;
+ nub_addr_t pthread_t_value = GetPThreadT();
+ if (plo_pthread_tsd_base_offset != 0 &&
+ plo_pthread_tsd_base_offset != INVALID_NUB_ADDRESS) {
+ tsd_addr = pthread_t_value + plo_pthread_tsd_base_offset;
+ } else {
+ if (plo_pthread_tsd_entry_size == 4) {
+ uint32_t addr = 0;
+ if (m_process->ReadMemory(pthread_t_value +
+ plo_pthread_tsd_base_address_offset,
+ 4, &addr) == 4) {
+ if (addr != 0) {
+ tsd_addr = addr;
+ }
+ }
+ }
+ if (plo_pthread_tsd_entry_size == 4) {
+ uint64_t addr = 0;
+ if (m_process->ReadMemory(pthread_t_value +
+ plo_pthread_tsd_base_address_offset,
+ 8, &addr) == 8) {
+ if (addr != 0) {
+ tsd_addr = addr;
+ }
+ }
+ }
+ }
+ return tsd_addr;
+}
+
+nub_addr_t MachThread::GetDispatchQueueT() {
+ nub_addr_t dispatch_queue_t_value = INVALID_NUB_ADDRESS;
+ if (MachPortNumberIsValid(m_mach_port_number)) {
+ kern_return_t kr;
+ thread_identifier_info_data_t tident;
+ mach_msg_type_number_t tident_count = THREAD_IDENTIFIER_INFO_COUNT;
+ kr = thread_info(m_mach_port_number, THREAD_IDENTIFIER_INFO,
+ (thread_info_t)&tident, &tident_count);
+ if (kr == KERN_SUCCESS && tident.dispatch_qaddr != 0 &&
+ tident.dispatch_qaddr != INVALID_NUB_ADDRESS) {
+ // Dereference dispatch_qaddr to get the dispatch_queue_t value for this
+ // thread's queue, if any.
+ if (m_is_64_bit) {
+ uint64_t addr;
+ if (m_process->ReadMemory(tident.dispatch_qaddr, 8, &addr) == 8) {
+ if (addr != 0)
+ dispatch_queue_t_value = addr;
+ }
+ } else {
+ uint32_t addr;
+ if (m_process->ReadMemory(tident.dispatch_qaddr, 4, &addr) == 4) {
+ if (addr != 0)
+ dispatch_queue_t_value = addr;
+ }
+ }
+ }
+ }
+ return dispatch_queue_t_value;
+}
+
+ThreadInfo::QoS MachThread::GetRequestedQoS(nub_addr_t tsd,
+ uint64_t dti_qos_class_index) {
+ ThreadInfo::QoS qos_value;
+ if (MachPortNumberIsValid(m_mach_port_number) &&
+ m_pthread_qos_class_decode != nullptr) {
+ uint64_t pthread_priority_value = 0;
+ if (m_is_64_bit) {
+ uint64_t pri;
+ if (m_process->ReadMemory(tsd + (dti_qos_class_index * 8), 8, &pri) ==
+ 8) {
+ pthread_priority_value = pri;
+ }
+ } else {
+ uint32_t pri;
+ if (m_process->ReadMemory(tsd + (dti_qos_class_index * 4), 4, &pri) ==
+ 4) {
+ pthread_priority_value = pri;
+ }
+ }
+
+ uint32_t requested_qos =
+ m_pthread_qos_class_decode(pthread_priority_value, NULL, NULL);
+
+ switch (requested_qos) {
+ // These constants from <pthread/qos.h>
+ case 0x21:
+ qos_value.enum_value = requested_qos;
+ qos_value.constant_name = "QOS_CLASS_USER_INTERACTIVE";
+ qos_value.printable_name = "User Interactive";
+ break;
+ case 0x19:
+ qos_value.enum_value = requested_qos;
+ qos_value.constant_name = "QOS_CLASS_USER_INITIATED";
+ qos_value.printable_name = "User Initiated";
+ break;
+ case 0x15:
+ qos_value.enum_value = requested_qos;
+ qos_value.constant_name = "QOS_CLASS_DEFAULT";
+ qos_value.printable_name = "Default";
+ break;
+ case 0x11:
+ qos_value.enum_value = requested_qos;
+ qos_value.constant_name = "QOS_CLASS_UTILITY";
+ qos_value.printable_name = "Utility";
+ break;
+ case 0x09:
+ qos_value.enum_value = requested_qos;
+ qos_value.constant_name = "QOS_CLASS_BACKGROUND";
+ qos_value.printable_name = "Background";
+ break;
+ case 0x00:
+ qos_value.enum_value = requested_qos;
+ qos_value.constant_name = "QOS_CLASS_UNSPECIFIED";
+ qos_value.printable_name = "Unspecified";
+ break;
}
- return qos_value;
+ }
+ return qos_value;
}
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachThread.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachThread.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachThread.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachThread.h Tue Sep 6 15:57:50 2016
@@ -22,11 +22,11 @@
#include <pthread.h>
#include <sys/signal.h>
-#include "PThreadCondition.h"
-#include "PThreadMutex.h"
-#include "MachException.h"
#include "DNBArch.h"
#include "DNBRegisterInfo.h"
+#include "MachException.h"
+#include "PThreadCondition.h"
+#include "PThreadMutex.h"
#include "ThreadInfo.h"
@@ -34,124 +34,135 @@ class DNBBreakpoint;
class MachProcess;
class MachThreadList;
-class MachThread
-{
+class MachThread {
public:
+ MachThread(MachProcess *process, bool is_64_bit,
+ uint64_t unique_thread_id = 0, thread_t mach_port_number = 0);
+ ~MachThread();
+
+ MachProcess *Process() { return m_process; }
+ const MachProcess *Process() const { return m_process; }
+ nub_process_t ProcessID() const;
+ void Dump(uint32_t index);
+ uint64_t ThreadID() const { return m_unique_id; }
+ thread_t MachPortNumber() const { return m_mach_port_number; }
+ thread_t InferiorThreadID() const;
+
+ uint32_t SequenceID() const { return m_seq_id; }
+ static bool ThreadIDIsValid(
+ uint64_t thread); // The 64-bit system-wide unique thread identifier
+ static bool MachPortNumberIsValid(thread_t thread); // The mach port # for
+ // this thread in
+ // debugserver namespace
+ void Resume(bool others_stopped);
+ void Suspend();
+ bool SetSuspendCountBeforeResume(bool others_stopped);
+ bool RestoreSuspendCountAfterStop();
+
+ bool GetRegisterState(int flavor, bool force);
+ bool SetRegisterState(int flavor);
+ uint64_t
+ GetPC(uint64_t failValue = INVALID_NUB_ADDRESS); // Get program counter
+ bool SetPC(uint64_t value); // Set program counter
+ uint64_t GetSP(uint64_t failValue = INVALID_NUB_ADDRESS); // Get stack pointer
+
+ DNBBreakpoint *CurrentBreakpoint();
+ uint32_t EnableHardwareBreakpoint(const DNBBreakpoint *breakpoint);
+ uint32_t EnableHardwareWatchpoint(const DNBBreakpoint *watchpoint,
+ bool also_set_on_task);
+ bool DisableHardwareBreakpoint(const DNBBreakpoint *breakpoint);
+ bool DisableHardwareWatchpoint(const DNBBreakpoint *watchpoint,
+ bool also_set_on_task);
+ uint32_t NumSupportedHardwareWatchpoints() const;
+ bool RollbackTransForHWP();
+ bool FinishTransForHWP();
+
+ nub_state_t GetState();
+ void SetState(nub_state_t state);
+
+ void ThreadWillResume(const DNBThreadResumeAction *thread_action,
+ bool others_stopped = false);
+ bool ShouldStop(bool &step_more);
+ bool IsStepping();
+ bool ThreadDidStop();
+ bool NotifyException(MachException::Data &exc);
+ const MachException::Data &GetStopException() { return m_stop_exception; }
+
+ nub_size_t GetNumRegistersInSet(nub_size_t regSet) const;
+ const char *GetRegisterSetName(nub_size_t regSet) const;
+ const DNBRegisterInfo *GetRegisterInfo(nub_size_t regSet,
+ nub_size_t regIndex) const;
+ void DumpRegisterState(nub_size_t regSet);
+ const DNBRegisterSetInfo *GetRegisterSetInfo(nub_size_t *num_reg_sets) const;
+ bool GetRegisterValue(uint32_t reg_set_idx, uint32_t reg_idx,
+ DNBRegisterValue *reg_value);
+ bool SetRegisterValue(uint32_t reg_set_idx, uint32_t reg_idx,
+ const DNBRegisterValue *reg_value);
+ nub_size_t GetRegisterContext(void *buf, nub_size_t buf_len);
+ nub_size_t SetRegisterContext(const void *buf, nub_size_t buf_len);
+ uint32_t SaveRegisterState();
+ bool RestoreRegisterState(uint32_t save_id);
+
+ void NotifyBreakpointChanged(const DNBBreakpoint *bp) {}
+
+ bool IsUserReady();
+ struct thread_basic_info *GetBasicInfo();
+ const char *GetBasicInfoAsString() const;
+ const char *GetName();
+
+ DNBArchProtocol *GetArchProtocol() { return m_arch_ap.get(); }
+
+ ThreadInfo::QoS GetRequestedQoS(nub_addr_t tsd, uint64_t dti_qos_class_index);
+ nub_addr_t GetPThreadT();
+ nub_addr_t GetDispatchQueueT();
+ nub_addr_t
+ GetTSDAddressForThread(uint64_t plo_pthread_tsd_base_address_offset,
+ uint64_t plo_pthread_tsd_base_offset,
+ uint64_t plo_pthread_tsd_entry_size);
- MachThread (MachProcess *process, bool is_64_bit, uint64_t unique_thread_id = 0, thread_t mach_port_number = 0);
- ~MachThread ();
-
- MachProcess * Process() { return m_process; }
- const MachProcess *
- Process() const { return m_process; }
- nub_process_t ProcessID() const;
- void Dump(uint32_t index);
- uint64_t ThreadID() const { return m_unique_id; }
- thread_t MachPortNumber() const { return m_mach_port_number; }
- thread_t InferiorThreadID() const;
-
- uint32_t SequenceID() const { return m_seq_id; }
- static bool ThreadIDIsValid(uint64_t thread); // The 64-bit system-wide unique thread identifier
- static bool MachPortNumberIsValid(thread_t thread); // The mach port # for this thread in debugserver namespace
- void Resume(bool others_stopped);
- void Suspend();
- bool SetSuspendCountBeforeResume(bool others_stopped);
- bool RestoreSuspendCountAfterStop();
-
- bool GetRegisterState(int flavor, bool force);
- bool SetRegisterState(int flavor);
- uint64_t GetPC(uint64_t failValue = INVALID_NUB_ADDRESS); // Get program counter
- bool SetPC(uint64_t value); // Set program counter
- uint64_t GetSP(uint64_t failValue = INVALID_NUB_ADDRESS); // Get stack pointer
-
- DNBBreakpoint * CurrentBreakpoint();
- uint32_t EnableHardwareBreakpoint (const DNBBreakpoint *breakpoint);
- uint32_t EnableHardwareWatchpoint (const DNBBreakpoint *watchpoint, bool also_set_on_task);
- bool DisableHardwareBreakpoint (const DNBBreakpoint *breakpoint);
- bool DisableHardwareWatchpoint (const DNBBreakpoint *watchpoint, bool also_set_on_task);
- uint32_t NumSupportedHardwareWatchpoints () const;
- bool RollbackTransForHWP();
- bool FinishTransForHWP();
-
- nub_state_t GetState();
- void SetState(nub_state_t state);
-
- void ThreadWillResume (const DNBThreadResumeAction *thread_action, bool others_stopped = false);
- bool ShouldStop(bool &step_more);
- bool IsStepping();
- bool ThreadDidStop();
- bool NotifyException(MachException::Data& exc);
- const MachException::Data& GetStopException() { return m_stop_exception; }
-
- nub_size_t GetNumRegistersInSet(nub_size_t regSet) const;
- const char * GetRegisterSetName(nub_size_t regSet) const;
- const DNBRegisterInfo *
- GetRegisterInfo(nub_size_t regSet, nub_size_t regIndex) const;
- void DumpRegisterState(nub_size_t regSet);
- const DNBRegisterSetInfo *
- GetRegisterSetInfo(nub_size_t *num_reg_sets ) const;
- bool GetRegisterValue ( uint32_t reg_set_idx, uint32_t reg_idx, DNBRegisterValue *reg_value );
- bool SetRegisterValue ( uint32_t reg_set_idx, uint32_t reg_idx, const DNBRegisterValue *reg_value );
- nub_size_t GetRegisterContext (void *buf, nub_size_t buf_len);
- nub_size_t SetRegisterContext (const void *buf, nub_size_t buf_len);
- uint32_t SaveRegisterState ();
- bool RestoreRegisterState (uint32_t save_id);
-
- void NotifyBreakpointChanged (const DNBBreakpoint *bp)
- {
- }
-
- bool IsUserReady();
- struct thread_basic_info *
- GetBasicInfo ();
- const char * GetBasicInfoAsString () const;
- const char * GetName ();
-
- DNBArchProtocol*
- GetArchProtocol()
- {
- return m_arch_ap.get();
- }
-
- ThreadInfo::QoS GetRequestedQoS (nub_addr_t tsd, uint64_t dti_qos_class_index);
- nub_addr_t GetPThreadT();
- nub_addr_t GetDispatchQueueT();
- nub_addr_t GetTSDAddressForThread (uint64_t plo_pthread_tsd_base_address_offset, uint64_t plo_pthread_tsd_base_offset, uint64_t plo_pthread_tsd_entry_size);
-
- static uint64_t GetGloballyUniqueThreadIDForMachPortID (thread_t mach_port_id);
+ static uint64_t GetGloballyUniqueThreadIDForMachPortID(thread_t mach_port_id);
protected:
- static bool GetBasicInfo(thread_t threadID, struct thread_basic_info *basic_info);
-
- bool
- GetIdentifierInfo ();
+ static bool GetBasicInfo(thread_t threadID,
+ struct thread_basic_info *basic_info);
-// const char *
-// GetDispatchQueueName();
-//
- MachProcess * m_process; // The process that owns this thread
- uint64_t m_unique_id; // The globally unique ID for this thread (nub_thread_t)
- thread_t m_mach_port_number; // The mach port # for this thread in debugserver namesp.
- uint32_t m_seq_id; // A Sequential ID that increments with each new thread
- nub_state_t m_state; // The state of our process
- PThreadMutex m_state_mutex; // Multithreaded protection for m_state
- struct thread_basic_info m_basic_info; // Basic information for a thread used to see if a thread is valid
- int32_t m_suspend_count; // The current suspend count > 0 means we have suspended m_suspendCount times,
- // < 0 means we have resumed it m_suspendCount times.
- MachException::Data m_stop_exception; // The best exception that describes why this thread is stopped
- std::unique_ptr<DNBArchProtocol> m_arch_ap; // Arch specific information for register state and more
- const DNBRegisterSetInfo * m_reg_sets; // Register set information for this thread
- nub_size_t m_num_reg_sets;
- thread_identifier_info_data_t m_ident_info;
- struct proc_threadinfo m_proc_threadinfo;
- std::string m_dispatch_queue_name;
- bool m_is_64_bit;
+ bool GetIdentifierInfo();
- // qos_class_t _pthread_qos_class_decode(pthread_priority_t priority, int *, unsigned long *);
- unsigned int (*m_pthread_qos_class_decode) (unsigned long priority, int*, unsigned long *);
+ // const char *
+ // GetDispatchQueueName();
+ //
+ MachProcess *m_process; // The process that owns this thread
+ uint64_t m_unique_id; // The globally unique ID for this thread (nub_thread_t)
+ thread_t m_mach_port_number; // The mach port # for this thread in debugserver
+ // namesp.
+ uint32_t m_seq_id; // A Sequential ID that increments with each new thread
+ nub_state_t m_state; // The state of our process
+ PThreadMutex m_state_mutex; // Multithreaded protection for m_state
+ struct thread_basic_info m_basic_info; // Basic information for a thread used
+ // to see if a thread is valid
+ int32_t m_suspend_count; // The current suspend count > 0 means we have
+ // suspended m_suspendCount times,
+ // < 0 means we have resumed it m_suspendCount
+ // times.
+ MachException::Data m_stop_exception; // The best exception that describes why
+ // this thread is stopped
+ std::unique_ptr<DNBArchProtocol>
+ m_arch_ap; // Arch specific information for register state and more
+ const DNBRegisterSetInfo
+ *m_reg_sets; // Register set information for this thread
+ nub_size_t m_num_reg_sets;
+ thread_identifier_info_data_t m_ident_info;
+ struct proc_threadinfo m_proc_threadinfo;
+ std::string m_dispatch_queue_name;
+ bool m_is_64_bit;
+
+ // qos_class_t _pthread_qos_class_decode(pthread_priority_t priority, int *,
+ // unsigned long *);
+ unsigned int (*m_pthread_qos_class_decode)(unsigned long priority, int *,
+ unsigned long *);
private:
- friend class MachThreadList;
+ friend class MachThreadList;
};
typedef std::shared_ptr<MachThread> MachThreadSP;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.cpp Tue Sep 6 15:57:50 2016
@@ -20,501 +20,434 @@
#include "DNBThreadResumeActions.h"
#include "MachProcess.h"
-MachThreadList::MachThreadList() :
- m_threads(),
- m_threads_mutex(PTHREAD_MUTEX_RECURSIVE),
- m_is_64_bit(false)
-{
-}
-
-MachThreadList::~MachThreadList()
-{
-}
-
-nub_state_t
-MachThreadList::GetState(nub_thread_t tid)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetState();
- return eStateInvalid;
-}
-
-const char *
-MachThreadList::GetName (nub_thread_t tid)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetName();
- return NULL;
-}
-
-ThreadInfo::QoS
-MachThreadList::GetRequestedQoS (nub_thread_t tid, nub_addr_t tsd, uint64_t dti_qos_class_index)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetRequestedQoS(tsd, dti_qos_class_index);
- return ThreadInfo::QoS();
-}
-
-nub_addr_t
-MachThreadList::GetPThreadT (nub_thread_t tid)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetPThreadT();
- return INVALID_NUB_ADDRESS;
-}
-
-nub_addr_t
-MachThreadList::GetDispatchQueueT (nub_thread_t tid)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetDispatchQueueT();
- return INVALID_NUB_ADDRESS;
-}
-
-nub_addr_t
-MachThreadList::GetTSDAddressForThread (nub_thread_t tid, uint64_t plo_pthread_tsd_base_address_offset, uint64_t plo_pthread_tsd_base_offset, uint64_t plo_pthread_tsd_entry_size)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetTSDAddressForThread(plo_pthread_tsd_base_address_offset, plo_pthread_tsd_base_offset, plo_pthread_tsd_entry_size);
- return INVALID_NUB_ADDRESS;
-}
-
-nub_thread_t
-MachThreadList::SetCurrentThread(nub_thread_t tid)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- {
- m_current_thread = thread_sp;
- return tid;
- }
- return INVALID_NUB_THREAD;
-}
-
-
-bool
-MachThreadList::GetThreadStoppedReason(nub_thread_t tid, struct DNBThreadStopInfo *stop_info) const
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetStopException().GetStopInfo(stop_info);
- return false;
-}
-
-bool
-MachThreadList::GetIdentifierInfo (nub_thread_t tid, thread_identifier_info_data_t *ident_info)
-{
- thread_t mach_port_number = GetMachPortNumberByThreadID (tid);
-
- mach_msg_type_number_t count = THREAD_IDENTIFIER_INFO_COUNT;
- return ::thread_info (mach_port_number, THREAD_IDENTIFIER_INFO, (thread_info_t)ident_info, &count) == KERN_SUCCESS;
-}
-
-void
-MachThreadList::DumpThreadStoppedReason (nub_thread_t tid) const
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- thread_sp->GetStopException().DumpStopReason();
-}
-
-const char *
-MachThreadList::GetThreadInfo (nub_thread_t tid) const
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetBasicInfoAsString();
- return NULL;
-}
-
-MachThreadSP
-MachThreadList::GetThreadByID (nub_thread_t tid) const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- MachThreadSP thread_sp;
- const size_t num_threads = m_threads.size();
- for (size_t idx = 0; idx < num_threads; ++idx)
- {
- if (m_threads[idx]->ThreadID() == tid)
- {
- thread_sp = m_threads[idx];
- break;
- }
+MachThreadList::MachThreadList()
+ : m_threads(), m_threads_mutex(PTHREAD_MUTEX_RECURSIVE),
+ m_is_64_bit(false) {}
+
+MachThreadList::~MachThreadList() {}
+
+nub_state_t MachThreadList::GetState(nub_thread_t tid) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetState();
+ return eStateInvalid;
+}
+
+const char *MachThreadList::GetName(nub_thread_t tid) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetName();
+ return NULL;
+}
+
+ThreadInfo::QoS MachThreadList::GetRequestedQoS(nub_thread_t tid,
+ nub_addr_t tsd,
+ uint64_t dti_qos_class_index) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetRequestedQoS(tsd, dti_qos_class_index);
+ return ThreadInfo::QoS();
+}
+
+nub_addr_t MachThreadList::GetPThreadT(nub_thread_t tid) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetPThreadT();
+ return INVALID_NUB_ADDRESS;
+}
+
+nub_addr_t MachThreadList::GetDispatchQueueT(nub_thread_t tid) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetDispatchQueueT();
+ return INVALID_NUB_ADDRESS;
+}
+
+nub_addr_t MachThreadList::GetTSDAddressForThread(
+ nub_thread_t tid, uint64_t plo_pthread_tsd_base_address_offset,
+ uint64_t plo_pthread_tsd_base_offset, uint64_t plo_pthread_tsd_entry_size) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetTSDAddressForThread(
+ plo_pthread_tsd_base_address_offset, plo_pthread_tsd_base_offset,
+ plo_pthread_tsd_entry_size);
+ return INVALID_NUB_ADDRESS;
+}
+
+nub_thread_t MachThreadList::SetCurrentThread(nub_thread_t tid) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp) {
+ m_current_thread = thread_sp;
+ return tid;
+ }
+ return INVALID_NUB_THREAD;
+}
+
+bool MachThreadList::GetThreadStoppedReason(
+ nub_thread_t tid, struct DNBThreadStopInfo *stop_info) const {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetStopException().GetStopInfo(stop_info);
+ return false;
+}
+
+bool MachThreadList::GetIdentifierInfo(
+ nub_thread_t tid, thread_identifier_info_data_t *ident_info) {
+ thread_t mach_port_number = GetMachPortNumberByThreadID(tid);
+
+ mach_msg_type_number_t count = THREAD_IDENTIFIER_INFO_COUNT;
+ return ::thread_info(mach_port_number, THREAD_IDENTIFIER_INFO,
+ (thread_info_t)ident_info, &count) == KERN_SUCCESS;
+}
+
+void MachThreadList::DumpThreadStoppedReason(nub_thread_t tid) const {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ thread_sp->GetStopException().DumpStopReason();
+}
+
+const char *MachThreadList::GetThreadInfo(nub_thread_t tid) const {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetBasicInfoAsString();
+ return NULL;
+}
+
+MachThreadSP MachThreadList::GetThreadByID(nub_thread_t tid) const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ MachThreadSP thread_sp;
+ const size_t num_threads = m_threads.size();
+ for (size_t idx = 0; idx < num_threads; ++idx) {
+ if (m_threads[idx]->ThreadID() == tid) {
+ thread_sp = m_threads[idx];
+ break;
}
- return thread_sp;
+ }
+ return thread_sp;
}
MachThreadSP
-MachThreadList::GetThreadByMachPortNumber (thread_t mach_port_number) const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- MachThreadSP thread_sp;
- const size_t num_threads = m_threads.size();
- for (size_t idx = 0; idx < num_threads; ++idx)
- {
- if (m_threads[idx]->MachPortNumber() == mach_port_number)
- {
- thread_sp = m_threads[idx];
- break;
- }
+MachThreadList::GetThreadByMachPortNumber(thread_t mach_port_number) const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ MachThreadSP thread_sp;
+ const size_t num_threads = m_threads.size();
+ for (size_t idx = 0; idx < num_threads; ++idx) {
+ if (m_threads[idx]->MachPortNumber() == mach_port_number) {
+ thread_sp = m_threads[idx];
+ break;
}
- return thread_sp;
+ }
+ return thread_sp;
}
nub_thread_t
-MachThreadList::GetThreadIDByMachPortNumber (thread_t mach_port_number) const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- MachThreadSP thread_sp;
- const size_t num_threads = m_threads.size();
- for (size_t idx = 0; idx < num_threads; ++idx)
- {
- if (m_threads[idx]->MachPortNumber() == mach_port_number)
- {
- return m_threads[idx]->ThreadID();
- }
+MachThreadList::GetThreadIDByMachPortNumber(thread_t mach_port_number) const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ MachThreadSP thread_sp;
+ const size_t num_threads = m_threads.size();
+ for (size_t idx = 0; idx < num_threads; ++idx) {
+ if (m_threads[idx]->MachPortNumber() == mach_port_number) {
+ return m_threads[idx]->ThreadID();
}
- return INVALID_NUB_THREAD;
+ }
+ return INVALID_NUB_THREAD;
}
-thread_t
-MachThreadList::GetMachPortNumberByThreadID (nub_thread_t globally_unique_id) const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- MachThreadSP thread_sp;
- const size_t num_threads = m_threads.size();
- for (size_t idx = 0; idx < num_threads; ++idx)
- {
- if (m_threads[idx]->ThreadID() == globally_unique_id)
- {
- return m_threads[idx]->MachPortNumber();
- }
+thread_t MachThreadList::GetMachPortNumberByThreadID(
+ nub_thread_t globally_unique_id) const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ MachThreadSP thread_sp;
+ const size_t num_threads = m_threads.size();
+ for (size_t idx = 0; idx < num_threads; ++idx) {
+ if (m_threads[idx]->ThreadID() == globally_unique_id) {
+ return m_threads[idx]->MachPortNumber();
}
- return 0;
+ }
+ return 0;
}
-bool
-MachThreadList::GetRegisterValue (nub_thread_t tid, uint32_t set, uint32_t reg, DNBRegisterValue *reg_value ) const
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetRegisterValue(set, reg, reg_value);
+bool MachThreadList::GetRegisterValue(nub_thread_t tid, uint32_t set,
+ uint32_t reg,
+ DNBRegisterValue *reg_value) const {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetRegisterValue(set, reg, reg_value);
- return false;
+ return false;
}
-bool
-MachThreadList::SetRegisterValue (nub_thread_t tid, uint32_t set, uint32_t reg, const DNBRegisterValue *reg_value ) const
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->SetRegisterValue(set, reg, reg_value);
+bool MachThreadList::SetRegisterValue(nub_thread_t tid, uint32_t set,
+ uint32_t reg,
+ const DNBRegisterValue *reg_value) const {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->SetRegisterValue(set, reg, reg_value);
- return false;
+ return false;
}
-nub_size_t
-MachThreadList::GetRegisterContext (nub_thread_t tid, void *buf, size_t buf_len)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->GetRegisterContext (buf, buf_len);
- return 0;
+nub_size_t MachThreadList::GetRegisterContext(nub_thread_t tid, void *buf,
+ size_t buf_len) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->GetRegisterContext(buf, buf_len);
+ return 0;
}
-nub_size_t
-MachThreadList::SetRegisterContext (nub_thread_t tid, const void *buf, size_t buf_len)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->SetRegisterContext (buf, buf_len);
- return 0;
+nub_size_t MachThreadList::SetRegisterContext(nub_thread_t tid, const void *buf,
+ size_t buf_len) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->SetRegisterContext(buf, buf_len);
+ return 0;
}
-uint32_t
-MachThreadList::SaveRegisterState (nub_thread_t tid)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->SaveRegisterState ();
- return 0;
-}
-
-bool
-MachThreadList::RestoreRegisterState (nub_thread_t tid, uint32_t save_id)
-{
- MachThreadSP thread_sp (GetThreadByID (tid));
- if (thread_sp)
- return thread_sp->RestoreRegisterState (save_id);
- return 0;
+uint32_t MachThreadList::SaveRegisterState(nub_thread_t tid) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->SaveRegisterState();
+ return 0;
}
-
-nub_size_t
-MachThreadList::NumThreads () const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- return m_threads.size();
+bool MachThreadList::RestoreRegisterState(nub_thread_t tid, uint32_t save_id) {
+ MachThreadSP thread_sp(GetThreadByID(tid));
+ if (thread_sp)
+ return thread_sp->RestoreRegisterState(save_id);
+ return 0;
}
-nub_thread_t
-MachThreadList::ThreadIDAtIndex (nub_size_t idx) const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- if (idx < m_threads.size())
- return m_threads[idx]->ThreadID();
- return INVALID_NUB_THREAD;
+nub_size_t MachThreadList::NumThreads() const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ return m_threads.size();
}
-nub_thread_t
-MachThreadList::CurrentThreadID ( )
-{
- MachThreadSP thread_sp;
- CurrentThread(thread_sp);
- if (thread_sp.get())
- return thread_sp->ThreadID();
- return INVALID_NUB_THREAD;
-}
-
-bool
-MachThreadList::NotifyException(MachException::Data& exc)
-{
- MachThreadSP thread_sp (GetThreadByMachPortNumber (exc.thread_port));
- if (thread_sp)
- {
- thread_sp->NotifyException(exc);
- return true;
- }
- return false;
-}
-
-void
-MachThreadList::Clear()
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- m_threads.clear();
+nub_thread_t MachThreadList::ThreadIDAtIndex(nub_size_t idx) const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ if (idx < m_threads.size())
+ return m_threads[idx]->ThreadID();
+ return INVALID_NUB_THREAD;
}
-uint32_t
-MachThreadList::UpdateThreadList(MachProcess *process, bool update, MachThreadList::collection *new_threads)
-{
- // locker will keep a mutex locked until it goes out of scope
- DNBLogThreadedIf (LOG_THREAD, "MachThreadList::UpdateThreadList (pid = %4.4x, update = %u) process stop count = %u", process->ProcessID(), update, process->StopCount());
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
-
- if (process->StopCount() == 0)
- {
- int mib[4] = { CTL_KERN, KERN_PROC, KERN_PROC_PID, process->ProcessID() };
- struct kinfo_proc processInfo;
- size_t bufsize = sizeof(processInfo);
- if (sysctl(mib, (unsigned)(sizeof(mib)/sizeof(int)), &processInfo, &bufsize, NULL, 0) == 0 && bufsize > 0)
- {
- if (processInfo.kp_proc.p_flag & P_LP64)
- m_is_64_bit = true;
- }
-#if defined (__i386__) || defined (__x86_64__)
- if (m_is_64_bit)
- DNBArchProtocol::SetArchitecture(CPU_TYPE_X86_64);
- else
- DNBArchProtocol::SetArchitecture(CPU_TYPE_I386);
-#elif defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
- if (m_is_64_bit)
- DNBArchProtocol::SetArchitecture(CPU_TYPE_ARM64);
- else
- DNBArchProtocol::SetArchitecture(CPU_TYPE_ARM);
-#endif
- }
-
- if (m_threads.empty() || update)
- {
- thread_array_t thread_list = NULL;
- mach_msg_type_number_t thread_list_count = 0;
- task_t task = process->Task().TaskPort();
- DNBError err(::task_threads (task, &thread_list, &thread_list_count), DNBError::MachKernel);
-
- if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
- err.LogThreaded("::task_threads ( task = 0x%4.4x, thread_list => %p, thread_list_count => %u )", task, thread_list, thread_list_count);
-
- if (err.Error() == KERN_SUCCESS && thread_list_count > 0)
- {
- MachThreadList::collection currThreads;
- size_t idx;
- // Iterator through the current thread list and see which threads
- // we already have in our list (keep them), which ones we don't
- // (add them), and which ones are not around anymore (remove them).
- for (idx = 0; idx < thread_list_count; ++idx)
- {
- const thread_t mach_port_num = thread_list[idx];
-
- uint64_t unique_thread_id = MachThread::GetGloballyUniqueThreadIDForMachPortID (mach_port_num);
- MachThreadSP thread_sp (GetThreadByID (unique_thread_id));
- if (thread_sp)
- {
- // Keep the existing thread class
- currThreads.push_back(thread_sp);
- }
- else
- {
- // We don't have this thread, lets add it.
- thread_sp.reset(new MachThread(process, m_is_64_bit, unique_thread_id, mach_port_num));
-
- // Add the new thread regardless of its is user ready state...
- // Make sure the thread is ready to be displayed and shown to users
- // before we add this thread to our list...
- if (thread_sp->IsUserReady())
- {
- if (new_threads)
- new_threads->push_back(thread_sp);
-
- currThreads.push_back(thread_sp);
- }
- }
- }
-
- m_threads.swap(currThreads);
- m_current_thread.reset();
-
- // Free the vm memory given to us by ::task_threads()
- vm_size_t thread_list_size = (vm_size_t) (thread_list_count * sizeof (thread_t));
- ::vm_deallocate (::mach_task_self(),
- (vm_address_t)thread_list,
- thread_list_size);
- }
- }
- return static_cast<uint32_t>(m_threads.size());
+nub_thread_t MachThreadList::CurrentThreadID() {
+ MachThreadSP thread_sp;
+ CurrentThread(thread_sp);
+ if (thread_sp.get())
+ return thread_sp->ThreadID();
+ return INVALID_NUB_THREAD;
}
-
-void
-MachThreadList::CurrentThread (MachThreadSP& thread_sp)
-{
- // locker will keep a mutex locked until it goes out of scope
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- if (m_current_thread.get() == NULL)
- {
- // Figure out which thread is going to be our current thread.
- // This is currently done by finding the first thread in the list
- // that has a valid exception.
- const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- if (m_threads[idx]->GetStopException().IsValid())
- {
- m_current_thread = m_threads[idx];
- break;
- }
- }
- }
- thread_sp = m_current_thread;
+bool MachThreadList::NotifyException(MachException::Data &exc) {
+ MachThreadSP thread_sp(GetThreadByMachPortNumber(exc.thread_port));
+ if (thread_sp) {
+ thread_sp->NotifyException(exc);
+ return true;
+ }
+ return false;
}
-void
-MachThreadList::Dump() const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- m_threads[idx]->Dump(idx);
- }
+void MachThreadList::Clear() {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ m_threads.clear();
}
-
-void
-MachThreadList::ProcessWillResume(MachProcess *process, const DNBThreadResumeActions &thread_actions)
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
-
- // Update our thread list, because sometimes libdispatch or the kernel
- // will spawn threads while a task is suspended.
- MachThreadList::collection new_threads;
-
- // First figure out if we were planning on running only one thread, and if so force that thread to resume.
- bool run_one_thread;
- nub_thread_t solo_thread = INVALID_NUB_THREAD;
- if (thread_actions.GetSize() > 0
- && thread_actions.NumActionsWithState(eStateStepping) + thread_actions.NumActionsWithState (eStateRunning) == 1)
- {
- run_one_thread = true;
- const DNBThreadResumeAction *action_ptr = thread_actions.GetFirst();
- size_t num_actions = thread_actions.GetSize();
- for (size_t i = 0; i < num_actions; i++, action_ptr++)
- {
- if (action_ptr->state == eStateStepping || action_ptr->state == eStateRunning)
- {
- solo_thread = action_ptr->tid;
- break;
- }
- }
- }
+uint32_t
+MachThreadList::UpdateThreadList(MachProcess *process, bool update,
+ MachThreadList::collection *new_threads) {
+ // locker will keep a mutex locked until it goes out of scope
+ DNBLogThreadedIf(LOG_THREAD, "MachThreadList::UpdateThreadList (pid = %4.4x, "
+ "update = %u) process stop count = %u",
+ process->ProcessID(), update, process->StopCount());
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+
+ if (process->StopCount() == 0) {
+ int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PID, process->ProcessID()};
+ struct kinfo_proc processInfo;
+ size_t bufsize = sizeof(processInfo);
+ if (sysctl(mib, (unsigned)(sizeof(mib) / sizeof(int)), &processInfo,
+ &bufsize, NULL, 0) == 0 &&
+ bufsize > 0) {
+ if (processInfo.kp_proc.p_flag & P_LP64)
+ m_is_64_bit = true;
+ }
+#if defined(__i386__) || defined(__x86_64__)
+ if (m_is_64_bit)
+ DNBArchProtocol::SetArchitecture(CPU_TYPE_X86_64);
else
- run_one_thread = false;
-
- UpdateThreadList(process, true, &new_threads);
-
- DNBThreadResumeAction resume_new_threads = { -1U, eStateRunning, 0, INVALID_NUB_ADDRESS };
- // If we are planning to run only one thread, any new threads should be suspended.
- if (run_one_thread)
- resume_new_threads.state = eStateSuspended;
+ DNBArchProtocol::SetArchitecture(CPU_TYPE_I386);
+#elif defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
+ if (m_is_64_bit)
+ DNBArchProtocol::SetArchitecture(CPU_TYPE_ARM64);
+ else
+ DNBArchProtocol::SetArchitecture(CPU_TYPE_ARM);
+#endif
+ }
- const size_t num_new_threads = new_threads.size();
+ if (m_threads.empty() || update) {
+ thread_array_t thread_list = NULL;
+ mach_msg_type_number_t thread_list_count = 0;
+ task_t task = process->Task().TaskPort();
+ DNBError err(::task_threads(task, &thread_list, &thread_list_count),
+ DNBError::MachKernel);
+
+ if (DNBLogCheckLogBit(LOG_THREAD) || err.Fail())
+ err.LogThreaded("::task_threads ( task = 0x%4.4x, thread_list => %p, "
+ "thread_list_count => %u )",
+ task, thread_list, thread_list_count);
+
+ if (err.Error() == KERN_SUCCESS && thread_list_count > 0) {
+ MachThreadList::collection currThreads;
+ size_t idx;
+ // Iterator through the current thread list and see which threads
+ // we already have in our list (keep them), which ones we don't
+ // (add them), and which ones are not around anymore (remove them).
+ for (idx = 0; idx < thread_list_count; ++idx) {
+ const thread_t mach_port_num = thread_list[idx];
+
+ uint64_t unique_thread_id =
+ MachThread::GetGloballyUniqueThreadIDForMachPortID(mach_port_num);
+ MachThreadSP thread_sp(GetThreadByID(unique_thread_id));
+ if (thread_sp) {
+ // Keep the existing thread class
+ currThreads.push_back(thread_sp);
+ } else {
+ // We don't have this thread, lets add it.
+ thread_sp.reset(new MachThread(process, m_is_64_bit, unique_thread_id,
+ mach_port_num));
+
+ // Add the new thread regardless of its is user ready state...
+ // Make sure the thread is ready to be displayed and shown to users
+ // before we add this thread to our list...
+ if (thread_sp->IsUserReady()) {
+ if (new_threads)
+ new_threads->push_back(thread_sp);
+
+ currThreads.push_back(thread_sp);
+ }
+ }
+ }
+
+ m_threads.swap(currThreads);
+ m_current_thread.reset();
+
+ // Free the vm memory given to us by ::task_threads()
+ vm_size_t thread_list_size =
+ (vm_size_t)(thread_list_count * sizeof(thread_t));
+ ::vm_deallocate(::mach_task_self(), (vm_address_t)thread_list,
+ thread_list_size);
+ }
+ }
+ return static_cast<uint32_t>(m_threads.size());
+}
+
+void MachThreadList::CurrentThread(MachThreadSP &thread_sp) {
+ // locker will keep a mutex locked until it goes out of scope
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ if (m_current_thread.get() == NULL) {
+ // Figure out which thread is going to be our current thread.
+ // This is currently done by finding the first thread in the list
+ // that has a valid exception.
const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- MachThread *thread = m_threads[idx].get();
- bool handled = false;
- for (uint32_t new_idx = 0; new_idx < num_new_threads; ++new_idx)
- {
- if (thread == new_threads[new_idx].get())
- {
- thread->ThreadWillResume(&resume_new_threads);
- handled = true;
- break;
- }
- }
-
- if (!handled)
- {
- const DNBThreadResumeAction *thread_action = thread_actions.GetActionForThread (thread->ThreadID(), true);
- // There must always be a thread action for every thread.
- assert (thread_action);
- bool others_stopped = false;
- if (solo_thread == thread->ThreadID())
- others_stopped = true;
- thread->ThreadWillResume (thread_action, others_stopped);
- }
- }
-
- if (new_threads.size())
- {
- for (uint32_t idx = 0; idx < num_new_threads; ++idx)
- {
- DNBLogThreadedIf (LOG_THREAD, "MachThreadList::ProcessWillResume (pid = %4.4x) stop-id=%u, resuming newly discovered thread: 0x%8.8" PRIx64 ", thread-is-user-ready=%i)",
- process->ProcessID(),
- process->StopCount(),
- new_threads[idx]->ThreadID(),
- new_threads[idx]->IsUserReady());
- }
- }
-}
-
-uint32_t
-MachThreadList::ProcessDidStop(MachProcess *process)
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- // Update our thread list
- const uint32_t num_threads = UpdateThreadList(process, true);
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- m_threads[idx]->ThreadDidStop();
- }
- return num_threads;
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ if (m_threads[idx]->GetStopException().IsValid()) {
+ m_current_thread = m_threads[idx];
+ break;
+ }
+ }
+ }
+ thread_sp = m_current_thread;
+}
+
+void MachThreadList::Dump() const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ const size_t num_threads = m_threads.size();
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ m_threads[idx]->Dump(idx);
+ }
+}
+
+void MachThreadList::ProcessWillResume(
+ MachProcess *process, const DNBThreadResumeActions &thread_actions) {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+
+ // Update our thread list, because sometimes libdispatch or the kernel
+ // will spawn threads while a task is suspended.
+ MachThreadList::collection new_threads;
+
+ // First figure out if we were planning on running only one thread, and if so
+ // force that thread to resume.
+ bool run_one_thread;
+ nub_thread_t solo_thread = INVALID_NUB_THREAD;
+ if (thread_actions.GetSize() > 0 &&
+ thread_actions.NumActionsWithState(eStateStepping) +
+ thread_actions.NumActionsWithState(eStateRunning) ==
+ 1) {
+ run_one_thread = true;
+ const DNBThreadResumeAction *action_ptr = thread_actions.GetFirst();
+ size_t num_actions = thread_actions.GetSize();
+ for (size_t i = 0; i < num_actions; i++, action_ptr++) {
+ if (action_ptr->state == eStateStepping ||
+ action_ptr->state == eStateRunning) {
+ solo_thread = action_ptr->tid;
+ break;
+ }
+ }
+ } else
+ run_one_thread = false;
+
+ UpdateThreadList(process, true, &new_threads);
+
+ DNBThreadResumeAction resume_new_threads = {-1U, eStateRunning, 0,
+ INVALID_NUB_ADDRESS};
+ // If we are planning to run only one thread, any new threads should be
+ // suspended.
+ if (run_one_thread)
+ resume_new_threads.state = eStateSuspended;
+
+ const size_t num_new_threads = new_threads.size();
+ const size_t num_threads = m_threads.size();
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ MachThread *thread = m_threads[idx].get();
+ bool handled = false;
+ for (uint32_t new_idx = 0; new_idx < num_new_threads; ++new_idx) {
+ if (thread == new_threads[new_idx].get()) {
+ thread->ThreadWillResume(&resume_new_threads);
+ handled = true;
+ break;
+ }
+ }
+
+ if (!handled) {
+ const DNBThreadResumeAction *thread_action =
+ thread_actions.GetActionForThread(thread->ThreadID(), true);
+ // There must always be a thread action for every thread.
+ assert(thread_action);
+ bool others_stopped = false;
+ if (solo_thread == thread->ThreadID())
+ others_stopped = true;
+ thread->ThreadWillResume(thread_action, others_stopped);
+ }
+ }
+
+ if (new_threads.size()) {
+ for (uint32_t idx = 0; idx < num_new_threads; ++idx) {
+ DNBLogThreadedIf(
+ LOG_THREAD, "MachThreadList::ProcessWillResume (pid = %4.4x) "
+ "stop-id=%u, resuming newly discovered thread: "
+ "0x%8.8" PRIx64 ", thread-is-user-ready=%i)",
+ process->ProcessID(), process->StopCount(),
+ new_threads[idx]->ThreadID(), new_threads[idx]->IsUserReady());
+ }
+ }
+}
+
+uint32_t MachThreadList::ProcessDidStop(MachProcess *process) {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ // Update our thread list
+ const uint32_t num_threads = UpdateThreadList(process, true);
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ m_threads[idx]->ThreadDidStop();
+ }
+ return num_threads;
}
//----------------------------------------------------------------------
@@ -528,141 +461,122 @@ MachThreadList::ProcessDidStop(MachProce
// true if we should stop and notify our clients
// false if we should resume our child process and skip notification
//----------------------------------------------------------------------
-bool
-MachThreadList::ShouldStop(bool &step_more)
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- uint32_t should_stop = false;
- const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; !should_stop && idx < num_threads; ++idx)
- {
- should_stop = m_threads[idx]->ShouldStop(step_more);
- }
- return should_stop;
+bool MachThreadList::ShouldStop(bool &step_more) {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ uint32_t should_stop = false;
+ const size_t num_threads = m_threads.size();
+ for (uint32_t idx = 0; !should_stop && idx < num_threads; ++idx) {
+ should_stop = m_threads[idx]->ShouldStop(step_more);
+ }
+ return should_stop;
+}
+
+void MachThreadList::NotifyBreakpointChanged(const DNBBreakpoint *bp) {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ const size_t num_threads = m_threads.size();
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ m_threads[idx]->NotifyBreakpointChanged(bp);
+ }
}
-
-void
-MachThreadList::NotifyBreakpointChanged (const DNBBreakpoint *bp)
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
+uint32_t
+MachThreadList::EnableHardwareBreakpoint(const DNBBreakpoint *bp) const {
+ if (bp != NULL) {
const size_t num_threads = m_threads.size();
for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- m_threads[idx]->NotifyBreakpointChanged(bp);
- }
+ m_threads[idx]->EnableHardwareBreakpoint(bp);
+ }
+ return INVALID_NUB_HW_INDEX;
}
-
-uint32_t
-MachThreadList::EnableHardwareBreakpoint (const DNBBreakpoint* bp) const
-{
- if (bp != NULL)
- {
- const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- m_threads[idx]->EnableHardwareBreakpoint(bp);
- }
- return INVALID_NUB_HW_INDEX;
-}
-
-bool
-MachThreadList::DisableHardwareBreakpoint (const DNBBreakpoint* bp) const
-{
- if (bp != NULL)
- {
- const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- m_threads[idx]->DisableHardwareBreakpoint(bp);
- }
- return false;
+bool MachThreadList::DisableHardwareBreakpoint(const DNBBreakpoint *bp) const {
+ if (bp != NULL) {
+ const size_t num_threads = m_threads.size();
+ for (uint32_t idx = 0; idx < num_threads; ++idx)
+ m_threads[idx]->DisableHardwareBreakpoint(bp);
+ }
+ return false;
}
-// DNBWatchpointSet() -> MachProcess::CreateWatchpoint() -> MachProcess::EnableWatchpoint()
+// DNBWatchpointSet() -> MachProcess::CreateWatchpoint() ->
+// MachProcess::EnableWatchpoint()
// -> MachThreadList::EnableHardwareWatchpoint().
uint32_t
-MachThreadList::EnableHardwareWatchpoint (const DNBBreakpoint* wp) const
-{
- uint32_t hw_index = INVALID_NUB_HW_INDEX;
- if (wp != NULL)
- {
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- const size_t num_threads = m_threads.size();
- // On Mac OS X we have to prime the control registers for new threads. We do this
- // using the control register data for the first thread, for lack of a better way of choosing.
- bool also_set_on_task = true;
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- if ((hw_index = m_threads[idx]->EnableHardwareWatchpoint(wp, also_set_on_task)) == INVALID_NUB_HW_INDEX)
- {
- // We know that idx failed for some reason. Let's rollback the transaction for [0, idx).
- for (uint32_t i = 0; i < idx; ++i)
- m_threads[i]->RollbackTransForHWP();
- return INVALID_NUB_HW_INDEX;
- }
- also_set_on_task = false;
- }
- // Notify each thread to commit the pending transaction.
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- m_threads[idx]->FinishTransForHWP();
-
- }
- return hw_index;
-}
-
-bool
-MachThreadList::DisableHardwareWatchpoint (const DNBBreakpoint* wp) const
-{
- if (wp != NULL)
- {
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- const size_t num_threads = m_threads.size();
-
- // On Mac OS X we have to prime the control registers for new threads. We do this
- // using the control register data for the first thread, for lack of a better way of choosing.
- bool also_set_on_task = true;
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- {
- if (!m_threads[idx]->DisableHardwareWatchpoint(wp, also_set_on_task))
- {
- // We know that idx failed for some reason. Let's rollback the transaction for [0, idx).
- for (uint32_t i = 0; i < idx; ++i)
- m_threads[i]->RollbackTransForHWP();
- return false;
- }
- also_set_on_task = false;
- }
- // Notify each thread to commit the pending transaction.
- for (uint32_t idx = 0; idx < num_threads; ++idx)
- m_threads[idx]->FinishTransForHWP();
-
- return true;
+MachThreadList::EnableHardwareWatchpoint(const DNBBreakpoint *wp) const {
+ uint32_t hw_index = INVALID_NUB_HW_INDEX;
+ if (wp != NULL) {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ const size_t num_threads = m_threads.size();
+ // On Mac OS X we have to prime the control registers for new threads. We
+ // do this
+ // using the control register data for the first thread, for lack of a
+ // better way of choosing.
+ bool also_set_on_task = true;
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ if ((hw_index = m_threads[idx]->EnableHardwareWatchpoint(
+ wp, also_set_on_task)) == INVALID_NUB_HW_INDEX) {
+ // We know that idx failed for some reason. Let's rollback the
+ // transaction for [0, idx).
+ for (uint32_t i = 0; i < idx; ++i)
+ m_threads[i]->RollbackTransForHWP();
+ return INVALID_NUB_HW_INDEX;
+ }
+ also_set_on_task = false;
}
- return false;
+ // Notify each thread to commit the pending transaction.
+ for (uint32_t idx = 0; idx < num_threads; ++idx)
+ m_threads[idx]->FinishTransForHWP();
+ }
+ return hw_index;
}
-uint32_t
-MachThreadList::NumSupportedHardwareWatchpoints () const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
+bool MachThreadList::DisableHardwareWatchpoint(const DNBBreakpoint *wp) const {
+ if (wp != NULL) {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
const size_t num_threads = m_threads.size();
- // Use an arbitrary thread to retrieve the number of supported hardware watchpoints.
- if (num_threads)
- return m_threads[0]->NumSupportedHardwareWatchpoints();
- return 0;
-}
-uint32_t
-MachThreadList::GetThreadIndexForThreadStoppedWithSignal (const int signo) const
-{
- PTHREAD_MUTEX_LOCKER (locker, m_threads_mutex);
- uint32_t should_stop = false;
- const size_t num_threads = m_threads.size();
- for (uint32_t idx = 0; !should_stop && idx < num_threads; ++idx)
- {
- if (m_threads[idx]->GetStopException().SoftSignal () == signo)
- return idx;
+ // On Mac OS X we have to prime the control registers for new threads. We
+ // do this
+ // using the control register data for the first thread, for lack of a
+ // better way of choosing.
+ bool also_set_on_task = true;
+ for (uint32_t idx = 0; idx < num_threads; ++idx) {
+ if (!m_threads[idx]->DisableHardwareWatchpoint(wp, also_set_on_task)) {
+ // We know that idx failed for some reason. Let's rollback the
+ // transaction for [0, idx).
+ for (uint32_t i = 0; i < idx; ++i)
+ m_threads[i]->RollbackTransForHWP();
+ return false;
+ }
+ also_set_on_task = false;
}
- return UINT32_MAX;
-}
+ // Notify each thread to commit the pending transaction.
+ for (uint32_t idx = 0; idx < num_threads; ++idx)
+ m_threads[idx]->FinishTransForHWP();
+ return true;
+ }
+ return false;
+}
+
+uint32_t MachThreadList::NumSupportedHardwareWatchpoints() const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ const size_t num_threads = m_threads.size();
+ // Use an arbitrary thread to retrieve the number of supported hardware
+ // watchpoints.
+ if (num_threads)
+ return m_threads[0]->NumSupportedHardwareWatchpoints();
+ return 0;
+}
+
+uint32_t MachThreadList::GetThreadIndexForThreadStoppedWithSignal(
+ const int signo) const {
+ PTHREAD_MUTEX_LOCKER(locker, m_threads_mutex);
+ uint32_t should_stop = false;
+ const size_t num_threads = m_threads.size();
+ for (uint32_t idx = 0; !should_stop && idx < num_threads; ++idx) {
+ if (m_threads[idx]->GetStopException().SoftSignal() == signo)
+ return idx;
+ }
+ return UINT32_MAX;
+}
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachThreadList.h Tue Sep 6 15:57:50 2016
@@ -19,69 +19,79 @@
class DNBThreadResumeActions;
-class MachThreadList
-{
+class MachThreadList {
public:
- MachThreadList ();
- ~MachThreadList ();
+ MachThreadList();
+ ~MachThreadList();
- void Clear ();
- void Dump () const;
- bool GetRegisterValue (nub_thread_t tid, uint32_t set, uint32_t reg, DNBRegisterValue *reg_value) const;
- bool SetRegisterValue (nub_thread_t tid, uint32_t set, uint32_t reg, const DNBRegisterValue *reg_value) const;
- nub_size_t GetRegisterContext (nub_thread_t tid, void *buf, size_t buf_len);
- nub_size_t SetRegisterContext (nub_thread_t tid, const void *buf, size_t buf_len);
- uint32_t SaveRegisterState (nub_thread_t tid);
- bool RestoreRegisterState (nub_thread_t tid, uint32_t save_id);
- const char * GetThreadInfo (nub_thread_t tid) const;
- void ProcessWillResume (MachProcess *process, const DNBThreadResumeActions &thread_actions);
- uint32_t ProcessDidStop (MachProcess *process);
- bool NotifyException (MachException::Data& exc);
- bool ShouldStop (bool &step_more);
- const char * GetName (nub_thread_t tid);
- nub_state_t GetState (nub_thread_t tid);
- nub_thread_t SetCurrentThread (nub_thread_t tid);
-
- ThreadInfo::QoS GetRequestedQoS (nub_thread_t tid, nub_addr_t tsd, uint64_t dti_qos_class_index);
- nub_addr_t GetPThreadT (nub_thread_t tid);
- nub_addr_t GetDispatchQueueT (nub_thread_t tid);
- nub_addr_t GetTSDAddressForThread (nub_thread_t tid, uint64_t plo_pthread_tsd_base_address_offset, uint64_t plo_pthread_tsd_base_offset, uint64_t plo_pthread_tsd_entry_size);
-
- bool GetThreadStoppedReason (nub_thread_t tid, struct DNBThreadStopInfo *stop_info) const;
- void DumpThreadStoppedReason (nub_thread_t tid) const;
- bool GetIdentifierInfo (nub_thread_t tid, thread_identifier_info_data_t *ident_info);
- nub_size_t NumThreads () const;
- nub_thread_t ThreadIDAtIndex (nub_size_t idx) const;
- nub_thread_t CurrentThreadID ();
- void CurrentThread (MachThreadSP& threadSP);
- void NotifyBreakpointChanged (const DNBBreakpoint *bp);
- uint32_t EnableHardwareBreakpoint (const DNBBreakpoint *bp) const;
- bool DisableHardwareBreakpoint (const DNBBreakpoint *bp) const;
- uint32_t EnableHardwareWatchpoint (const DNBBreakpoint *wp) const;
- bool DisableHardwareWatchpoint (const DNBBreakpoint *wp) const;
- uint32_t NumSupportedHardwareWatchpoints () const;
-
- uint32_t GetThreadIndexForThreadStoppedWithSignal (const int signo) const;
-
- MachThreadSP GetThreadByID (nub_thread_t tid) const;
-
- MachThreadSP GetThreadByMachPortNumber (thread_t mach_port_number) const;
- nub_thread_t GetThreadIDByMachPortNumber (thread_t mach_port_number) const;
- thread_t GetMachPortNumberByThreadID (nub_thread_t globally_unique_id) const;
+ void Clear();
+ void Dump() const;
+ bool GetRegisterValue(nub_thread_t tid, uint32_t set, uint32_t reg,
+ DNBRegisterValue *reg_value) const;
+ bool SetRegisterValue(nub_thread_t tid, uint32_t set, uint32_t reg,
+ const DNBRegisterValue *reg_value) const;
+ nub_size_t GetRegisterContext(nub_thread_t tid, void *buf, size_t buf_len);
+ nub_size_t SetRegisterContext(nub_thread_t tid, const void *buf,
+ size_t buf_len);
+ uint32_t SaveRegisterState(nub_thread_t tid);
+ bool RestoreRegisterState(nub_thread_t tid, uint32_t save_id);
+ const char *GetThreadInfo(nub_thread_t tid) const;
+ void ProcessWillResume(MachProcess *process,
+ const DNBThreadResumeActions &thread_actions);
+ uint32_t ProcessDidStop(MachProcess *process);
+ bool NotifyException(MachException::Data &exc);
+ bool ShouldStop(bool &step_more);
+ const char *GetName(nub_thread_t tid);
+ nub_state_t GetState(nub_thread_t tid);
+ nub_thread_t SetCurrentThread(nub_thread_t tid);
+
+ ThreadInfo::QoS GetRequestedQoS(nub_thread_t tid, nub_addr_t tsd,
+ uint64_t dti_qos_class_index);
+ nub_addr_t GetPThreadT(nub_thread_t tid);
+ nub_addr_t GetDispatchQueueT(nub_thread_t tid);
+ nub_addr_t
+ GetTSDAddressForThread(nub_thread_t tid,
+ uint64_t plo_pthread_tsd_base_address_offset,
+ uint64_t plo_pthread_tsd_base_offset,
+ uint64_t plo_pthread_tsd_entry_size);
+
+ bool GetThreadStoppedReason(nub_thread_t tid,
+ struct DNBThreadStopInfo *stop_info) const;
+ void DumpThreadStoppedReason(nub_thread_t tid) const;
+ bool GetIdentifierInfo(nub_thread_t tid,
+ thread_identifier_info_data_t *ident_info);
+ nub_size_t NumThreads() const;
+ nub_thread_t ThreadIDAtIndex(nub_size_t idx) const;
+ nub_thread_t CurrentThreadID();
+ void CurrentThread(MachThreadSP &threadSP);
+ void NotifyBreakpointChanged(const DNBBreakpoint *bp);
+ uint32_t EnableHardwareBreakpoint(const DNBBreakpoint *bp) const;
+ bool DisableHardwareBreakpoint(const DNBBreakpoint *bp) const;
+ uint32_t EnableHardwareWatchpoint(const DNBBreakpoint *wp) const;
+ bool DisableHardwareWatchpoint(const DNBBreakpoint *wp) const;
+ uint32_t NumSupportedHardwareWatchpoints() const;
+
+ uint32_t GetThreadIndexForThreadStoppedWithSignal(const int signo) const;
+
+ MachThreadSP GetThreadByID(nub_thread_t tid) const;
+
+ MachThreadSP GetThreadByMachPortNumber(thread_t mach_port_number) const;
+ nub_thread_t GetThreadIDByMachPortNumber(thread_t mach_port_number) const;
+ thread_t GetMachPortNumberByThreadID(nub_thread_t globally_unique_id) const;
protected:
- typedef std::vector<MachThreadSP> collection;
- typedef collection::iterator iterator;
- typedef collection::const_iterator const_iterator;
-
- uint32_t UpdateThreadList (MachProcess *process, bool update, collection *num_threads = NULL);
-// const_iterator FindThreadByID (thread_t tid) const;
-
- collection m_threads;
- mutable PThreadMutex m_threads_mutex;
- MachThreadSP m_current_thread;
- bool m_is_64_bit;
+ typedef std::vector<MachThreadSP> collection;
+ typedef collection::iterator iterator;
+ typedef collection::const_iterator const_iterator;
+
+ uint32_t UpdateThreadList(MachProcess *process, bool update,
+ collection *num_threads = NULL);
+ // const_iterator FindThreadByID (thread_t tid) const;
+
+ collection m_threads;
+ mutable PThreadMutex m_threads_mutex;
+ MachThreadSP m_current_thread;
+ bool m_is_64_bit;
};
#endif // #ifndef __MachThreadList_h__
-
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.cpp Tue Sep 6 15:57:50 2016
@@ -12,587 +12,559 @@
//===----------------------------------------------------------------------===//
#include "MachVMMemory.h"
-#include "MachVMRegion.h"
#include "DNBLog.h"
+#include "MachVMRegion.h"
+#include <dlfcn.h>
#include <mach/mach_vm.h>
#include <mach/shared_region.h>
#include <sys/sysctl.h>
-#include <dlfcn.h>
static const vm_size_t kInvalidPageSize = ~0;
-MachVMMemory::MachVMMemory() :
- m_page_size (kInvalidPageSize),
- m_err (0)
-{
-}
+MachVMMemory::MachVMMemory() : m_page_size(kInvalidPageSize), m_err(0) {}
-MachVMMemory::~MachVMMemory()
-{
-}
+MachVMMemory::~MachVMMemory() {}
-nub_size_t
-MachVMMemory::PageSize(task_t task)
-{
- if (m_page_size == kInvalidPageSize)
- {
-#if defined (TASK_VM_INFO) && TASK_VM_INFO >= 22
- if (task != TASK_NULL)
- {
- kern_return_t kr;
- mach_msg_type_number_t info_count = TASK_VM_INFO_COUNT;
- task_vm_info_data_t vm_info;
- kr = task_info (task, TASK_VM_INFO, (task_info_t) &vm_info, &info_count);
- if (kr == KERN_SUCCESS)
- {
- DNBLogThreadedIf(LOG_TASK, "MachVMMemory::PageSize task_info returned page size of 0x%x", (int) vm_info.page_size);
- m_page_size = vm_info.page_size;
- return m_page_size;
- }
- else
- {
- DNBLogThreadedIf(LOG_TASK, "MachVMMemory::PageSize task_info call failed to get page size, TASK_VM_INFO %d, TASK_VM_INFO_COUNT %d, kern return %d", TASK_VM_INFO, TASK_VM_INFO_COUNT, kr);
- }
- }
-#endif
- m_err = ::host_page_size( ::mach_host_self(), &m_page_size);
- if (m_err.Fail())
- m_page_size = 0;
+nub_size_t MachVMMemory::PageSize(task_t task) {
+ if (m_page_size == kInvalidPageSize) {
+#if defined(TASK_VM_INFO) && TASK_VM_INFO >= 22
+ if (task != TASK_NULL) {
+ kern_return_t kr;
+ mach_msg_type_number_t info_count = TASK_VM_INFO_COUNT;
+ task_vm_info_data_t vm_info;
+ kr = task_info(task, TASK_VM_INFO, (task_info_t)&vm_info, &info_count);
+ if (kr == KERN_SUCCESS) {
+ DNBLogThreadedIf(
+ LOG_TASK,
+ "MachVMMemory::PageSize task_info returned page size of 0x%x",
+ (int)vm_info.page_size);
+ m_page_size = vm_info.page_size;
+ return m_page_size;
+ } else {
+ DNBLogThreadedIf(LOG_TASK, "MachVMMemory::PageSize task_info call "
+ "failed to get page size, TASK_VM_INFO %d, "
+ "TASK_VM_INFO_COUNT %d, kern return %d",
+ TASK_VM_INFO, TASK_VM_INFO_COUNT, kr);
+ }
}
- return m_page_size;
-}
+#endif
+ m_err = ::host_page_size(::mach_host_self(), &m_page_size);
+ if (m_err.Fail())
+ m_page_size = 0;
+ }
+ return m_page_size;
+}
+
+nub_size_t MachVMMemory::MaxBytesLeftInPage(task_t task, nub_addr_t addr,
+ nub_size_t count) {
+ const nub_size_t page_size = PageSize(task);
+ if (page_size > 0) {
+ nub_size_t page_offset = (addr % page_size);
+ nub_size_t bytes_left_in_page = page_size - page_offset;
+ if (count > bytes_left_in_page)
+ count = bytes_left_in_page;
+ }
+ return count;
+}
+
+nub_bool_t MachVMMemory::GetMemoryRegionInfo(task_t task, nub_addr_t address,
+ DNBRegionInfo *region_info) {
+ MachVMRegion vmRegion(task);
+
+ if (vmRegion.GetRegionForAddress(address)) {
+ region_info->addr = vmRegion.StartAddress();
+ region_info->size = vmRegion.GetByteSize();
+ region_info->permissions = vmRegion.GetDNBPermissions();
+ } else {
+ region_info->addr = address;
+ region_info->size = 0;
+ if (vmRegion.GetError().Success()) {
+ // vmRegion.GetRegionForAddress() return false, indicating that "address"
+ // wasn't in a valid region, but the "vmRegion" info was successfully
+ // read from the task which means the info describes the next valid
+ // region from which we can infer the size of this invalid region
+ mach_vm_address_t start_addr = vmRegion.StartAddress();
+ if (address < start_addr)
+ region_info->size = start_addr - address;
+ }
+ // If we can't get any info about the size from the next region it means
+ // we asked about an address that was past all mappings, so the size
+ // of this region will take up all remaining address space.
+ if (region_info->size == 0)
+ region_info->size = INVALID_NUB_ADDRESS - region_info->addr;
+
+ // Not readable, writeable or executable
+ region_info->permissions = 0;
+ }
+ return true;
+}
+
+// For integrated graphics chip, this makes the accounting info for 'wired'
+// memory more like top.
+uint64_t MachVMMemory::GetStolenPages(task_t task) {
+ static uint64_t stolenPages = 0;
+ static bool calculated = false;
+ if (calculated)
+ return stolenPages;
-nub_size_t
-MachVMMemory::MaxBytesLeftInPage(task_t task, nub_addr_t addr, nub_size_t count)
-{
- const nub_size_t page_size = PageSize(task);
- if (page_size > 0)
- {
- nub_size_t page_offset = (addr % page_size);
- nub_size_t bytes_left_in_page = page_size - page_offset;
- if (count > bytes_left_in_page)
- count = bytes_left_in_page;
- }
- return count;
-}
+ static int mib_reserved[CTL_MAXNAME];
+ static int mib_unusable[CTL_MAXNAME];
+ static int mib_other[CTL_MAXNAME];
+ static size_t mib_reserved_len = 0;
+ static size_t mib_unusable_len = 0;
+ static size_t mib_other_len = 0;
+ int r;
-nub_bool_t
-MachVMMemory::GetMemoryRegionInfo(task_t task, nub_addr_t address, DNBRegionInfo *region_info)
-{
- MachVMRegion vmRegion(task);
+ /* This can be used for testing: */
+ // tsamp->pages_stolen = (256 * 1024 * 1024ULL) / tsamp->pagesize;
- if (vmRegion.GetRegionForAddress(address))
- {
- region_info->addr = vmRegion.StartAddress();
- region_info->size = vmRegion.GetByteSize();
- region_info->permissions = vmRegion.GetDNBPermissions();
- }
- else
- {
- region_info->addr = address;
- region_info->size = 0;
- if (vmRegion.GetError().Success())
- {
- // vmRegion.GetRegionForAddress() return false, indicating that "address"
- // wasn't in a valid region, but the "vmRegion" info was successfully
- // read from the task which means the info describes the next valid
- // region from which we can infer the size of this invalid region
- mach_vm_address_t start_addr = vmRegion.StartAddress();
- if (address < start_addr)
- region_info->size = start_addr - address;
- }
- // If we can't get any info about the size from the next region it means
- // we asked about an address that was past all mappings, so the size
- // of this region will take up all remaining address space.
- if (region_info->size == 0)
- region_info->size = INVALID_NUB_ADDRESS - region_info->addr;
+ if (0 == mib_reserved_len) {
+ mib_reserved_len = CTL_MAXNAME;
- // Not readable, writeable or executable
- region_info->permissions = 0;
+ r = sysctlnametomib("machdep.memmap.Reserved", mib_reserved,
+ &mib_reserved_len);
+
+ if (-1 == r) {
+ mib_reserved_len = 0;
+ return 0;
}
- return true;
-}
-// For integrated graphics chip, this makes the accounting info for 'wired' memory more like top.
-uint64_t
-MachVMMemory::GetStolenPages(task_t task)
-{
- static uint64_t stolenPages = 0;
- static bool calculated = false;
- if (calculated) return stolenPages;
-
- static int mib_reserved[CTL_MAXNAME];
- static int mib_unusable[CTL_MAXNAME];
- static int mib_other[CTL_MAXNAME];
- static size_t mib_reserved_len = 0;
- static size_t mib_unusable_len = 0;
- static size_t mib_other_len = 0;
- int r;
-
- /* This can be used for testing: */
- //tsamp->pages_stolen = (256 * 1024 * 1024ULL) / tsamp->pagesize;
-
- if(0 == mib_reserved_len)
- {
- mib_reserved_len = CTL_MAXNAME;
-
- r = sysctlnametomib("machdep.memmap.Reserved", mib_reserved,
- &mib_reserved_len);
-
- if(-1 == r)
- {
- mib_reserved_len = 0;
- return 0;
- }
-
- mib_unusable_len = CTL_MAXNAME;
-
- r = sysctlnametomib("machdep.memmap.Unusable", mib_unusable,
- &mib_unusable_len);
-
- if(-1 == r)
- {
- mib_reserved_len = 0;
- return 0;
- }
-
-
- mib_other_len = CTL_MAXNAME;
-
- r = sysctlnametomib("machdep.memmap.Other", mib_other,
- &mib_other_len);
-
- if(-1 == r)
- {
- mib_reserved_len = 0;
- return 0;
- }
- }
-
- if(mib_reserved_len > 0 && mib_unusable_len > 0 && mib_other_len > 0)
- {
- uint64_t reserved = 0, unusable = 0, other = 0;
- size_t reserved_len;
- size_t unusable_len;
- size_t other_len;
-
- reserved_len = sizeof(reserved);
- unusable_len = sizeof(unusable);
- other_len = sizeof(other);
-
- /* These are all declared as QUAD/uint64_t sysctls in the kernel. */
-
- if (sysctl (mib_reserved,
- static_cast<u_int>(mib_reserved_len),
- &reserved,
- &reserved_len,
- NULL,
- 0))
- {
- return 0;
- }
-
- if (sysctl (mib_unusable,
- static_cast<u_int>(mib_unusable_len),
- &unusable,
- &unusable_len,
- NULL,
- 0))
- {
- return 0;
- }
-
- if (sysctl (mib_other,
- static_cast<u_int>(mib_other_len),
- &other,
- &other_len,
- NULL,
- 0))
- {
- return 0;
- }
-
- if (reserved_len == sizeof(reserved) &&
- unusable_len == sizeof(unusable) &&
- other_len == sizeof(other))
- {
- uint64_t stolen = reserved + unusable + other;
- uint64_t mb128 = 128 * 1024 * 1024ULL;
-
- if(stolen >= mb128)
- {
- stolen = (stolen & ~((128 * 1024 * 1024ULL) - 1)); // rounding down
- stolenPages = stolen / PageSize (task);
- }
- }
- }
-
- calculated = true;
- return stolenPages;
-}
+ mib_unusable_len = CTL_MAXNAME;
-static uint64_t GetPhysicalMemory()
-{
- // This doesn't change often at all. No need to poll each time.
- static uint64_t physical_memory = 0;
- static bool calculated = false;
- if (calculated) return physical_memory;
-
- size_t len = sizeof(physical_memory);
- sysctlbyname("hw.memsize", &physical_memory, &len, NULL, 0);
-
- calculated = true;
- return physical_memory;
-}
+ r = sysctlnametomib("machdep.memmap.Unusable", mib_unusable,
+ &mib_unusable_len);
-// rsize and dirty_size is not adjusted for dyld shared cache and multiple __LINKEDIT segment, as in vmmap. In practice, dirty_size doesn't differ much but rsize may. There is performance penalty for the adjustment. Right now, only use the dirty_size.
-void
-MachVMMemory::GetRegionSizes(task_t task, mach_vm_size_t &rsize, mach_vm_size_t &dirty_size)
-{
-#if defined (TASK_VM_INFO) && TASK_VM_INFO >= 22
-
- task_vm_info_data_t vm_info;
- mach_msg_type_number_t info_count;
- kern_return_t kr;
-
- info_count = TASK_VM_INFO_COUNT;
- kr = task_info(task, TASK_VM_INFO_PURGEABLE, (task_info_t)&vm_info, &info_count);
- if (kr == KERN_SUCCESS)
- dirty_size = vm_info.internal;
-#endif
-}
+ if (-1 == r) {
+ mib_reserved_len = 0;
+ return 0;
+ }
-// Test whether the virtual address is within the architecture's shared region.
-static bool InSharedRegion(mach_vm_address_t addr, cpu_type_t type)
-{
- mach_vm_address_t base = 0, size = 0;
-
- switch(type) {
-#if defined (CPU_TYPE_ARM64) && defined (SHARED_REGION_BASE_ARM64)
- case CPU_TYPE_ARM64:
- base = SHARED_REGION_BASE_ARM64;
- size = SHARED_REGION_SIZE_ARM64;
- break;
-#endif
+ mib_other_len = CTL_MAXNAME;
- case CPU_TYPE_ARM:
- base = SHARED_REGION_BASE_ARM;
- size = SHARED_REGION_SIZE_ARM;
- break;
-
- case CPU_TYPE_X86_64:
- base = SHARED_REGION_BASE_X86_64;
- size = SHARED_REGION_SIZE_X86_64;
- break;
-
- case CPU_TYPE_I386:
- base = SHARED_REGION_BASE_I386;
- size = SHARED_REGION_SIZE_I386;
- break;
-
- default: {
- // Log error abut unknown CPU type
- break;
- }
+ r = sysctlnametomib("machdep.memmap.Other", mib_other, &mib_other_len);
+
+ if (-1 == r) {
+ mib_reserved_len = 0;
+ return 0;
}
-
-
- return(addr >= base && addr < (base + size));
-}
+ }
-void
-MachVMMemory::GetMemorySizes(task_t task, cpu_type_t cputype, nub_process_t pid, mach_vm_size_t &rprvt, mach_vm_size_t &vprvt)
-{
- // Collecting some other info cheaply but not reporting for now.
- mach_vm_size_t empty = 0;
- mach_vm_size_t fw_private = 0;
-
- mach_vm_size_t aliased = 0;
- bool global_shared_text_data_mapped = false;
- vm_size_t pagesize = PageSize (task);
-
- for (mach_vm_address_t addr=0, size=0; ; addr += size)
- {
- vm_region_top_info_data_t info;
- mach_msg_type_number_t count = VM_REGION_TOP_INFO_COUNT;
- mach_port_t object_name;
-
- kern_return_t kr = mach_vm_region(task, &addr, &size, VM_REGION_TOP_INFO, (vm_region_info_t)&info, &count, &object_name);
- if (kr != KERN_SUCCESS) break;
-
- if (InSharedRegion(addr, cputype))
- {
- // Private Shared
- fw_private += info.private_pages_resident * pagesize;
-
- // Check if this process has the globally shared text and data regions mapped in. If so, set global_shared_text_data_mapped to TRUE and avoid checking again.
- if (global_shared_text_data_mapped == FALSE && info.share_mode == SM_EMPTY) {
- vm_region_basic_info_data_64_t b_info;
- mach_vm_address_t b_addr = addr;
- mach_vm_size_t b_size = size;
- count = VM_REGION_BASIC_INFO_COUNT_64;
-
- kr = mach_vm_region(task, &b_addr, &b_size, VM_REGION_BASIC_INFO, (vm_region_info_t)&b_info, &count, &object_name);
- if (kr != KERN_SUCCESS) break;
-
- if (b_info.reserved) {
- global_shared_text_data_mapped = TRUE;
- }
- }
-
- // Short circuit the loop if this isn't a shared private region, since that's the only region type we care about within the current address range.
- if (info.share_mode != SM_PRIVATE)
- {
- continue;
- }
- }
-
- // Update counters according to the region type.
- if (info.share_mode == SM_COW && info.ref_count == 1)
- {
- // Treat single reference SM_COW as SM_PRIVATE
- info.share_mode = SM_PRIVATE;
- }
-
- switch (info.share_mode)
- {
- case SM_LARGE_PAGE:
- // Treat SM_LARGE_PAGE the same as SM_PRIVATE
- // since they are not shareable and are wired.
- case SM_PRIVATE:
- rprvt += info.private_pages_resident * pagesize;
- rprvt += info.shared_pages_resident * pagesize;
- vprvt += size;
- break;
-
- case SM_EMPTY:
- empty += size;
- break;
-
- case SM_COW:
- case SM_SHARED:
- {
- if (pid == 0)
- {
- // Treat kernel_task specially
- if (info.share_mode == SM_COW)
- {
- rprvt += info.private_pages_resident * pagesize;
- vprvt += size;
- }
- break;
- }
-
- if (info.share_mode == SM_COW)
- {
- rprvt += info.private_pages_resident * pagesize;
- vprvt += info.private_pages_resident * pagesize;
- }
- break;
- }
- default:
- // log that something is really bad.
- break;
- }
+ if (mib_reserved_len > 0 && mib_unusable_len > 0 && mib_other_len > 0) {
+ uint64_t reserved = 0, unusable = 0, other = 0;
+ size_t reserved_len;
+ size_t unusable_len;
+ size_t other_len;
+
+ reserved_len = sizeof(reserved);
+ unusable_len = sizeof(unusable);
+ other_len = sizeof(other);
+
+ /* These are all declared as QUAD/uint64_t sysctls in the kernel. */
+
+ if (sysctl(mib_reserved, static_cast<u_int>(mib_reserved_len), &reserved,
+ &reserved_len, NULL, 0)) {
+ return 0;
}
-
- rprvt += aliased;
-}
-static void
-GetPurgeableAndAnonymous(task_t task, uint64_t &purgeable, uint64_t &anonymous)
-{
-#if defined (TASK_VM_INFO) && TASK_VM_INFO >= 22
+ if (sysctl(mib_unusable, static_cast<u_int>(mib_unusable_len), &unusable,
+ &unusable_len, NULL, 0)) {
+ return 0;
+ }
- kern_return_t kr;
- mach_msg_type_number_t info_count;
- task_vm_info_data_t vm_info;
-
- info_count = TASK_VM_INFO_COUNT;
- kr = task_info(task, TASK_VM_INFO_PURGEABLE, (task_info_t)&vm_info, &info_count);
- if (kr == KERN_SUCCESS)
- {
- purgeable = vm_info.purgeable_volatile_resident;
- anonymous = vm_info.internal + vm_info.compressed - vm_info.purgeable_volatile_pmap;
+ if (sysctl(mib_other, static_cast<u_int>(mib_other_len), &other, &other_len,
+ NULL, 0)) {
+ return 0;
}
-#endif
-}
+ if (reserved_len == sizeof(reserved) && unusable_len == sizeof(unusable) &&
+ other_len == sizeof(other)) {
+ uint64_t stolen = reserved + unusable + other;
+ uint64_t mb128 = 128 * 1024 * 1024ULL;
-#if defined (HOST_VM_INFO64_COUNT)
-nub_bool_t
-MachVMMemory::GetMemoryProfile(DNBProfileDataScanType scanType, task_t task, struct task_basic_info ti, cpu_type_t cputype, nub_process_t pid, vm_statistics64_data_t &vminfo, uint64_t &physical_memory, mach_vm_size_t &rprvt, mach_vm_size_t &rsize, mach_vm_size_t &vprvt, mach_vm_size_t &vsize, mach_vm_size_t &dirty_size, mach_vm_size_t &purgeable, mach_vm_size_t &anonymous)
-#else
-nub_bool_t
-MachVMMemory::GetMemoryProfile(DNBProfileDataScanType scanType, task_t task, struct task_basic_info ti, cpu_type_t cputype, nub_process_t pid, vm_statistics_data_t &vminfo, uint64_t &physical_memory, mach_vm_size_t &rprvt, mach_vm_size_t &rsize, mach_vm_size_t &vprvt, mach_vm_size_t &vsize, mach_vm_size_t &dirty_size, mach_vm_size_t &purgeable, mach_vm_size_t &anonymous)
-#endif
-{
- if (scanType & eProfileHostMemory)
- physical_memory = GetPhysicalMemory();
-
- if (scanType & eProfileMemory)
- {
- static mach_port_t localHost = mach_host_self();
-#if defined (HOST_VM_INFO64_COUNT)
- mach_msg_type_number_t count = HOST_VM_INFO64_COUNT;
- host_statistics64(localHost, HOST_VM_INFO64, (host_info64_t)&vminfo, &count);
-#else
- mach_msg_type_number_t count = HOST_VM_INFO_COUNT;
- host_statistics(localHost, HOST_VM_INFO, (host_info_t)&vminfo, &count);
- vminfo.wire_count += GetStolenPages(task);
-#endif
-
- /* We are no longer reporting these. Let's not waste time.
- GetMemorySizes(task, cputype, pid, rprvt, vprvt);
- rsize = ti.resident_size;
- vsize = ti.virtual_size;
-
- if (scanType & eProfileMemoryDirtyPage)
- {
- // This uses vmmap strategy. We don't use the returned rsize for now. We prefer to match top's version since that's what we do for the rest of the metrics.
- GetRegionSizes(task, rsize, dirty_size);
- }
- */
-
- if (scanType & eProfileMemoryAnonymous)
- {
- GetPurgeableAndAnonymous(task, purgeable, anonymous);
- }
+ if (stolen >= mb128) {
+ stolen = (stolen & ~((128 * 1024 * 1024ULL) - 1)); // rounding down
+ stolenPages = stolen / PageSize(task);
+ }
}
-
- return true;
+ }
+
+ calculated = true;
+ return stolenPages;
}
-nub_size_t
-MachVMMemory::Read(task_t task, nub_addr_t address, void *data, nub_size_t data_count)
-{
- if (data == NULL || data_count == 0)
- return 0;
+static uint64_t GetPhysicalMemory() {
+ // This doesn't change often at all. No need to poll each time.
+ static uint64_t physical_memory = 0;
+ static bool calculated = false;
+ if (calculated)
+ return physical_memory;
- nub_size_t total_bytes_read = 0;
- nub_addr_t curr_addr = address;
- uint8_t *curr_data = (uint8_t*)data;
- while (total_bytes_read < data_count)
- {
- mach_vm_size_t curr_size = MaxBytesLeftInPage(task, curr_addr, data_count - total_bytes_read);
- mach_msg_type_number_t curr_bytes_read = 0;
- vm_offset_t vm_memory = 0;
- m_err = ::mach_vm_read (task, curr_addr, curr_size, &vm_memory, &curr_bytes_read);
-
- if (DNBLogCheckLogBit(LOG_MEMORY))
- m_err.LogThreaded("::mach_vm_read ( task = 0x%4.4x, addr = 0x%8.8llx, size = %llu, data => %8.8p, dataCnt => %i )", task, (uint64_t)curr_addr, (uint64_t)curr_size, vm_memory, curr_bytes_read);
+ size_t len = sizeof(physical_memory);
+ sysctlbyname("hw.memsize", &physical_memory, &len, NULL, 0);
- if (m_err.Success())
- {
- if (curr_bytes_read != curr_size)
- {
- if (DNBLogCheckLogBit(LOG_MEMORY))
- m_err.LogThreaded("::mach_vm_read ( task = 0x%4.4x, addr = 0x%8.8llx, size = %llu, data => %8.8p, dataCnt=>%i ) only read %u of %llu bytes", task, (uint64_t)curr_addr, (uint64_t)curr_size, vm_memory, curr_bytes_read, curr_bytes_read, (uint64_t)curr_size);
- }
- ::memcpy (curr_data, (void *)vm_memory, curr_bytes_read);
- ::vm_deallocate (mach_task_self (), vm_memory, curr_bytes_read);
- total_bytes_read += curr_bytes_read;
- curr_addr += curr_bytes_read;
- curr_data += curr_bytes_read;
- }
- else
- {
- break;
- }
- }
- return total_bytes_read;
+ calculated = true;
+ return physical_memory;
}
+// rsize and dirty_size is not adjusted for dyld shared cache and multiple
+// __LINKEDIT segment, as in vmmap. In practice, dirty_size doesn't differ much
+// but rsize may. There is performance penalty for the adjustment. Right now,
+// only use the dirty_size.
+void MachVMMemory::GetRegionSizes(task_t task, mach_vm_size_t &rsize,
+ mach_vm_size_t &dirty_size) {
+#if defined(TASK_VM_INFO) && TASK_VM_INFO >= 22
+
+ task_vm_info_data_t vm_info;
+ mach_msg_type_number_t info_count;
+ kern_return_t kr;
+
+ info_count = TASK_VM_INFO_COUNT;
+ kr = task_info(task, TASK_VM_INFO_PURGEABLE, (task_info_t)&vm_info,
+ &info_count);
+ if (kr == KERN_SUCCESS)
+ dirty_size = vm_info.internal;
+#endif
+}
-nub_size_t
-MachVMMemory::Write(task_t task, nub_addr_t address, const void *data, nub_size_t data_count)
-{
- MachVMRegion vmRegion(task);
-
- nub_size_t total_bytes_written = 0;
- nub_addr_t curr_addr = address;
- const uint8_t *curr_data = (const uint8_t*)data;
+// Test whether the virtual address is within the architecture's shared region.
+static bool InSharedRegion(mach_vm_address_t addr, cpu_type_t type) {
+ mach_vm_address_t base = 0, size = 0;
+ switch (type) {
+#if defined(CPU_TYPE_ARM64) && defined(SHARED_REGION_BASE_ARM64)
+ case CPU_TYPE_ARM64:
+ base = SHARED_REGION_BASE_ARM64;
+ size = SHARED_REGION_SIZE_ARM64;
+ break;
+#endif
- while (total_bytes_written < data_count)
- {
- if (vmRegion.GetRegionForAddress(curr_addr))
- {
- mach_vm_size_t curr_data_count = data_count - total_bytes_written;
- mach_vm_size_t region_bytes_left = vmRegion.BytesRemaining(curr_addr);
- if (region_bytes_left == 0)
- {
- break;
- }
- if (curr_data_count > region_bytes_left)
- curr_data_count = region_bytes_left;
-
- if (vmRegion.SetProtections(curr_addr, curr_data_count, VM_PROT_READ | VM_PROT_WRITE))
- {
- nub_size_t bytes_written = WriteRegion(task, curr_addr, curr_data, curr_data_count);
- if (bytes_written <= 0)
- {
- // Error should have already be posted by WriteRegion...
- break;
- }
- else
- {
- total_bytes_written += bytes_written;
- curr_addr += bytes_written;
- curr_data += bytes_written;
- }
- }
- else
- {
- DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS, "Failed to set read/write protections on region for address: [0x%8.8llx-0x%8.8llx)", (uint64_t)curr_addr, (uint64_t)(curr_addr + curr_data_count));
- break;
- }
- }
- else
- {
- DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS, "Failed to get region for address: 0x%8.8llx", (uint64_t)address);
- break;
- }
- }
+ case CPU_TYPE_ARM:
+ base = SHARED_REGION_BASE_ARM;
+ size = SHARED_REGION_SIZE_ARM;
+ break;
+
+ case CPU_TYPE_X86_64:
+ base = SHARED_REGION_BASE_X86_64;
+ size = SHARED_REGION_SIZE_X86_64;
+ break;
+
+ case CPU_TYPE_I386:
+ base = SHARED_REGION_BASE_I386;
+ size = SHARED_REGION_SIZE_I386;
+ break;
+
+ default: {
+ // Log error abut unknown CPU type
+ break;
+ }
+ }
+
+ return (addr >= base && addr < (base + size));
+}
+
+void MachVMMemory::GetMemorySizes(task_t task, cpu_type_t cputype,
+ nub_process_t pid, mach_vm_size_t &rprvt,
+ mach_vm_size_t &vprvt) {
+ // Collecting some other info cheaply but not reporting for now.
+ mach_vm_size_t empty = 0;
+ mach_vm_size_t fw_private = 0;
+
+ mach_vm_size_t aliased = 0;
+ bool global_shared_text_data_mapped = false;
+ vm_size_t pagesize = PageSize(task);
+
+ for (mach_vm_address_t addr = 0, size = 0;; addr += size) {
+ vm_region_top_info_data_t info;
+ mach_msg_type_number_t count = VM_REGION_TOP_INFO_COUNT;
+ mach_port_t object_name;
+
+ kern_return_t kr =
+ mach_vm_region(task, &addr, &size, VM_REGION_TOP_INFO,
+ (vm_region_info_t)&info, &count, &object_name);
+ if (kr != KERN_SUCCESS)
+ break;
+
+ if (InSharedRegion(addr, cputype)) {
+ // Private Shared
+ fw_private += info.private_pages_resident * pagesize;
+
+ // Check if this process has the globally shared text and data regions
+ // mapped in. If so, set global_shared_text_data_mapped to TRUE and avoid
+ // checking again.
+ if (global_shared_text_data_mapped == FALSE &&
+ info.share_mode == SM_EMPTY) {
+ vm_region_basic_info_data_64_t b_info;
+ mach_vm_address_t b_addr = addr;
+ mach_vm_size_t b_size = size;
+ count = VM_REGION_BASIC_INFO_COUNT_64;
+
+ kr = mach_vm_region(task, &b_addr, &b_size, VM_REGION_BASIC_INFO,
+ (vm_region_info_t)&b_info, &count, &object_name);
+ if (kr != KERN_SUCCESS)
+ break;
+
+ if (b_info.reserved) {
+ global_shared_text_data_mapped = TRUE;
+ }
+ }
+
+ // Short circuit the loop if this isn't a shared private region, since
+ // that's the only region type we care about within the current address
+ // range.
+ if (info.share_mode != SM_PRIVATE) {
+ continue;
+ }
+ }
+
+ // Update counters according to the region type.
+ if (info.share_mode == SM_COW && info.ref_count == 1) {
+ // Treat single reference SM_COW as SM_PRIVATE
+ info.share_mode = SM_PRIVATE;
+ }
+
+ switch (info.share_mode) {
+ case SM_LARGE_PAGE:
+ // Treat SM_LARGE_PAGE the same as SM_PRIVATE
+ // since they are not shareable and are wired.
+ case SM_PRIVATE:
+ rprvt += info.private_pages_resident * pagesize;
+ rprvt += info.shared_pages_resident * pagesize;
+ vprvt += size;
+ break;
+
+ case SM_EMPTY:
+ empty += size;
+ break;
+
+ case SM_COW:
+ case SM_SHARED: {
+ if (pid == 0) {
+ // Treat kernel_task specially
+ if (info.share_mode == SM_COW) {
+ rprvt += info.private_pages_resident * pagesize;
+ vprvt += size;
+ }
+ break;
+ }
+
+ if (info.share_mode == SM_COW) {
+ rprvt += info.private_pages_resident * pagesize;
+ vprvt += info.private_pages_resident * pagesize;
+ }
+ break;
+ }
+ default:
+ // log that something is really bad.
+ break;
+ }
+ }
+
+ rprvt += aliased;
+}
+
+static void GetPurgeableAndAnonymous(task_t task, uint64_t &purgeable,
+ uint64_t &anonymous) {
+#if defined(TASK_VM_INFO) && TASK_VM_INFO >= 22
+
+ kern_return_t kr;
+ mach_msg_type_number_t info_count;
+ task_vm_info_data_t vm_info;
+
+ info_count = TASK_VM_INFO_COUNT;
+ kr = task_info(task, TASK_VM_INFO_PURGEABLE, (task_info_t)&vm_info,
+ &info_count);
+ if (kr == KERN_SUCCESS) {
+ purgeable = vm_info.purgeable_volatile_resident;
+ anonymous =
+ vm_info.internal + vm_info.compressed - vm_info.purgeable_volatile_pmap;
+ }
- return total_bytes_written;
+#endif
}
-
-nub_size_t
-MachVMMemory::WriteRegion(task_t task, const nub_addr_t address, const void *data, const nub_size_t data_count)
+#if defined(HOST_VM_INFO64_COUNT)
+nub_bool_t MachVMMemory::GetMemoryProfile(
+ DNBProfileDataScanType scanType, task_t task, struct task_basic_info ti,
+ cpu_type_t cputype, nub_process_t pid, vm_statistics64_data_t &vminfo,
+ uint64_t &physical_memory, mach_vm_size_t &rprvt, mach_vm_size_t &rsize,
+ mach_vm_size_t &vprvt, mach_vm_size_t &vsize, mach_vm_size_t &dirty_size,
+ mach_vm_size_t &purgeable, mach_vm_size_t &anonymous)
+#else
+nub_bool_t MachVMMemory::GetMemoryProfile(
+ DNBProfileDataScanType scanType, task_t task, struct task_basic_info ti,
+ cpu_type_t cputype, nub_process_t pid, vm_statistics_data_t &vminfo,
+ uint64_t &physical_memory, mach_vm_size_t &rprvt, mach_vm_size_t &rsize,
+ mach_vm_size_t &vprvt, mach_vm_size_t &vsize, mach_vm_size_t &dirty_size,
+ mach_vm_size_t &purgeable, mach_vm_size_t &anonymous)
+#endif
{
- if (data == NULL || data_count == 0)
- return 0;
+ if (scanType & eProfileHostMemory)
+ physical_memory = GetPhysicalMemory();
- nub_size_t total_bytes_written = 0;
- nub_addr_t curr_addr = address;
- const uint8_t *curr_data = (const uint8_t*)data;
- while (total_bytes_written < data_count)
- {
- mach_msg_type_number_t curr_data_count = static_cast<mach_msg_type_number_t>(MaxBytesLeftInPage(task, curr_addr, data_count - total_bytes_written));
- m_err = ::mach_vm_write (task, curr_addr, (pointer_t) curr_data, curr_data_count);
- if (DNBLogCheckLogBit(LOG_MEMORY) || m_err.Fail())
- m_err.LogThreaded("::mach_vm_write ( task = 0x%4.4x, addr = 0x%8.8llx, data = %8.8p, dataCnt = %u )", task, (uint64_t)curr_addr, curr_data, curr_data_count);
-
-#if !defined (__i386__) && !defined (__x86_64__)
- vm_machine_attribute_val_t mattr_value = MATTR_VAL_CACHE_FLUSH;
-
- m_err = ::vm_machine_attribute (task, curr_addr, curr_data_count, MATTR_CACHE, &mattr_value);
- if (DNBLogCheckLogBit(LOG_MEMORY) || m_err.Fail())
- m_err.LogThreaded("::vm_machine_attribute ( task = 0x%4.4x, addr = 0x%8.8llx, size = %u, attr = MATTR_CACHE, mattr_value => MATTR_VAL_CACHE_FLUSH )", task, (uint64_t)curr_addr, curr_data_count);
+ if (scanType & eProfileMemory) {
+ static mach_port_t localHost = mach_host_self();
+#if defined(HOST_VM_INFO64_COUNT)
+ mach_msg_type_number_t count = HOST_VM_INFO64_COUNT;
+ host_statistics64(localHost, HOST_VM_INFO64, (host_info64_t)&vminfo,
+ &count);
+#else
+ mach_msg_type_number_t count = HOST_VM_INFO_COUNT;
+ host_statistics(localHost, HOST_VM_INFO, (host_info_t)&vminfo, &count);
+ vminfo.wire_count += GetStolenPages(task);
#endif
- if (m_err.Success())
- {
- total_bytes_written += curr_data_count;
- curr_addr += curr_data_count;
- curr_data += curr_data_count;
- }
- else
- {
- break;
- }
+ /* We are no longer reporting these. Let's not waste time.
+ GetMemorySizes(task, cputype, pid, rprvt, vprvt);
+ rsize = ti.resident_size;
+ vsize = ti.virtual_size;
+
+ if (scanType & eProfileMemoryDirtyPage)
+ {
+ // This uses vmmap strategy. We don't use the returned rsize for now. We
+ prefer to match top's version since that's what we do for the rest of the
+ metrics.
+ GetRegionSizes(task, rsize, dirty_size);
+ }
+ */
+
+ if (scanType & eProfileMemoryAnonymous) {
+ GetPurgeableAndAnonymous(task, purgeable, anonymous);
+ }
+ }
+
+ return true;
+}
+
+nub_size_t MachVMMemory::Read(task_t task, nub_addr_t address, void *data,
+ nub_size_t data_count) {
+ if (data == NULL || data_count == 0)
+ return 0;
+
+ nub_size_t total_bytes_read = 0;
+ nub_addr_t curr_addr = address;
+ uint8_t *curr_data = (uint8_t *)data;
+ while (total_bytes_read < data_count) {
+ mach_vm_size_t curr_size =
+ MaxBytesLeftInPage(task, curr_addr, data_count - total_bytes_read);
+ mach_msg_type_number_t curr_bytes_read = 0;
+ vm_offset_t vm_memory = 0;
+ m_err = ::mach_vm_read(task, curr_addr, curr_size, &vm_memory,
+ &curr_bytes_read);
+
+ if (DNBLogCheckLogBit(LOG_MEMORY))
+ m_err.LogThreaded("::mach_vm_read ( task = 0x%4.4x, addr = 0x%8.8llx, "
+ "size = %llu, data => %8.8p, dataCnt => %i )",
+ task, (uint64_t)curr_addr, (uint64_t)curr_size,
+ vm_memory, curr_bytes_read);
+
+ if (m_err.Success()) {
+ if (curr_bytes_read != curr_size) {
+ if (DNBLogCheckLogBit(LOG_MEMORY))
+ m_err.LogThreaded(
+ "::mach_vm_read ( task = 0x%4.4x, addr = 0x%8.8llx, size = %llu, "
+ "data => %8.8p, dataCnt=>%i ) only read %u of %llu bytes",
+ task, (uint64_t)curr_addr, (uint64_t)curr_size, vm_memory,
+ curr_bytes_read, curr_bytes_read, (uint64_t)curr_size);
+ }
+ ::memcpy(curr_data, (void *)vm_memory, curr_bytes_read);
+ ::vm_deallocate(mach_task_self(), vm_memory, curr_bytes_read);
+ total_bytes_read += curr_bytes_read;
+ curr_addr += curr_bytes_read;
+ curr_data += curr_bytes_read;
+ } else {
+ break;
+ }
+ }
+ return total_bytes_read;
+}
+
+nub_size_t MachVMMemory::Write(task_t task, nub_addr_t address,
+ const void *data, nub_size_t data_count) {
+ MachVMRegion vmRegion(task);
+
+ nub_size_t total_bytes_written = 0;
+ nub_addr_t curr_addr = address;
+ const uint8_t *curr_data = (const uint8_t *)data;
+
+ while (total_bytes_written < data_count) {
+ if (vmRegion.GetRegionForAddress(curr_addr)) {
+ mach_vm_size_t curr_data_count = data_count - total_bytes_written;
+ mach_vm_size_t region_bytes_left = vmRegion.BytesRemaining(curr_addr);
+ if (region_bytes_left == 0) {
+ break;
+ }
+ if (curr_data_count > region_bytes_left)
+ curr_data_count = region_bytes_left;
+
+ if (vmRegion.SetProtections(curr_addr, curr_data_count,
+ VM_PROT_READ | VM_PROT_WRITE)) {
+ nub_size_t bytes_written =
+ WriteRegion(task, curr_addr, curr_data, curr_data_count);
+ if (bytes_written <= 0) {
+ // Error should have already be posted by WriteRegion...
+ break;
+ } else {
+ total_bytes_written += bytes_written;
+ curr_addr += bytes_written;
+ curr_data += bytes_written;
+ }
+ } else {
+ DNBLogThreadedIf(
+ LOG_MEMORY_PROTECTIONS, "Failed to set read/write protections on "
+ "region for address: [0x%8.8llx-0x%8.8llx)",
+ (uint64_t)curr_addr, (uint64_t)(curr_addr + curr_data_count));
+ break;
+ }
+ } else {
+ DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS,
+ "Failed to get region for address: 0x%8.8llx",
+ (uint64_t)address);
+ break;
+ }
+ }
+
+ return total_bytes_written;
+}
+
+nub_size_t MachVMMemory::WriteRegion(task_t task, const nub_addr_t address,
+ const void *data,
+ const nub_size_t data_count) {
+ if (data == NULL || data_count == 0)
+ return 0;
+
+ nub_size_t total_bytes_written = 0;
+ nub_addr_t curr_addr = address;
+ const uint8_t *curr_data = (const uint8_t *)data;
+ while (total_bytes_written < data_count) {
+ mach_msg_type_number_t curr_data_count =
+ static_cast<mach_msg_type_number_t>(MaxBytesLeftInPage(
+ task, curr_addr, data_count - total_bytes_written));
+ m_err =
+ ::mach_vm_write(task, curr_addr, (pointer_t)curr_data, curr_data_count);
+ if (DNBLogCheckLogBit(LOG_MEMORY) || m_err.Fail())
+ m_err.LogThreaded("::mach_vm_write ( task = 0x%4.4x, addr = 0x%8.8llx, "
+ "data = %8.8p, dataCnt = %u )",
+ task, (uint64_t)curr_addr, curr_data, curr_data_count);
+
+#if !defined(__i386__) && !defined(__x86_64__)
+ vm_machine_attribute_val_t mattr_value = MATTR_VAL_CACHE_FLUSH;
+
+ m_err = ::vm_machine_attribute(task, curr_addr, curr_data_count,
+ MATTR_CACHE, &mattr_value);
+ if (DNBLogCheckLogBit(LOG_MEMORY) || m_err.Fail())
+ m_err.LogThreaded("::vm_machine_attribute ( task = 0x%4.4x, addr = "
+ "0x%8.8llx, size = %u, attr = MATTR_CACHE, mattr_value "
+ "=> MATTR_VAL_CACHE_FLUSH )",
+ task, (uint64_t)curr_addr, curr_data_count);
+#endif
+
+ if (m_err.Success()) {
+ total_bytes_written += curr_data_count;
+ curr_addr += curr_data_count;
+ curr_data += curr_data_count;
+ } else {
+ break;
}
- return total_bytes_written;
+ }
+ return total_bytes_written;
}
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachVMMemory.h Tue Sep 6 15:57:50 2016
@@ -18,34 +18,51 @@
#include "DNBError.h"
#include <mach/mach.h>
-class MachVMMemory
-{
+class MachVMMemory {
public:
- MachVMMemory();
- ~MachVMMemory();
- nub_size_t Read(task_t task, nub_addr_t address, void *data, nub_size_t data_count);
- nub_size_t Write(task_t task, nub_addr_t address, const void *data, nub_size_t data_count);
- nub_size_t PageSize(task_t task);
- nub_bool_t GetMemoryRegionInfo(task_t task, nub_addr_t address, DNBRegionInfo *region_info);
-#if defined (HOST_VM_INFO64_COUNT)
- nub_bool_t GetMemoryProfile(DNBProfileDataScanType scanType, task_t task, struct task_basic_info ti, cpu_type_t cputype, nub_process_t pid, vm_statistics64_data_t &vminfo, uint64_t &physical_memory, mach_vm_size_t &rprvt, mach_vm_size_t &rsize, mach_vm_size_t &vprvt, mach_vm_size_t &vsize, mach_vm_size_t &dirty_size, mach_vm_size_t &purgeable, mach_vm_size_t &anonymous);
+ MachVMMemory();
+ ~MachVMMemory();
+ nub_size_t Read(task_t task, nub_addr_t address, void *data,
+ nub_size_t data_count);
+ nub_size_t Write(task_t task, nub_addr_t address, const void *data,
+ nub_size_t data_count);
+ nub_size_t PageSize(task_t task);
+ nub_bool_t GetMemoryRegionInfo(task_t task, nub_addr_t address,
+ DNBRegionInfo *region_info);
+#if defined(HOST_VM_INFO64_COUNT)
+ nub_bool_t GetMemoryProfile(DNBProfileDataScanType scanType, task_t task,
+ struct task_basic_info ti, cpu_type_t cputype,
+ nub_process_t pid, vm_statistics64_data_t &vminfo,
+ uint64_t &physical_memory, mach_vm_size_t &rprvt,
+ mach_vm_size_t &rsize, mach_vm_size_t &vprvt,
+ mach_vm_size_t &vsize, mach_vm_size_t &dirty_size,
+ mach_vm_size_t &purgeable,
+ mach_vm_size_t &anonymous);
#else
- nub_bool_t GetMemoryProfile(DNBProfileDataScanType scanType, task_t task, struct task_basic_info ti, cpu_type_t cputype, nub_process_t pid, vm_statistics_data_t &vminfo, uint64_t &physical_memory, mach_vm_size_t &rprvt, mach_vm_size_t &rsize, mach_vm_size_t &vprvt, mach_vm_size_t &vsize, mach_vm_size_t &dirty_size, mach_vm_size_t &purgeable, mach_vm_size_t &anonymous);
+ nub_bool_t GetMemoryProfile(DNBProfileDataScanType scanType, task_t task,
+ struct task_basic_info ti, cpu_type_t cputype,
+ nub_process_t pid, vm_statistics_data_t &vminfo,
+ uint64_t &physical_memory, mach_vm_size_t &rprvt,
+ mach_vm_size_t &rsize, mach_vm_size_t &vprvt,
+ mach_vm_size_t &vsize, mach_vm_size_t &dirty_size,
+ mach_vm_size_t &purgeable,
+ mach_vm_size_t &anonymous);
#endif
protected:
- nub_size_t MaxBytesLeftInPage(task_t task, nub_addr_t addr, nub_size_t count);
+ nub_size_t MaxBytesLeftInPage(task_t task, nub_addr_t addr, nub_size_t count);
- uint64_t GetStolenPages(task_t task);
- void GetRegionSizes(task_t task, mach_vm_size_t &rsize, mach_vm_size_t &dirty_size);
- void GetMemorySizes(task_t task, cpu_type_t cputype, nub_process_t pid, mach_vm_size_t &rprvt, mach_vm_size_t &vprvt);
+ uint64_t GetStolenPages(task_t task);
+ void GetRegionSizes(task_t task, mach_vm_size_t &rsize,
+ mach_vm_size_t &dirty_size);
+ void GetMemorySizes(task_t task, cpu_type_t cputype, nub_process_t pid,
+ mach_vm_size_t &rprvt, mach_vm_size_t &vprvt);
+ nub_size_t WriteRegion(task_t task, const nub_addr_t address,
+ const void *data, const nub_size_t data_count);
- nub_size_t WriteRegion(task_t task, const nub_addr_t address, const void *data, const nub_size_t data_count);
-
- vm_size_t m_page_size;
- DNBError m_err;
+ vm_size_t m_page_size;
+ DNBError m_err;
};
-
#endif // #ifndef __MachVMMemory_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.cpp Tue Sep 6 15:57:50 2016
@@ -12,191 +12,177 @@
//===----------------------------------------------------------------------===//
#include "MachVMRegion.h"
-#include <mach/mach_vm.h>
#include "DNBLog.h"
#include <assert.h>
+#include <mach/mach_vm.h>
-MachVMRegion::MachVMRegion(task_t task) :
- m_task(task),
- m_addr(INVALID_NUB_ADDRESS),
- m_err(),
- m_start(INVALID_NUB_ADDRESS),
- m_size(0),
- m_depth(-1),
- m_curr_protection(0),
- m_protection_addr(INVALID_NUB_ADDRESS),
- m_protection_size(0)
-{
- memset(&m_data, 0, sizeof(m_data));
-}
-
-MachVMRegion::~MachVMRegion()
-{
- // Restore any original protections and clear our vars
- Clear();
-}
-
-void
-MachVMRegion::Clear()
-{
- RestoreProtections();
- m_addr = INVALID_NUB_ADDRESS;
- m_err.Clear();
- m_start = INVALID_NUB_ADDRESS;
- m_size = 0;
- m_depth = -1;
- memset(&m_data, 0, sizeof(m_data));
- m_curr_protection = 0;
- m_protection_addr = INVALID_NUB_ADDRESS;
- m_protection_size = 0;
-}
-
-bool
-MachVMRegion::SetProtections(mach_vm_address_t addr, mach_vm_size_t size, vm_prot_t prot)
-{
- if (ContainsAddress(addr))
- {
- mach_vm_size_t prot_size = size;
- mach_vm_address_t end_addr = EndAddress();
- if (prot_size > (end_addr - addr))
- prot_size = end_addr - addr;
-
- if (prot_size > 0)
- {
- if (prot == (m_curr_protection & VM_PROT_ALL))
- {
- DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS | LOG_VERBOSE, "MachVMRegion::%s: protections (%u) already sufficient for task 0x%4.4x at address 0x%8.8llx) ", __FUNCTION__, prot, m_task, (uint64_t)addr);
- // Protections are already set as requested...
- return true;
- }
- else
- {
- m_err = ::mach_vm_protect (m_task, addr, prot_size, 0, prot);
- if (DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS))
- m_err.LogThreaded("::mach_vm_protect ( task = 0x%4.4x, addr = 0x%8.8llx, size = %llu, set_max = %i, prot = %u )", m_task, (uint64_t)addr, (uint64_t)prot_size, 0, prot);
- if (m_err.Fail())
- {
- // Try again with the ability to create a copy on write region
- m_err = ::mach_vm_protect (m_task, addr, prot_size, 0, prot | VM_PROT_COPY);
- if (DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS) || m_err.Fail())
- m_err.LogThreaded("::mach_vm_protect ( task = 0x%4.4x, addr = 0x%8.8llx, size = %llu, set_max = %i, prot = %u )", m_task, (uint64_t)addr, (uint64_t)prot_size, 0, prot | VM_PROT_COPY);
- }
- if (m_err.Success())
- {
- m_curr_protection = prot;
- m_protection_addr = addr;
- m_protection_size = prot_size;
- return true;
- }
- }
+MachVMRegion::MachVMRegion(task_t task)
+ : m_task(task), m_addr(INVALID_NUB_ADDRESS), m_err(),
+ m_start(INVALID_NUB_ADDRESS), m_size(0), m_depth(-1),
+ m_curr_protection(0), m_protection_addr(INVALID_NUB_ADDRESS),
+ m_protection_size(0) {
+ memset(&m_data, 0, sizeof(m_data));
+}
+
+MachVMRegion::~MachVMRegion() {
+ // Restore any original protections and clear our vars
+ Clear();
+}
+
+void MachVMRegion::Clear() {
+ RestoreProtections();
+ m_addr = INVALID_NUB_ADDRESS;
+ m_err.Clear();
+ m_start = INVALID_NUB_ADDRESS;
+ m_size = 0;
+ m_depth = -1;
+ memset(&m_data, 0, sizeof(m_data));
+ m_curr_protection = 0;
+ m_protection_addr = INVALID_NUB_ADDRESS;
+ m_protection_size = 0;
+}
+
+bool MachVMRegion::SetProtections(mach_vm_address_t addr, mach_vm_size_t size,
+ vm_prot_t prot) {
+ if (ContainsAddress(addr)) {
+ mach_vm_size_t prot_size = size;
+ mach_vm_address_t end_addr = EndAddress();
+ if (prot_size > (end_addr - addr))
+ prot_size = end_addr - addr;
+
+ if (prot_size > 0) {
+ if (prot == (m_curr_protection & VM_PROT_ALL)) {
+ DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS | LOG_VERBOSE,
+ "MachVMRegion::%s: protections (%u) already "
+ "sufficient for task 0x%4.4x at address 0x%8.8llx) ",
+ __FUNCTION__, prot, m_task, (uint64_t)addr);
+ // Protections are already set as requested...
+ return true;
+ } else {
+ m_err = ::mach_vm_protect(m_task, addr, prot_size, 0, prot);
+ if (DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS))
+ m_err.LogThreaded("::mach_vm_protect ( task = 0x%4.4x, addr = "
+ "0x%8.8llx, size = %llu, set_max = %i, prot = %u )",
+ m_task, (uint64_t)addr, (uint64_t)prot_size, 0,
+ prot);
+ if (m_err.Fail()) {
+ // Try again with the ability to create a copy on write region
+ m_err = ::mach_vm_protect(m_task, addr, prot_size, 0,
+ prot | VM_PROT_COPY);
+ if (DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS) || m_err.Fail())
+ m_err.LogThreaded("::mach_vm_protect ( task = 0x%4.4x, addr = "
+ "0x%8.8llx, size = %llu, set_max = %i, prot = %u "
+ ")",
+ m_task, (uint64_t)addr, (uint64_t)prot_size, 0,
+ prot | VM_PROT_COPY);
}
- else
- {
- DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS | LOG_VERBOSE, "%s: Zero size for task 0x%4.4x at address 0x%8.8llx) ", __FUNCTION__, m_task, (uint64_t)addr);
+ if (m_err.Success()) {
+ m_curr_protection = prot;
+ m_protection_addr = addr;
+ m_protection_size = prot_size;
+ return true;
}
+ }
+ } else {
+ DNBLogThreadedIf(LOG_MEMORY_PROTECTIONS | LOG_VERBOSE,
+ "%s: Zero size for task 0x%4.4x at address 0x%8.8llx) ",
+ __FUNCTION__, m_task, (uint64_t)addr);
}
- return false;
+ }
+ return false;
}
-bool
-MachVMRegion::RestoreProtections()
-{
- if (m_curr_protection != m_data.protection && m_protection_size > 0)
- {
- m_err = ::mach_vm_protect (m_task, m_protection_addr, m_protection_size, 0, m_data.protection);
- if (DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS) || m_err.Fail())
- m_err.LogThreaded("::mach_vm_protect ( task = 0x%4.4x, addr = 0x%8.8llx, size = %llu, set_max = %i, prot = %u )", m_task, (uint64_t)m_protection_addr, (uint64_t)m_protection_size, 0, m_data.protection);
- if (m_err.Success())
- {
- m_protection_size = 0;
- m_protection_addr = INVALID_NUB_ADDRESS;
- m_curr_protection = m_data.protection;
- return true;
- }
- }
- else
- {
- m_err.Clear();
- return true;
+bool MachVMRegion::RestoreProtections() {
+ if (m_curr_protection != m_data.protection && m_protection_size > 0) {
+ m_err = ::mach_vm_protect(m_task, m_protection_addr, m_protection_size, 0,
+ m_data.protection);
+ if (DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS) || m_err.Fail())
+ m_err.LogThreaded("::mach_vm_protect ( task = 0x%4.4x, addr = 0x%8.8llx, "
+ "size = %llu, set_max = %i, prot = %u )",
+ m_task, (uint64_t)m_protection_addr,
+ (uint64_t)m_protection_size, 0, m_data.protection);
+ if (m_err.Success()) {
+ m_protection_size = 0;
+ m_protection_addr = INVALID_NUB_ADDRESS;
+ m_curr_protection = m_data.protection;
+ return true;
}
+ } else {
+ m_err.Clear();
+ return true;
+ }
- return false;
+ return false;
}
-bool
-MachVMRegion::GetRegionForAddress(nub_addr_t addr)
-{
- // Restore any original protections and clear our vars
- Clear();
- m_err.Clear();
- m_addr = addr;
- m_start = addr;
- m_depth = 1024;
- mach_msg_type_number_t info_size = kRegionInfoSize;
- assert(sizeof(info_size) == 4);
- m_err = ::mach_vm_region_recurse (m_task, &m_start, &m_size, &m_depth, (vm_region_recurse_info_t)&m_data, &info_size);
-
- const bool failed = m_err.Fail();
- const bool log_protections = DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS);
-
- if (log_protections || failed)
- m_err.LogThreaded("::mach_vm_region_recurse ( task = 0x%4.4x, address => 0x%8.8llx, size => %llu, nesting_depth => %d, info => %p, infoCnt => %d) addr = 0x%8.8llx ", m_task, (uint64_t)m_start, (uint64_t)m_size, m_depth, &m_data, info_size, (uint64_t)addr);
-
- if (failed)
- return false;
- if (log_protections)
- {
- DNBLogThreaded("info = { prot = %u, "
- "max_prot = %u, "
- "inheritance = 0x%8.8x, "
- "offset = 0x%8.8llx, "
- "user_tag = 0x%8.8x, "
- "ref_count = %u, "
- "shadow_depth = %u, "
- "ext_pager = %u, "
- "share_mode = %u, "
- "is_submap = %d, "
- "behavior = %d, "
- "object_id = 0x%8.8x, "
- "user_wired_count = 0x%4.4x }",
- m_data.protection,
- m_data.max_protection,
- m_data.inheritance,
- (uint64_t)m_data.offset,
- m_data.user_tag,
- m_data.ref_count,
- m_data.shadow_depth,
- m_data.external_pager,
- m_data.share_mode,
- m_data.is_submap,
- m_data.behavior,
- m_data.object_id,
- m_data.user_wired_count);
- }
- m_curr_protection = m_data.protection;
-
- // We make a request for an address and got no error back, but this
- // doesn't mean that "addr" is in the range. The data in this object will
- // be valid though, so you could see where the next region begins. So we
- // return false, yet leave "m_err" with a successfull return code.
- if ((addr < m_start) || (addr >= (m_start + m_size)))
- return false;
+bool MachVMRegion::GetRegionForAddress(nub_addr_t addr) {
+ // Restore any original protections and clear our vars
+ Clear();
+ m_err.Clear();
+ m_addr = addr;
+ m_start = addr;
+ m_depth = 1024;
+ mach_msg_type_number_t info_size = kRegionInfoSize;
+ assert(sizeof(info_size) == 4);
+ m_err =
+ ::mach_vm_region_recurse(m_task, &m_start, &m_size, &m_depth,
+ (vm_region_recurse_info_t)&m_data, &info_size);
+
+ const bool failed = m_err.Fail();
+ const bool log_protections = DNBLogCheckLogBit(LOG_MEMORY_PROTECTIONS);
+
+ if (log_protections || failed)
+ m_err.LogThreaded("::mach_vm_region_recurse ( task = 0x%4.4x, address => "
+ "0x%8.8llx, size => %llu, nesting_depth => %d, info => "
+ "%p, infoCnt => %d) addr = 0x%8.8llx ",
+ m_task, (uint64_t)m_start, (uint64_t)m_size, m_depth,
+ &m_data, info_size, (uint64_t)addr);
- return true;
+ if (failed)
+ return false;
+ if (log_protections) {
+ DNBLogThreaded("info = { prot = %u, "
+ "max_prot = %u, "
+ "inheritance = 0x%8.8x, "
+ "offset = 0x%8.8llx, "
+ "user_tag = 0x%8.8x, "
+ "ref_count = %u, "
+ "shadow_depth = %u, "
+ "ext_pager = %u, "
+ "share_mode = %u, "
+ "is_submap = %d, "
+ "behavior = %d, "
+ "object_id = 0x%8.8x, "
+ "user_wired_count = 0x%4.4x }",
+ m_data.protection, m_data.max_protection, m_data.inheritance,
+ (uint64_t)m_data.offset, m_data.user_tag, m_data.ref_count,
+ m_data.shadow_depth, m_data.external_pager,
+ m_data.share_mode, m_data.is_submap, m_data.behavior,
+ m_data.object_id, m_data.user_wired_count);
+ }
+ m_curr_protection = m_data.protection;
+
+ // We make a request for an address and got no error back, but this
+ // doesn't mean that "addr" is in the range. The data in this object will
+ // be valid though, so you could see where the next region begins. So we
+ // return false, yet leave "m_err" with a successfull return code.
+ if ((addr < m_start) || (addr >= (m_start + m_size)))
+ return false;
+
+ return true;
}
-uint32_t
-MachVMRegion::GetDNBPermissions () const
-{
- if (m_addr == INVALID_NUB_ADDRESS || m_start == INVALID_NUB_ADDRESS || m_size == 0)
- return 0;
- uint32_t dnb_permissions = 0;
-
- if ((m_data.protection & VM_PROT_READ) == VM_PROT_READ)
- dnb_permissions |= eMemoryPermissionsReadable;
- if ((m_data.protection & VM_PROT_WRITE) == VM_PROT_WRITE)
- dnb_permissions |= eMemoryPermissionsWritable;
- if ((m_data.protection & VM_PROT_EXECUTE) == VM_PROT_EXECUTE)
- dnb_permissions |= eMemoryPermissionsExecutable;
- return dnb_permissions;
+uint32_t MachVMRegion::GetDNBPermissions() const {
+ if (m_addr == INVALID_NUB_ADDRESS || m_start == INVALID_NUB_ADDRESS ||
+ m_size == 0)
+ return 0;
+ uint32_t dnb_permissions = 0;
+
+ if ((m_data.protection & VM_PROT_READ) == VM_PROT_READ)
+ dnb_permissions |= eMemoryPermissionsReadable;
+ if ((m_data.protection & VM_PROT_WRITE) == VM_PROT_WRITE)
+ dnb_permissions |= eMemoryPermissionsWritable;
+ if ((m_data.protection & VM_PROT_EXECUTE) == VM_PROT_EXECUTE)
+ dnb_permissions |= eMemoryPermissionsExecutable;
+ return dnb_permissions;
}
Modified: lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/MachVMRegion.h Tue Sep 6 15:57:50 2016
@@ -18,60 +18,56 @@
#include "DNBError.h"
#include <mach/mach.h>
-class MachVMRegion
-{
+class MachVMRegion {
public:
- MachVMRegion(task_t task);
- ~MachVMRegion();
+ MachVMRegion(task_t task);
+ ~MachVMRegion();
+
+ void Clear();
+ mach_vm_address_t StartAddress() const { return m_start; }
+ mach_vm_address_t EndAddress() const { return m_start + m_size; }
+ mach_vm_size_t GetByteSize() const { return m_size; }
+ mach_vm_address_t BytesRemaining(mach_vm_address_t addr) const {
+ if (ContainsAddress(addr))
+ return m_size - (addr - m_start);
+ else
+ return 0;
+ }
+ bool ContainsAddress(mach_vm_address_t addr) const {
+ return addr >= StartAddress() && addr < EndAddress();
+ }
+
+ bool SetProtections(mach_vm_address_t addr, mach_vm_size_t size,
+ vm_prot_t prot);
+ bool RestoreProtections();
+ bool GetRegionForAddress(nub_addr_t addr);
+
+ uint32_t GetDNBPermissions() const;
+
+ const DNBError &GetError() { return m_err; }
- void Clear();
- mach_vm_address_t StartAddress() const { return m_start; }
- mach_vm_address_t EndAddress() const { return m_start + m_size; }
- mach_vm_size_t GetByteSize () const { return m_size; }
- mach_vm_address_t BytesRemaining(mach_vm_address_t addr) const
- {
- if (ContainsAddress(addr))
- return m_size - (addr - m_start);
- else
- return 0;
- }
- bool ContainsAddress(mach_vm_address_t addr) const
- {
- return addr >= StartAddress() && addr < EndAddress();
- }
-
- bool SetProtections(mach_vm_address_t addr, mach_vm_size_t size, vm_prot_t prot);
- bool RestoreProtections();
- bool GetRegionForAddress(nub_addr_t addr);
-
- uint32_t
- GetDNBPermissions () const;
-
- const DNBError &
- GetError ()
- {
- return m_err;
- }
protected:
-#if defined (VM_REGION_SUBMAP_SHORT_INFO_COUNT_64)
- typedef vm_region_submap_short_info_data_64_t RegionInfo;
- enum { kRegionInfoSize = VM_REGION_SUBMAP_SHORT_INFO_COUNT_64 };
+#if defined(VM_REGION_SUBMAP_SHORT_INFO_COUNT_64)
+ typedef vm_region_submap_short_info_data_64_t RegionInfo;
+ enum { kRegionInfoSize = VM_REGION_SUBMAP_SHORT_INFO_COUNT_64 };
#else
- typedef vm_region_submap_info_data_64_t RegionInfo;
- enum { kRegionInfoSize = VM_REGION_SUBMAP_INFO_COUNT_64 };
+ typedef vm_region_submap_info_data_64_t RegionInfo;
+ enum { kRegionInfoSize = VM_REGION_SUBMAP_INFO_COUNT_64 };
#endif
- task_t m_task;
- mach_vm_address_t m_addr;
- DNBError m_err;
- mach_vm_address_t m_start;
- mach_vm_size_t m_size;
- natural_t m_depth;
- RegionInfo m_data;
- vm_prot_t m_curr_protection; // The current, possibly modified protections. Original value is saved in m_data.protections.
- mach_vm_address_t m_protection_addr; // The start address at which protections were changed
- mach_vm_size_t m_protection_size; // The size of memory that had its protections changed
-
+ task_t m_task;
+ mach_vm_address_t m_addr;
+ DNBError m_err;
+ mach_vm_address_t m_start;
+ mach_vm_size_t m_size;
+ natural_t m_depth;
+ RegionInfo m_data;
+ vm_prot_t m_curr_protection; // The current, possibly modified protections.
+ // Original value is saved in m_data.protections.
+ mach_vm_address_t
+ m_protection_addr; // The start address at which protections were changed
+ mach_vm_size_t
+ m_protection_size; // The size of memory that had its protections changed
};
-#endif // #ifndef __MachVMRegion_h__
+#endif // #ifndef __MachVMRegion_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.cpp Tue Sep 6 15:57:50 2016
@@ -18,54 +18,49 @@
#define LLDB_OS_LOG_MAX_BUFFER_LENGTH 256
-namespace
-{
- //----------------------------------------------------------------------
- // Darwin os_log logging callback that can be registered with
- // DNBLogSetLogCallback
- //----------------------------------------------------------------------
- void
- DarwinLogCallback(void *baton, uint32_t flags, const char *format,
- va_list args)
- {
- if (format == nullptr)
- return;
-
- static os_log_t g_logger;
- if (!g_logger)
- {
- g_logger = os_log_create("com.apple.dt.lldb", "debugserver");
- if (!g_logger)
- return;
- }
-
- os_log_type_t log_type;
- if (flags & DNBLOG_FLAG_FATAL) log_type = OS_LOG_TYPE_FAULT;
- else if (flags & DNBLOG_FLAG_ERROR) log_type = OS_LOG_TYPE_ERROR;
- else if (flags & DNBLOG_FLAG_WARNING) log_type = OS_LOG_TYPE_DEFAULT;
- else if (flags & DNBLOG_FLAG_VERBOSE) log_type = OS_LOG_TYPE_DEBUG;
- else log_type = OS_LOG_TYPE_DEFAULT;
-
- // This code is unfortunate. os_log* only takes static strings, but
- // our current log API isn't set up to make use of that style.
- char buffer[LLDB_OS_LOG_MAX_BUFFER_LENGTH];
- vsnprintf(buffer, sizeof(buffer), format, args);
- os_log_with_type(g_logger, log_type, "%{public}s", buffer);
- }
+namespace {
+//----------------------------------------------------------------------
+// Darwin os_log logging callback that can be registered with
+// DNBLogSetLogCallback
+//----------------------------------------------------------------------
+void DarwinLogCallback(void *baton, uint32_t flags, const char *format,
+ va_list args) {
+ if (format == nullptr)
+ return;
+
+ static os_log_t g_logger;
+ if (!g_logger) {
+ g_logger = os_log_create("com.apple.dt.lldb", "debugserver");
+ if (!g_logger)
+ return;
+ }
+
+ os_log_type_t log_type;
+ if (flags & DNBLOG_FLAG_FATAL)
+ log_type = OS_LOG_TYPE_FAULT;
+ else if (flags & DNBLOG_FLAG_ERROR)
+ log_type = OS_LOG_TYPE_ERROR;
+ else if (flags & DNBLOG_FLAG_WARNING)
+ log_type = OS_LOG_TYPE_DEFAULT;
+ else if (flags & DNBLOG_FLAG_VERBOSE)
+ log_type = OS_LOG_TYPE_DEBUG;
+ else
+ log_type = OS_LOG_TYPE_DEFAULT;
+
+ // This code is unfortunate. os_log* only takes static strings, but
+ // our current log API isn't set up to make use of that style.
+ char buffer[LLDB_OS_LOG_MAX_BUFFER_LENGTH];
+ vsnprintf(buffer, sizeof(buffer), format, args);
+ os_log_with_type(g_logger, log_type, "%{public}s", buffer);
+}
}
-DNBCallbackLog
-OsLogger::GetLogFunction()
-{
- return _os_log_impl ? DarwinLogCallback : nullptr;
+DNBCallbackLog OsLogger::GetLogFunction() {
+ return _os_log_impl ? DarwinLogCallback : nullptr;
}
#else
-DNBCallbackLog
-OsLogger::GetLogFunction()
-{
- return nullptr;
-}
+DNBCallbackLog OsLogger::GetLogFunction() { return nullptr; }
#endif
Modified: lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/OsLogger.h Tue Sep 6 15:57:50 2016
@@ -12,13 +12,9 @@
#include "DNBDefs.h"
-class OsLogger
-{
+class OsLogger {
public:
-
- static DNBCallbackLog
- GetLogFunction();
-
+ static DNBCallbackLog GetLogFunction();
};
#endif /* OsLogger_h */
Modified: lldb/trunk/tools/debugserver/source/MacOSX/ThreadInfo.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/ThreadInfo.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/ThreadInfo.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/ThreadInfo.h Tue Sep 6 15:57:50 2016
@@ -1,4 +1,5 @@
-//===-- ThreadInfo.h -----------------------------------------------*- C++ -*-===//
+//===-- ThreadInfo.h -----------------------------------------------*- C++
+//-*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -14,13 +15,12 @@ namespace ThreadInfo {
class QoS {
public:
- QoS () : constant_name(), printable_name(), enum_value(UINT32_MAX) { }
- bool IsValid () { return enum_value != UINT32_MAX; }
- std::string constant_name;
- std::string printable_name;
- uint32_t enum_value;
+ QoS() : constant_name(), printable_name(), enum_value(UINT32_MAX) {}
+ bool IsValid() { return enum_value != UINT32_MAX; }
+ std::string constant_name;
+ std::string printable_name;
+ uint32_t enum_value;
};
-
};
#endif // __ThreadInfo_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp Tue Sep 6 15:57:50 2016
@@ -11,93 +11,93 @@
//
//===----------------------------------------------------------------------===//
-#if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
+#if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
#include "MacOSX/arm/DNBArchImpl.h"
-#include "MacOSX/MachProcess.h"
-#include "MacOSX/MachThread.h"
+#include "ARM_DWARF_Registers.h"
+#include "ARM_ehframe_Registers.h"
+#include "DNB.h"
#include "DNBBreakpoint.h"
#include "DNBLog.h"
#include "DNBRegisterInfo.h"
-#include "DNB.h"
-#include "ARM_ehframe_Registers.h"
-#include "ARM_DWARF_Registers.h"
+#include "MacOSX/MachProcess.h"
+#include "MacOSX/MachThread.h"
#include <inttypes.h>
#include <sys/sysctl.h>
// BCR address match type
-#define BCR_M_IMVA_MATCH ((uint32_t)(0u << 21))
-#define BCR_M_CONTEXT_ID_MATCH ((uint32_t)(1u << 21))
-#define BCR_M_IMVA_MISMATCH ((uint32_t)(2u << 21))
-#define BCR_M_RESERVED ((uint32_t)(3u << 21))
+#define BCR_M_IMVA_MATCH ((uint32_t)(0u << 21))
+#define BCR_M_CONTEXT_ID_MATCH ((uint32_t)(1u << 21))
+#define BCR_M_IMVA_MISMATCH ((uint32_t)(2u << 21))
+#define BCR_M_RESERVED ((uint32_t)(3u << 21))
// Link a BVR/BCR or WVR/WCR pair to another
-#define E_ENABLE_LINKING ((uint32_t)(1u << 20))
+#define E_ENABLE_LINKING ((uint32_t)(1u << 20))
// Byte Address Select
-#define BAS_IMVA_PLUS_0 ((uint32_t)(1u << 5))
-#define BAS_IMVA_PLUS_1 ((uint32_t)(1u << 6))
-#define BAS_IMVA_PLUS_2 ((uint32_t)(1u << 7))
-#define BAS_IMVA_PLUS_3 ((uint32_t)(1u << 8))
-#define BAS_IMVA_0_1 ((uint32_t)(3u << 5))
-#define BAS_IMVA_2_3 ((uint32_t)(3u << 7))
-#define BAS_IMVA_ALL ((uint32_t)(0xfu << 5))
+#define BAS_IMVA_PLUS_0 ((uint32_t)(1u << 5))
+#define BAS_IMVA_PLUS_1 ((uint32_t)(1u << 6))
+#define BAS_IMVA_PLUS_2 ((uint32_t)(1u << 7))
+#define BAS_IMVA_PLUS_3 ((uint32_t)(1u << 8))
+#define BAS_IMVA_0_1 ((uint32_t)(3u << 5))
+#define BAS_IMVA_2_3 ((uint32_t)(3u << 7))
+#define BAS_IMVA_ALL ((uint32_t)(0xfu << 5))
// Break only in privileged or user mode
-#define S_RSVD ((uint32_t)(0u << 1))
-#define S_PRIV ((uint32_t)(1u << 1))
-#define S_USER ((uint32_t)(2u << 1))
-#define S_PRIV_USER ((S_PRIV) | (S_USER))
+#define S_RSVD ((uint32_t)(0u << 1))
+#define S_PRIV ((uint32_t)(1u << 1))
+#define S_USER ((uint32_t)(2u << 1))
+#define S_PRIV_USER ((S_PRIV) | (S_USER))
-#define BCR_ENABLE ((uint32_t)(1u))
-#define WCR_ENABLE ((uint32_t)(1u))
+#define BCR_ENABLE ((uint32_t)(1u))
+#define WCR_ENABLE ((uint32_t)(1u))
// Watchpoint load/store
-#define WCR_LOAD ((uint32_t)(1u << 3))
-#define WCR_STORE ((uint32_t)(1u << 4))
+#define WCR_LOAD ((uint32_t)(1u << 3))
+#define WCR_STORE ((uint32_t)(1u << 4))
// Definitions for the Debug Status and Control Register fields:
// [5:2] => Method of debug entry
//#define WATCHPOINT_OCCURRED ((uint32_t)(2u))
// I'm seeing this, instead.
-#define WATCHPOINT_OCCURRED ((uint32_t)(10u))
+#define WATCHPOINT_OCCURRED ((uint32_t)(10u))
// 0xE120BE70
-static const uint8_t g_arm_breakpoint_opcode[] = { 0x70, 0xBE, 0x20, 0xE1 };
-static const uint8_t g_thumb_breakpoint_opcode[] = { 0x70, 0xBE };
+static const uint8_t g_arm_breakpoint_opcode[] = {0x70, 0xBE, 0x20, 0xE1};
+static const uint8_t g_thumb_breakpoint_opcode[] = {0x70, 0xBE};
// A watchpoint may need to be implemented using two watchpoint registers.
// e.g. watching an 8-byte region when the device can only watch 4-bytes.
//
// This stores the lo->hi mappings. It's safe to initialize to all 0's
// since hi > lo and therefore LoHi[i] cannot be 0.
-static uint32_t LoHi[16] = { 0 };
+static uint32_t LoHi[16] = {0};
// ARM constants used during decoding
-#define REG_RD 0
-#define LDM_REGLIST 1
-#define PC_REG 15
-#define PC_REGLIST_BIT 0x8000
+#define REG_RD 0
+#define LDM_REGLIST 1
+#define PC_REG 15
+#define PC_REGLIST_BIT 0x8000
// ARM conditions
-#define COND_EQ 0x0
-#define COND_NE 0x1
-#define COND_CS 0x2
-#define COND_HS 0x2
-#define COND_CC 0x3
-#define COND_LO 0x3
-#define COND_MI 0x4
-#define COND_PL 0x5
-#define COND_VS 0x6
-#define COND_VC 0x7
-#define COND_HI 0x8
-#define COND_LS 0x9
-#define COND_GE 0xA
-#define COND_LT 0xB
-#define COND_GT 0xC
-#define COND_LE 0xD
-#define COND_AL 0xE
+#define COND_EQ 0x0
+#define COND_NE 0x1
+#define COND_CS 0x2
+#define COND_HS 0x2
+#define COND_CC 0x3
+#define COND_LO 0x3
+#define COND_MI 0x4
+#define COND_PL 0x5
+#define COND_VS 0x6
+#define COND_VC 0x7
+#define COND_HI 0x8
+#define COND_LS 0x9
+#define COND_GE 0xA
+#define COND_LT 0xB
+#define COND_GT 0xC
+#define COND_LE 0xD
+#define COND_AL 0xE
#define COND_UNCOND 0xF
#define MASK_CPSR_T (1u << 5)
@@ -108,962 +108,971 @@ static uint32_t LoHi[16] = { 0 };
// Returns true if the first 16 bit opcode of a thumb instruction indicates
// the instruction will be a 32 bit thumb opcode
-static bool
-IsThumb32Opcode (uint16_t opcode)
-{
- if (((opcode & 0xE000) == 0xE000) && (opcode & 0x1800))
- return true;
- return false;
-}
-
-void
-DNBArchMachARM::Initialize()
-{
- DNBArchPluginInfo arch_plugin_info =
- {
- CPU_TYPE_ARM,
- DNBArchMachARM::Create,
- DNBArchMachARM::GetRegisterSetInfo,
- DNBArchMachARM::SoftwareBreakpointOpcode
- };
-
- // Register this arch plug-in with the main protocol class
- DNBArchProtocol::RegisterArchPlugin (arch_plugin_info);
-}
-
-
-DNBArchProtocol *
-DNBArchMachARM::Create (MachThread *thread)
-{
- DNBArchMachARM *obj = new DNBArchMachARM (thread);
- return obj;
-}
-
-const uint8_t *
-DNBArchMachARM::SoftwareBreakpointOpcode (nub_size_t byte_size)
-{
- switch (byte_size)
- {
- case 2: return g_thumb_breakpoint_opcode;
- case 4: return g_arm_breakpoint_opcode;
- }
- return NULL;
-}
-
-uint32_t
-DNBArchMachARM::GetCPUType()
-{
- return CPU_TYPE_ARM;
-}
-
-uint64_t
-DNBArchMachARM::GetPC(uint64_t failValue)
-{
- // Get program counter
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.context.gpr.__pc;
- return failValue;
-}
-
-kern_return_t
-DNBArchMachARM::SetPC(uint64_t value)
-{
- // Get program counter
- kern_return_t err = GetGPRState(false);
- if (err == KERN_SUCCESS)
- {
- m_state.context.gpr.__pc = (uint32_t) value;
- err = SetGPRState();
- }
- return err == KERN_SUCCESS;
-}
-
-uint64_t
-DNBArchMachARM::GetSP(uint64_t failValue)
-{
- // Get stack pointer
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.context.gpr.__sp;
- return failValue;
-}
-
-kern_return_t
-DNBArchMachARM::GetGPRState(bool force)
-{
- int set = e_regSetGPR;
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
- mach_msg_type_number_t count = ARM_THREAD_STATE_COUNT;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count);
- uint32_t *r = &m_state.context.gpr.__r[0];
- DNBLogThreadedIf(LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs r0=%8.8x r1=%8.8x r2=%8.8x r3=%8.8x r4=%8.8x r5=%8.8x r6=%8.8x r7=%8.8x r8=%8.8x r9=%8.8x r10=%8.8x r11=%8.8x s12=%8.8x sp=%8.8x lr=%8.8x pc=%8.8x cpsr=%8.8x",
- m_thread->MachPortNumber(),
- ARM_THREAD_STATE,
- ARM_THREAD_STATE_COUNT,
- kret,
- count,
- r[0],
- r[1],
- r[2],
- r[3],
- r[4],
- r[5],
- r[6],
- r[7],
- r[8],
- r[9],
- r[10],
- r[11],
- r[12],
- r[13],
- r[14],
- r[15],
- r[16]);
- m_state.SetError(set, Read, kret);
- return kret;
-}
-
-kern_return_t
-DNBArchMachARM::GetVFPState(bool force)
-{
- int set = e_regSetVFP;
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- kern_return_t kret;
-
-#if defined (__arm64__) || defined (__aarch64__)
- // Read the registers from our thread
- mach_msg_type_number_t count = ARM_NEON_STATE_COUNT;
- kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE, (thread_state_t)&m_state.context.vfp, &count);
- if (DNBLogEnabledForAny (LOG_THREAD))
- {
- DNBLogThreaded("thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
- "\n q0 = 0x%16.16llx%16.16llx"
- "\n q1 = 0x%16.16llx%16.16llx"
- "\n q2 = 0x%16.16llx%16.16llx"
- "\n q3 = 0x%16.16llx%16.16llx"
- "\n q4 = 0x%16.16llx%16.16llx"
- "\n q5 = 0x%16.16llx%16.16llx"
- "\n q6 = 0x%16.16llx%16.16llx"
- "\n q7 = 0x%16.16llx%16.16llx"
- "\n q8 = 0x%16.16llx%16.16llx"
- "\n q9 = 0x%16.16llx%16.16llx"
- "\n q10 = 0x%16.16llx%16.16llx"
- "\n q11 = 0x%16.16llx%16.16llx"
- "\n q12 = 0x%16.16llx%16.16llx"
- "\n q13 = 0x%16.16llx%16.16llx"
- "\n q14 = 0x%16.16llx%16.16llx"
- "\n q15 = 0x%16.16llx%16.16llx"
- "\n fpsr = 0x%8.8x"
- "\n fpcr = 0x%8.8x\n\n",
- m_thread->MachPortNumber(),
- ARM_NEON_STATE,
- ARM_NEON_STATE_COUNT,
- kret,
- count,
- ((uint64_t *)&m_state.context.vfp.__v[0])[0] , ((uint64_t *)&m_state.context.vfp.__v[0])[1],
- ((uint64_t *)&m_state.context.vfp.__v[1])[0] , ((uint64_t *)&m_state.context.vfp.__v[1])[1],
- ((uint64_t *)&m_state.context.vfp.__v[2])[0] , ((uint64_t *)&m_state.context.vfp.__v[2])[1],
- ((uint64_t *)&m_state.context.vfp.__v[3])[0] , ((uint64_t *)&m_state.context.vfp.__v[3])[1],
- ((uint64_t *)&m_state.context.vfp.__v[4])[0] , ((uint64_t *)&m_state.context.vfp.__v[4])[1],
- ((uint64_t *)&m_state.context.vfp.__v[5])[0] , ((uint64_t *)&m_state.context.vfp.__v[5])[1],
- ((uint64_t *)&m_state.context.vfp.__v[6])[0] , ((uint64_t *)&m_state.context.vfp.__v[6])[1],
- ((uint64_t *)&m_state.context.vfp.__v[7])[0] , ((uint64_t *)&m_state.context.vfp.__v[7])[1],
- ((uint64_t *)&m_state.context.vfp.__v[8])[0] , ((uint64_t *)&m_state.context.vfp.__v[8])[1],
- ((uint64_t *)&m_state.context.vfp.__v[9])[0] , ((uint64_t *)&m_state.context.vfp.__v[9])[1],
- ((uint64_t *)&m_state.context.vfp.__v[10])[0], ((uint64_t *)&m_state.context.vfp.__v[10])[1],
- ((uint64_t *)&m_state.context.vfp.__v[11])[0], ((uint64_t *)&m_state.context.vfp.__v[11])[1],
- ((uint64_t *)&m_state.context.vfp.__v[12])[0], ((uint64_t *)&m_state.context.vfp.__v[12])[1],
- ((uint64_t *)&m_state.context.vfp.__v[13])[0], ((uint64_t *)&m_state.context.vfp.__v[13])[1],
- ((uint64_t *)&m_state.context.vfp.__v[14])[0], ((uint64_t *)&m_state.context.vfp.__v[14])[1],
- ((uint64_t *)&m_state.context.vfp.__v[15])[0], ((uint64_t *)&m_state.context.vfp.__v[15])[1],
- m_state.context.vfp.__fpsr,
- m_state.context.vfp.__fpcr);
-
- }
+static bool IsThumb32Opcode(uint16_t opcode) {
+ if (((opcode & 0xE000) == 0xE000) && (opcode & 0x1800))
+ return true;
+ return false;
+}
+
+void DNBArchMachARM::Initialize() {
+ DNBArchPluginInfo arch_plugin_info = {
+ CPU_TYPE_ARM, DNBArchMachARM::Create, DNBArchMachARM::GetRegisterSetInfo,
+ DNBArchMachARM::SoftwareBreakpointOpcode};
+
+ // Register this arch plug-in with the main protocol class
+ DNBArchProtocol::RegisterArchPlugin(arch_plugin_info);
+}
+
+DNBArchProtocol *DNBArchMachARM::Create(MachThread *thread) {
+ DNBArchMachARM *obj = new DNBArchMachARM(thread);
+ return obj;
+}
+
+const uint8_t *DNBArchMachARM::SoftwareBreakpointOpcode(nub_size_t byte_size) {
+ switch (byte_size) {
+ case 2:
+ return g_thumb_breakpoint_opcode;
+ case 4:
+ return g_arm_breakpoint_opcode;
+ }
+ return NULL;
+}
+
+uint32_t DNBArchMachARM::GetCPUType() { return CPU_TYPE_ARM; }
+
+uint64_t DNBArchMachARM::GetPC(uint64_t failValue) {
+ // Get program counter
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.context.gpr.__pc;
+ return failValue;
+}
+
+kern_return_t DNBArchMachARM::SetPC(uint64_t value) {
+ // Get program counter
+ kern_return_t err = GetGPRState(false);
+ if (err == KERN_SUCCESS) {
+ m_state.context.gpr.__pc = (uint32_t)value;
+ err = SetGPRState();
+ }
+ return err == KERN_SUCCESS;
+}
+
+uint64_t DNBArchMachARM::GetSP(uint64_t failValue) {
+ // Get stack pointer
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.context.gpr.__sp;
+ return failValue;
+}
+
+kern_return_t DNBArchMachARM::GetGPRState(bool force) {
+ int set = e_regSetGPR;
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ // Read the registers from our thread
+ mach_msg_type_number_t count = ARM_THREAD_STATE_COUNT;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE,
+ (thread_state_t)&m_state.context.gpr, &count);
+ uint32_t *r = &m_state.context.gpr.__r[0];
+ DNBLogThreadedIf(
+ LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = "
+ "%u) regs r0=%8.8x r1=%8.8x r2=%8.8x r3=%8.8x r4=%8.8x "
+ "r5=%8.8x r6=%8.8x r7=%8.8x r8=%8.8x r9=%8.8x r10=%8.8x "
+ "r11=%8.8x s12=%8.8x sp=%8.8x lr=%8.8x pc=%8.8x cpsr=%8.8x",
+ m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
+ kret, count, r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7], r[8], r[9],
+ r[10], r[11], r[12], r[13], r[14], r[15], r[16]);
+ m_state.SetError(set, Read, kret);
+ return kret;
+}
+
+kern_return_t DNBArchMachARM::GetVFPState(bool force) {
+ int set = e_regSetVFP;
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ kern_return_t kret;
+
+#if defined(__arm64__) || defined(__aarch64__)
+ // Read the registers from our thread
+ mach_msg_type_number_t count = ARM_NEON_STATE_COUNT;
+ kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE,
+ (thread_state_t)&m_state.context.vfp, &count);
+ if (DNBLogEnabledForAny(LOG_THREAD)) {
+ DNBLogThreaded(
+ "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
+ "\n q0 = 0x%16.16llx%16.16llx"
+ "\n q1 = 0x%16.16llx%16.16llx"
+ "\n q2 = 0x%16.16llx%16.16llx"
+ "\n q3 = 0x%16.16llx%16.16llx"
+ "\n q4 = 0x%16.16llx%16.16llx"
+ "\n q5 = 0x%16.16llx%16.16llx"
+ "\n q6 = 0x%16.16llx%16.16llx"
+ "\n q7 = 0x%16.16llx%16.16llx"
+ "\n q8 = 0x%16.16llx%16.16llx"
+ "\n q9 = 0x%16.16llx%16.16llx"
+ "\n q10 = 0x%16.16llx%16.16llx"
+ "\n q11 = 0x%16.16llx%16.16llx"
+ "\n q12 = 0x%16.16llx%16.16llx"
+ "\n q13 = 0x%16.16llx%16.16llx"
+ "\n q14 = 0x%16.16llx%16.16llx"
+ "\n q15 = 0x%16.16llx%16.16llx"
+ "\n fpsr = 0x%8.8x"
+ "\n fpcr = 0x%8.8x\n\n",
+ m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret,
+ count, ((uint64_t *)&m_state.context.vfp.__v[0])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[0])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[1])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[1])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[2])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[2])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[3])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[3])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[4])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[4])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[5])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[5])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[6])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[6])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[7])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[7])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[8])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[8])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[9])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[9])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[10])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[10])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[11])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[11])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[12])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[12])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[13])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[13])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[14])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[14])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[15])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[15])[1],
+ m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
+ }
#else
- // Read the registers from our thread
- mach_msg_type_number_t count = ARM_VFP_STATE_COUNT;
- kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_VFP_STATE, (thread_state_t)&m_state.context.vfp, &count);
-
- if (DNBLogEnabledForAny (LOG_THREAD))
- {
- uint32_t *r = &m_state.context.vfp.__r[0];
- DNBLogThreaded ("thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
- m_thread->MachPortNumber(),
- ARM_THREAD_STATE,
- ARM_THREAD_STATE_COUNT,
- kret,
- count);
- DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x s5=%8.8x s6=%8.8x s7=%8.8x",r[ 0],r[ 1],r[ 2],r[ 3],r[ 4],r[ 5],r[ 6],r[ 7]);
- DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x s13=%8.8x s14=%8.8x s15=%8.8x",r[ 8],r[ 9],r[10],r[11],r[12],r[13],r[14],r[15]);
- DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x s21=%8.8x s22=%8.8x s23=%8.8x",r[16],r[17],r[18],r[19],r[20],r[21],r[22],r[23]);
- DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x s29=%8.8x s30=%8.8x s31=%8.8x",r[24],r[25],r[26],r[27],r[28],r[29],r[30],r[31]);
- DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x s37=%8.8x s38=%8.8x s39=%8.8x",r[32],r[33],r[34],r[35],r[36],r[37],r[38],r[39]);
- DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x s45=%8.8x s46=%8.8x s47=%8.8x",r[40],r[41],r[42],r[43],r[44],r[45],r[46],r[47]);
- DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x s53=%8.8x s54=%8.8x s55=%8.8x",r[48],r[49],r[50],r[51],r[52],r[53],r[54],r[55]);
- DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",r[56],r[57],r[58],r[59],r[60],r[61],r[62],r[63],r[64]);
- }
-
-#endif
- m_state.SetError(set, Read, kret);
- return kret;
-}
-
-kern_return_t
-DNBArchMachARM::GetEXCState(bool force)
-{
- int set = e_regSetEXC;
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
- mach_msg_type_number_t count = ARM_EXCEPTION_STATE_COUNT;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count);
- m_state.SetError(set, Read, kret);
- return kret;
-}
-
-static void
-DumpDBGState(const DNBArchMachARM::DBG& dbg)
-{
- uint32_t i = 0;
- for (i=0; i<16; i++)
- {
- DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
- i, i, dbg.__bvr[i], dbg.__bcr[i],
- i, i, dbg.__wvr[i], dbg.__wcr[i]);
- }
-}
-
-kern_return_t
-DNBArchMachARM::GetDBGState(bool force)
-{
- int set = e_regSetDBG;
-
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
-#if defined (ARM_DEBUG_STATE32) && (defined (__arm64__) || defined (__aarch64__))
- mach_msg_type_number_t count = ARM_DEBUG_STATE32_COUNT;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32, (thread_state_t)&m_state.dbg, &count);
+ // Read the registers from our thread
+ mach_msg_type_number_t count = ARM_VFP_STATE_COUNT;
+ kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_VFP_STATE,
+ (thread_state_t)&m_state.context.vfp, &count);
+
+ if (DNBLogEnabledForAny(LOG_THREAD)) {
+ uint32_t *r = &m_state.context.vfp.__r[0];
+ DNBLogThreaded(
+ "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
+ m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
+ kret, count);
+ DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x "
+ "s5=%8.8x s6=%8.8x s7=%8.8x",
+ r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
+ DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x "
+ "s13=%8.8x s14=%8.8x s15=%8.8x",
+ r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
+ DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x "
+ "s21=%8.8x s22=%8.8x s23=%8.8x",
+ r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]);
+ DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x "
+ "s29=%8.8x s30=%8.8x s31=%8.8x",
+ r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]);
+ DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x "
+ "s37=%8.8x s38=%8.8x s39=%8.8x",
+ r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]);
+ DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x "
+ "s45=%8.8x s46=%8.8x s47=%8.8x",
+ r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]);
+ DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x "
+ "s53=%8.8x s54=%8.8x s55=%8.8x",
+ r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]);
+ DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x "
+ "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",
+ r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63],
+ r[64]);
+ }
+
+#endif
+ m_state.SetError(set, Read, kret);
+ return kret;
+}
+
+kern_return_t DNBArchMachARM::GetEXCState(bool force) {
+ int set = e_regSetEXC;
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ // Read the registers from our thread
+ mach_msg_type_number_t count = ARM_EXCEPTION_STATE_COUNT;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE,
+ (thread_state_t)&m_state.context.exc, &count);
+ m_state.SetError(set, Read, kret);
+ return kret;
+}
+
+static void DumpDBGState(const DNBArchMachARM::DBG &dbg) {
+ uint32_t i = 0;
+ for (i = 0; i < 16; i++) {
+ DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } "
+ "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
+ i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i],
+ dbg.__wcr[i]);
+ }
+}
+
+kern_return_t DNBArchMachARM::GetDBGState(bool force) {
+ int set = e_regSetDBG;
+
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+// Read the registers from our thread
+#if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
+ mach_msg_type_number_t count = ARM_DEBUG_STATE32_COUNT;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32,
+ (thread_state_t)&m_state.dbg, &count);
#else
- mach_msg_type_number_t count = ARM_DEBUG_STATE_COUNT;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE, (thread_state_t)&m_state.dbg, &count);
-#endif
- m_state.SetError(set, Read, kret);
-
- return kret;
-}
-
-kern_return_t
-DNBArchMachARM::SetGPRState()
-{
- int set = e_regSetGPR;
- kern_return_t kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_THREAD_STATE, (thread_state_t)&m_state.context.gpr, ARM_THREAD_STATE_COUNT);
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-kern_return_t
-DNBArchMachARM::SetVFPState()
-{
- int set = e_regSetVFP;
- kern_return_t kret;
- mach_msg_type_number_t count;
-
-#if defined (__arm64__) || defined (__aarch64__)
- count = ARM_NEON_STATE_COUNT;
- kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_NEON_STATE, (thread_state_t)&m_state.context.vfp, count);
+ mach_msg_type_number_t count = ARM_DEBUG_STATE_COUNT;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE,
+ (thread_state_t)&m_state.dbg, &count);
+#endif
+ m_state.SetError(set, Read, kret);
+
+ return kret;
+}
+
+kern_return_t DNBArchMachARM::SetGPRState() {
+ int set = e_regSetGPR;
+ kern_return_t kret = ::thread_set_state(
+ m_thread->MachPortNumber(), ARM_THREAD_STATE,
+ (thread_state_t)&m_state.context.gpr, ARM_THREAD_STATE_COUNT);
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+kern_return_t DNBArchMachARM::SetVFPState() {
+ int set = e_regSetVFP;
+ kern_return_t kret;
+ mach_msg_type_number_t count;
+
+#if defined(__arm64__) || defined(__aarch64__)
+ count = ARM_NEON_STATE_COUNT;
+ kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_NEON_STATE,
+ (thread_state_t)&m_state.context.vfp, count);
#else
- count = ARM_VFP_STATE_COUNT;
- kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_VFP_STATE, (thread_state_t)&m_state.context.vfp, count);
-#endif
-
-#if defined (__arm64__) || defined (__aarch64__)
- if (DNBLogEnabledForAny (LOG_THREAD))
- {
- DNBLogThreaded("thread_set_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
- "\n q0 = 0x%16.16llx%16.16llx"
- "\n q1 = 0x%16.16llx%16.16llx"
- "\n q2 = 0x%16.16llx%16.16llx"
- "\n q3 = 0x%16.16llx%16.16llx"
- "\n q4 = 0x%16.16llx%16.16llx"
- "\n q5 = 0x%16.16llx%16.16llx"
- "\n q6 = 0x%16.16llx%16.16llx"
- "\n q7 = 0x%16.16llx%16.16llx"
- "\n q8 = 0x%16.16llx%16.16llx"
- "\n q9 = 0x%16.16llx%16.16llx"
- "\n q10 = 0x%16.16llx%16.16llx"
- "\n q11 = 0x%16.16llx%16.16llx"
- "\n q12 = 0x%16.16llx%16.16llx"
- "\n q13 = 0x%16.16llx%16.16llx"
- "\n q14 = 0x%16.16llx%16.16llx"
- "\n q15 = 0x%16.16llx%16.16llx"
- "\n fpsr = 0x%8.8x"
- "\n fpcr = 0x%8.8x\n\n",
- m_thread->MachPortNumber(),
- ARM_NEON_STATE,
- ARM_NEON_STATE_COUNT,
- kret,
- count,
- ((uint64_t *)&m_state.context.vfp.__v[0])[0] , ((uint64_t *)&m_state.context.vfp.__v[0])[1],
- ((uint64_t *)&m_state.context.vfp.__v[1])[0] , ((uint64_t *)&m_state.context.vfp.__v[1])[1],
- ((uint64_t *)&m_state.context.vfp.__v[2])[0] , ((uint64_t *)&m_state.context.vfp.__v[2])[1],
- ((uint64_t *)&m_state.context.vfp.__v[3])[0] , ((uint64_t *)&m_state.context.vfp.__v[3])[1],
- ((uint64_t *)&m_state.context.vfp.__v[4])[0] , ((uint64_t *)&m_state.context.vfp.__v[4])[1],
- ((uint64_t *)&m_state.context.vfp.__v[5])[0] , ((uint64_t *)&m_state.context.vfp.__v[5])[1],
- ((uint64_t *)&m_state.context.vfp.__v[6])[0] , ((uint64_t *)&m_state.context.vfp.__v[6])[1],
- ((uint64_t *)&m_state.context.vfp.__v[7])[0] , ((uint64_t *)&m_state.context.vfp.__v[7])[1],
- ((uint64_t *)&m_state.context.vfp.__v[8])[0] , ((uint64_t *)&m_state.context.vfp.__v[8])[1],
- ((uint64_t *)&m_state.context.vfp.__v[9])[0] , ((uint64_t *)&m_state.context.vfp.__v[9])[1],
- ((uint64_t *)&m_state.context.vfp.__v[10])[0], ((uint64_t *)&m_state.context.vfp.__v[10])[1],
- ((uint64_t *)&m_state.context.vfp.__v[11])[0], ((uint64_t *)&m_state.context.vfp.__v[11])[1],
- ((uint64_t *)&m_state.context.vfp.__v[12])[0], ((uint64_t *)&m_state.context.vfp.__v[12])[1],
- ((uint64_t *)&m_state.context.vfp.__v[13])[0], ((uint64_t *)&m_state.context.vfp.__v[13])[1],
- ((uint64_t *)&m_state.context.vfp.__v[14])[0], ((uint64_t *)&m_state.context.vfp.__v[14])[1],
- ((uint64_t *)&m_state.context.vfp.__v[15])[0], ((uint64_t *)&m_state.context.vfp.__v[15])[1],
- m_state.context.vfp.__fpsr,
- m_state.context.vfp.__fpcr);
- }
+ count = ARM_VFP_STATE_COUNT;
+ kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_VFP_STATE,
+ (thread_state_t)&m_state.context.vfp, count);
+#endif
+
+#if defined(__arm64__) || defined(__aarch64__)
+ if (DNBLogEnabledForAny(LOG_THREAD)) {
+ DNBLogThreaded(
+ "thread_set_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
+ "\n q0 = 0x%16.16llx%16.16llx"
+ "\n q1 = 0x%16.16llx%16.16llx"
+ "\n q2 = 0x%16.16llx%16.16llx"
+ "\n q3 = 0x%16.16llx%16.16llx"
+ "\n q4 = 0x%16.16llx%16.16llx"
+ "\n q5 = 0x%16.16llx%16.16llx"
+ "\n q6 = 0x%16.16llx%16.16llx"
+ "\n q7 = 0x%16.16llx%16.16llx"
+ "\n q8 = 0x%16.16llx%16.16llx"
+ "\n q9 = 0x%16.16llx%16.16llx"
+ "\n q10 = 0x%16.16llx%16.16llx"
+ "\n q11 = 0x%16.16llx%16.16llx"
+ "\n q12 = 0x%16.16llx%16.16llx"
+ "\n q13 = 0x%16.16llx%16.16llx"
+ "\n q14 = 0x%16.16llx%16.16llx"
+ "\n q15 = 0x%16.16llx%16.16llx"
+ "\n fpsr = 0x%8.8x"
+ "\n fpcr = 0x%8.8x\n\n",
+ m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret,
+ count, ((uint64_t *)&m_state.context.vfp.__v[0])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[0])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[1])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[1])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[2])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[2])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[3])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[3])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[4])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[4])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[5])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[5])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[6])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[6])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[7])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[7])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[8])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[8])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[9])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[9])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[10])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[10])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[11])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[11])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[12])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[12])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[13])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[13])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[14])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[14])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[15])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[15])[1],
+ m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
+ }
#else
- if (DNBLogEnabledForAny (LOG_THREAD))
- {
- uint32_t *r = &m_state.context.vfp.__r[0];
- DNBLogThreaded ("thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
- m_thread->MachPortNumber(),
- ARM_THREAD_STATE,
- ARM_THREAD_STATE_COUNT,
- kret,
- count);
- DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x s5=%8.8x s6=%8.8x s7=%8.8x",r[ 0],r[ 1],r[ 2],r[ 3],r[ 4],r[ 5],r[ 6],r[ 7]);
- DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x s13=%8.8x s14=%8.8x s15=%8.8x",r[ 8],r[ 9],r[10],r[11],r[12],r[13],r[14],r[15]);
- DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x s21=%8.8x s22=%8.8x s23=%8.8x",r[16],r[17],r[18],r[19],r[20],r[21],r[22],r[23]);
- DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x s29=%8.8x s30=%8.8x s31=%8.8x",r[24],r[25],r[26],r[27],r[28],r[29],r[30],r[31]);
- DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x s37=%8.8x s38=%8.8x s39=%8.8x",r[32],r[33],r[34],r[35],r[36],r[37],r[38],r[39]);
- DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x s45=%8.8x s46=%8.8x s47=%8.8x",r[40],r[41],r[42],r[43],r[44],r[45],r[46],r[47]);
- DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x s53=%8.8x s54=%8.8x s55=%8.8x",r[48],r[49],r[50],r[51],r[52],r[53],r[54],r[55]);
- DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",r[56],r[57],r[58],r[59],r[60],r[61],r[62],r[63],r[64]);
- }
-#endif
-
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-kern_return_t
-DNBArchMachARM::SetEXCState()
-{
- int set = e_regSetEXC;
- kern_return_t kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, ARM_EXCEPTION_STATE_COUNT);
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-kern_return_t
-DNBArchMachARM::SetDBGState(bool also_set_on_task)
-{
- int set = e_regSetDBG;
-#if defined (ARM_DEBUG_STATE32) && (defined (__arm64__) || defined (__aarch64__))
- kern_return_t kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_DEBUG_STATE32, (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
- if (also_set_on_task)
- {
- kern_return_t task_kret = ::task_set_state (m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE32, (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
- if (task_kret != KERN_SUCCESS)
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to set debug control register state: 0x%8.8x.", kret);
- }
+ if (DNBLogEnabledForAny(LOG_THREAD)) {
+ uint32_t *r = &m_state.context.vfp.__r[0];
+ DNBLogThreaded(
+ "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
+ m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
+ kret, count);
+ DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x "
+ "s5=%8.8x s6=%8.8x s7=%8.8x",
+ r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
+ DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x "
+ "s13=%8.8x s14=%8.8x s15=%8.8x",
+ r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
+ DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x "
+ "s21=%8.8x s22=%8.8x s23=%8.8x",
+ r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]);
+ DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x "
+ "s29=%8.8x s30=%8.8x s31=%8.8x",
+ r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]);
+ DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x "
+ "s37=%8.8x s38=%8.8x s39=%8.8x",
+ r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]);
+ DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x "
+ "s45=%8.8x s46=%8.8x s47=%8.8x",
+ r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]);
+ DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x "
+ "s53=%8.8x s54=%8.8x s55=%8.8x",
+ r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]);
+ DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x "
+ "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",
+ r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63],
+ r[64]);
+ }
+#endif
+
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+kern_return_t DNBArchMachARM::SetEXCState() {
+ int set = e_regSetEXC;
+ kern_return_t kret = ::thread_set_state(
+ m_thread->MachPortNumber(), ARM_EXCEPTION_STATE,
+ (thread_state_t)&m_state.context.exc, ARM_EXCEPTION_STATE_COUNT);
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+kern_return_t DNBArchMachARM::SetDBGState(bool also_set_on_task) {
+ int set = e_regSetDBG;
+#if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
+ kern_return_t kret =
+ ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32,
+ (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
+ if (also_set_on_task) {
+ kern_return_t task_kret = ::task_set_state(
+ m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE32,
+ (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
+ if (task_kret != KERN_SUCCESS)
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to "
+ "set debug control register state: "
+ "0x%8.8x.",
+ kret);
+ }
#else
- kern_return_t kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_DEBUG_STATE, (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
- if (also_set_on_task)
- {
- kern_return_t task_kret = ::task_set_state (m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE, (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
- if (task_kret != KERN_SUCCESS)
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to set debug control register state: 0x%8.8x.", kret);
- }
-#endif
-
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-void
-DNBArchMachARM::ThreadWillResume()
-{
- // Do we need to step this thread? If so, let the mach thread tell us so.
- if (m_thread->IsStepping())
- {
- // This is the primary thread, let the arch do anything it needs
- if (NumSupportedHardwareBreakpoints() > 0)
- {
- if (EnableHardwareSingleStep(true) != KERN_SUCCESS)
- {
- DNBLogThreaded("DNBArchMachARM::ThreadWillResume() failed to enable hardware single step");
- }
- }
- }
-
- // Disable the triggered watchpoint temporarily before we resume.
- // Plus, we try to enable hardware single step to execute past the instruction which triggered our watchpoint.
- if (m_watchpoint_did_occur)
- {
- if (m_watchpoint_hw_index >= 0)
- {
- kern_return_t kret = GetDBGState(false);
- if (kret == KERN_SUCCESS && !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) {
- // The watchpoint might have been disabled by the user. We don't need to do anything at all
- // to enable hardware single stepping.
- m_watchpoint_did_occur = false;
- m_watchpoint_hw_index = -1;
- return;
- }
-
- DisableHardwareWatchpoint(m_watchpoint_hw_index, false);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() DisableHardwareWatchpoint(%d) called",
- m_watchpoint_hw_index);
-
- // Enable hardware single step to move past the watchpoint-triggering instruction.
- m_watchpoint_resume_single_step_enabled = (EnableHardwareSingleStep(true) == KERN_SUCCESS);
-
- // If we are not able to enable single step to move past the watchpoint-triggering instruction,
- // at least we should reset the two watchpoint member variables so that the next time around
- // this callback function is invoked, the enclosing logical branch is skipped.
- if (!m_watchpoint_resume_single_step_enabled) {
- // Reset the two watchpoint member variables.
- m_watchpoint_did_occur = false;
- m_watchpoint_hw_index = -1;
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() failed to enable single step");
- }
- else
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() succeeded to enable single step");
- }
- }
-}
-
-bool
-DNBArchMachARM::ThreadDidStop()
-{
- bool success = true;
-
- m_state.InvalidateRegisterSetState (e_regSetALL);
-
- if (m_watchpoint_resume_single_step_enabled)
- {
- // Great! We now disable the hardware single step as well as re-enable the hardware watchpoint.
- // See also ThreadWillResume().
- if (EnableHardwareSingleStep(false) == KERN_SUCCESS)
- {
- if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0)
- {
- ReenableHardwareWatchpoint(m_watchpoint_hw_index);
- m_watchpoint_resume_single_step_enabled = false;
- m_watchpoint_did_occur = false;
- m_watchpoint_hw_index = -1;
- }
- else
- {
- DNBLogError("internal error detected: m_watchpoint_resume_step_enabled is true but (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) does not hold!");
- }
- }
- else
- {
- DNBLogError("internal error detected: m_watchpoint_resume_step_enabled is true but unable to disable single step!");
- }
- }
-
- // Are we stepping a single instruction?
- if (GetGPRState(true) == KERN_SUCCESS)
- {
- // We are single stepping, was this the primary thread?
- if (m_thread->IsStepping())
- {
- success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
- }
- else
- {
- // The MachThread will automatically restore the suspend count
- // in ThreadDidStop(), so we don't need to do anything here if
- // we weren't the primary thread the last time
- }
- }
- return success;
-}
-
-bool
-DNBArchMachARM::NotifyException(MachException::Data& exc)
-{
- switch (exc.exc_type)
- {
- default:
- break;
- case EXC_BREAKPOINT:
- if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG)
- {
- // The data break address is passed as exc_data[1].
- nub_addr_t addr = exc.exc_data[1];
- // Find the hardware index with the side effect of possibly massaging the
- // addr to return the starting address as seen from the debugger side.
- uint32_t hw_index = GetHardwareWatchpointHit(addr);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException watchpoint %d was hit on address 0x%llx", hw_index, (uint64_t) addr);
- const int num_watchpoints = NumSupportedHardwareWatchpoints ();
- for (int i = 0; i < num_watchpoints; i++)
- {
- if (LoHi[i] != 0
- && LoHi[i] == hw_index
- && LoHi[i] != i
- && GetWatchpointAddressByIndex (i) != INVALID_NUB_ADDRESS)
- {
- addr = GetWatchpointAddressByIndex (i);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException It is a linked watchpoint; rewritten to index %d addr 0x%llx", LoHi[i], (uint64_t) addr);
- }
- }
- if (hw_index != INVALID_NUB_HW_INDEX)
- {
- m_watchpoint_did_occur = true;
- m_watchpoint_hw_index = hw_index;
- exc.exc_data[1] = addr;
- // Piggyback the hw_index in the exc.data.
- exc.exc_data.push_back(hw_index);
- }
-
- return true;
- }
- break;
- }
- return false;
-}
-
-bool
-DNBArchMachARM::StepNotComplete ()
-{
- if (m_hw_single_chained_step_addr != INVALID_NUB_ADDRESS)
- {
- kern_return_t kret = KERN_INVALID_ARGUMENT;
- kret = GetGPRState(false);
- if (kret == KERN_SUCCESS)
- {
- if (m_state.context.gpr.__pc == m_hw_single_chained_step_addr)
- {
- DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8llx", (uint64_t) m_hw_single_chained_step_addr);
- return true;
- }
- }
+ kern_return_t kret =
+ ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE,
+ (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
+ if (also_set_on_task) {
+ kern_return_t task_kret = ::task_set_state(
+ m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE,
+ (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
+ if (task_kret != KERN_SUCCESS)
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to "
+ "set debug control register state: "
+ "0x%8.8x.",
+ kret);
+ }
+#endif
+
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+void DNBArchMachARM::ThreadWillResume() {
+ // Do we need to step this thread? If so, let the mach thread tell us so.
+ if (m_thread->IsStepping()) {
+ // This is the primary thread, let the arch do anything it needs
+ if (NumSupportedHardwareBreakpoints() > 0) {
+ if (EnableHardwareSingleStep(true) != KERN_SUCCESS) {
+ DNBLogThreaded("DNBArchMachARM::ThreadWillResume() failed to enable "
+ "hardware single step");
+ }
+ }
+ }
+
+ // Disable the triggered watchpoint temporarily before we resume.
+ // Plus, we try to enable hardware single step to execute past the instruction
+ // which triggered our watchpoint.
+ if (m_watchpoint_did_occur) {
+ if (m_watchpoint_hw_index >= 0) {
+ kern_return_t kret = GetDBGState(false);
+ if (kret == KERN_SUCCESS &&
+ !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) {
+ // The watchpoint might have been disabled by the user. We don't need
+ // to do anything at all
+ // to enable hardware single stepping.
+ m_watchpoint_did_occur = false;
+ m_watchpoint_hw_index = -1;
+ return;
+ }
+
+ DisableHardwareWatchpoint(m_watchpoint_hw_index, false);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
+ "DisableHardwareWatchpoint(%d) called",
+ m_watchpoint_hw_index);
+
+ // Enable hardware single step to move past the watchpoint-triggering
+ // instruction.
+ m_watchpoint_resume_single_step_enabled =
+ (EnableHardwareSingleStep(true) == KERN_SUCCESS);
+
+ // If we are not able to enable single step to move past the
+ // watchpoint-triggering instruction,
+ // at least we should reset the two watchpoint member variables so that
+ // the next time around
+ // this callback function is invoked, the enclosing logical branch is
+ // skipped.
+ if (!m_watchpoint_resume_single_step_enabled) {
+ // Reset the two watchpoint member variables.
+ m_watchpoint_did_occur = false;
+ m_watchpoint_hw_index = -1;
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchMachARM::ThreadWillResume() failed to enable single step");
+ } else
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
+ "succeeded to enable single step");
+ }
+ }
+}
+
+bool DNBArchMachARM::ThreadDidStop() {
+ bool success = true;
+
+ m_state.InvalidateRegisterSetState(e_regSetALL);
+
+ if (m_watchpoint_resume_single_step_enabled) {
+ // Great! We now disable the hardware single step as well as re-enable the
+ // hardware watchpoint.
+ // See also ThreadWillResume().
+ if (EnableHardwareSingleStep(false) == KERN_SUCCESS) {
+ if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) {
+ ReenableHardwareWatchpoint(m_watchpoint_hw_index);
+ m_watchpoint_resume_single_step_enabled = false;
+ m_watchpoint_did_occur = false;
+ m_watchpoint_hw_index = -1;
+ } else {
+ DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
+ "is true but (m_watchpoint_did_occur && "
+ "m_watchpoint_hw_index >= 0) does not hold!");
+ }
+ } else {
+ DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
+ "is true but unable to disable single step!");
+ }
+ }
+
+ // Are we stepping a single instruction?
+ if (GetGPRState(true) == KERN_SUCCESS) {
+ // We are single stepping, was this the primary thread?
+ if (m_thread->IsStepping()) {
+ success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
+ } else {
+ // The MachThread will automatically restore the suspend count
+ // in ThreadDidStop(), so we don't need to do anything here if
+ // we weren't the primary thread the last time
+ }
+ }
+ return success;
+}
+
+bool DNBArchMachARM::NotifyException(MachException::Data &exc) {
+ switch (exc.exc_type) {
+ default:
+ break;
+ case EXC_BREAKPOINT:
+ if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) {
+ // The data break address is passed as exc_data[1].
+ nub_addr_t addr = exc.exc_data[1];
+ // Find the hardware index with the side effect of possibly massaging the
+ // addr to return the starting address as seen from the debugger side.
+ uint32_t hw_index = GetHardwareWatchpointHit(addr);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
+ "watchpoint %d was hit on address "
+ "0x%llx",
+ hw_index, (uint64_t)addr);
+ const int num_watchpoints = NumSupportedHardwareWatchpoints();
+ for (int i = 0; i < num_watchpoints; i++) {
+ if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i &&
+ GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) {
+ addr = GetWatchpointAddressByIndex(i);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
+ "It is a linked watchpoint; "
+ "rewritten to index %d addr 0x%llx",
+ LoHi[i], (uint64_t)addr);
+ }
+ }
+ if (hw_index != INVALID_NUB_HW_INDEX) {
+ m_watchpoint_did_occur = true;
+ m_watchpoint_hw_index = hw_index;
+ exc.exc_data[1] = addr;
+ // Piggyback the hw_index in the exc.data.
+ exc.exc_data.push_back(hw_index);
+ }
+
+ return true;
+ }
+ break;
+ }
+ return false;
+}
+
+bool DNBArchMachARM::StepNotComplete() {
+ if (m_hw_single_chained_step_addr != INVALID_NUB_ADDRESS) {
+ kern_return_t kret = KERN_INVALID_ARGUMENT;
+ kret = GetGPRState(false);
+ if (kret == KERN_SUCCESS) {
+ if (m_state.context.gpr.__pc == m_hw_single_chained_step_addr) {
+ DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8llx",
+ (uint64_t)m_hw_single_chained_step_addr);
+ return true;
+ }
}
+ }
- m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
- return false;
+ m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
+ return false;
}
// Set the single step bit in the processor status register.
-kern_return_t
-DNBArchMachARM::EnableHardwareSingleStep (bool enable)
-{
- DNBError err;
- DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable);
-
- err = GetGPRState(false);
-
- if (err.Fail())
- {
- err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__);
- return err.Error();
- }
-
- err = GetDBGState(false);
-
- if (err.Fail())
- {
- err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__);
- return err.Error();
- }
+kern_return_t DNBArchMachARM::EnableHardwareSingleStep(bool enable) {
+ DNBError err;
+ DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable);
+
+ err = GetGPRState(false);
+
+ if (err.Fail()) {
+ err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__);
+ return err.Error();
+ }
+
+ err = GetDBGState(false);
+
+ if (err.Fail()) {
+ err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__);
+ return err.Error();
+ }
// The use of __arm64__ here is not ideal. If debugserver is running on
-// an armv8 device, regardless of whether it was built for arch arm or arch arm64,
+// an armv8 device, regardless of whether it was built for arch arm or arch
+// arm64,
// it needs to use the MDSCR_EL1 SS bit to single instruction step.
-#if defined (__arm64__) || defined (__aarch64__)
- if (enable)
- {
- DNBLogThreadedIf(LOG_STEP, "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", __FUNCTION__, (uint64_t) m_state.context.gpr.__pc);
- m_state.dbg.__mdscr_el1 |= 1; // Set bit 0 (single step, SS) in the MDSCR_EL1.
- }
- else
- {
- DNBLogThreadedIf(LOG_STEP, "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", __FUNCTION__, (uint64_t) m_state.context.gpr.__pc);
- m_state.dbg.__mdscr_el1 &= ~(1ULL); // Clear bit 0 (single step, SS) in the MDSCR_EL1.
- }
+#if defined(__arm64__) || defined(__aarch64__)
+ if (enable) {
+ DNBLogThreadedIf(LOG_STEP,
+ "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx",
+ __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
+ m_state.dbg.__mdscr_el1 |=
+ 1; // Set bit 0 (single step, SS) in the MDSCR_EL1.
+ } else {
+ DNBLogThreadedIf(LOG_STEP,
+ "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx",
+ __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
+ m_state.dbg.__mdscr_el1 &=
+ ~(1ULL); // Clear bit 0 (single step, SS) in the MDSCR_EL1.
+ }
#else
- const uint32_t i = 0;
- if (enable)
- {
- m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
-
- // Save our previous state
- m_dbg_save = m_state.dbg;
- // Set a breakpoint that will stop when the PC doesn't match the current one!
- m_state.dbg.__bvr[i] = m_state.context.gpr.__pc & 0xFFFFFFFCu; // Set the current PC as the breakpoint address
- m_state.dbg.__bcr[i] = BCR_M_IMVA_MISMATCH | // Stop on address mismatch
- S_USER | // Stop only in user mode
- BCR_ENABLE; // Enable this breakpoint
- if (m_state.context.gpr.__cpsr & 0x20)
- {
- // Thumb breakpoint
- if (m_state.context.gpr.__pc & 2)
- m_state.dbg.__bcr[i] |= BAS_IMVA_2_3;
- else
- m_state.dbg.__bcr[i] |= BAS_IMVA_0_1;
-
- uint16_t opcode;
- if (sizeof(opcode) == m_thread->Process()->Task().ReadMemory(m_state.context.gpr.__pc, sizeof(opcode), &opcode))
- {
- if (IsThumb32Opcode(opcode))
- {
- // 32 bit thumb opcode...
- if (m_state.context.gpr.__pc & 2)
- {
- // We can't take care of a 32 bit thumb instruction single step
- // with just IVA mismatching. We will need to chain an extra
- // hardware single step in order to complete this single step...
- m_hw_single_chained_step_addr = m_state.context.gpr.__pc + 2;
- }
- else
- {
- // Extend the number of bits to ignore for the mismatch
- m_state.dbg.__bcr[i] |= BAS_IMVA_ALL;
- }
- }
- }
- }
- else
- {
- // ARM breakpoint
- m_state.dbg.__bcr[i] |= BAS_IMVA_ALL; // Stop when any address bits change
- }
-
- DNBLogThreadedIf(LOG_STEP, "%s: BVR%u=0x%8.8x BCR%u=0x%8.8x", __FUNCTION__, i, m_state.dbg.__bvr[i], i, m_state.dbg.__bcr[i]);
+ const uint32_t i = 0;
+ if (enable) {
+ m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
- for (uint32_t j=i+1; j<16; ++j)
- {
- // Disable all others
- m_state.dbg.__bvr[j] = 0;
- m_state.dbg.__bcr[j] = 0;
- }
- }
- else
- {
- // Just restore the state we had before we did single stepping
- m_state.dbg = m_dbg_save;
- }
+ // Save our previous state
+ m_dbg_save = m_state.dbg;
+ // Set a breakpoint that will stop when the PC doesn't match the current
+ // one!
+ m_state.dbg.__bvr[i] =
+ m_state.context.gpr.__pc &
+ 0xFFFFFFFCu; // Set the current PC as the breakpoint address
+ m_state.dbg.__bcr[i] = BCR_M_IMVA_MISMATCH | // Stop on address mismatch
+ S_USER | // Stop only in user mode
+ BCR_ENABLE; // Enable this breakpoint
+ if (m_state.context.gpr.__cpsr & 0x20) {
+ // Thumb breakpoint
+ if (m_state.context.gpr.__pc & 2)
+ m_state.dbg.__bcr[i] |= BAS_IMVA_2_3;
+ else
+ m_state.dbg.__bcr[i] |= BAS_IMVA_0_1;
+
+ uint16_t opcode;
+ if (sizeof(opcode) ==
+ m_thread->Process()->Task().ReadMemory(m_state.context.gpr.__pc,
+ sizeof(opcode), &opcode)) {
+ if (IsThumb32Opcode(opcode)) {
+ // 32 bit thumb opcode...
+ if (m_state.context.gpr.__pc & 2) {
+ // We can't take care of a 32 bit thumb instruction single step
+ // with just IVA mismatching. We will need to chain an extra
+ // hardware single step in order to complete this single step...
+ m_hw_single_chained_step_addr = m_state.context.gpr.__pc + 2;
+ } else {
+ // Extend the number of bits to ignore for the mismatch
+ m_state.dbg.__bcr[i] |= BAS_IMVA_ALL;
+ }
+ }
+ }
+ } else {
+ // ARM breakpoint
+ m_state.dbg.__bcr[i] |= BAS_IMVA_ALL; // Stop when any address bits change
+ }
+
+ DNBLogThreadedIf(LOG_STEP, "%s: BVR%u=0x%8.8x BCR%u=0x%8.8x", __FUNCTION__,
+ i, m_state.dbg.__bvr[i], i, m_state.dbg.__bcr[i]);
+
+ for (uint32_t j = i + 1; j < 16; ++j) {
+ // Disable all others
+ m_state.dbg.__bvr[j] = 0;
+ m_state.dbg.__bcr[j] = 0;
+ }
+ } else {
+ // Just restore the state we had before we did single stepping
+ m_state.dbg = m_dbg_save;
+ }
#endif
- return SetDBGState(false);
+ return SetDBGState(false);
}
// return 1 if bit "BIT" is set in "value"
-static inline uint32_t bit(uint32_t value, uint32_t bit)
-{
- return (value >> bit) & 1u;
+static inline uint32_t bit(uint32_t value, uint32_t bit) {
+ return (value >> bit) & 1u;
}
// return the bitfield "value[msbit:lsbit]".
-static inline uint32_t bits(uint32_t value, uint32_t msbit, uint32_t lsbit)
-{
- assert(msbit >= lsbit);
- uint32_t shift_left = sizeof(value) * 8 - 1 - msbit;
- value <<= shift_left; // shift anything above the msbit off of the unsigned edge
- value >>= (shift_left + lsbit); // shift it back again down to the lsbit (including undoing any shift from above)
- return value; // return our result
-}
-
-bool
-DNBArchMachARM::ConditionPassed(uint8_t condition, uint32_t cpsr)
-{
- uint32_t cpsr_n = bit(cpsr, 31); // Negative condition code flag
- uint32_t cpsr_z = bit(cpsr, 30); // Zero condition code flag
- uint32_t cpsr_c = bit(cpsr, 29); // Carry condition code flag
- uint32_t cpsr_v = bit(cpsr, 28); // Overflow condition code flag
-
- switch (condition) {
- case COND_EQ: // (0x0)
- if (cpsr_z == 1) return true;
- break;
- case COND_NE: // (0x1)
- if (cpsr_z == 0) return true;
- break;
- case COND_CS: // (0x2)
- if (cpsr_c == 1) return true;
- break;
- case COND_CC: // (0x3)
- if (cpsr_c == 0) return true;
- break;
- case COND_MI: // (0x4)
- if (cpsr_n == 1) return true;
- break;
- case COND_PL: // (0x5)
- if (cpsr_n == 0) return true;
- break;
- case COND_VS: // (0x6)
- if (cpsr_v == 1) return true;
- break;
- case COND_VC: // (0x7)
- if (cpsr_v == 0) return true;
- break;
- case COND_HI: // (0x8)
- if ((cpsr_c == 1) && (cpsr_z == 0)) return true;
- break;
- case COND_LS: // (0x9)
- if ((cpsr_c == 0) || (cpsr_z == 1)) return true;
- break;
- case COND_GE: // (0xA)
- if (cpsr_n == cpsr_v) return true;
- break;
- case COND_LT: // (0xB)
- if (cpsr_n != cpsr_v) return true;
- break;
- case COND_GT: // (0xC)
- if ((cpsr_z == 0) && (cpsr_n == cpsr_v)) return true;
- break;
- case COND_LE: // (0xD)
- if ((cpsr_z == 1) || (cpsr_n != cpsr_v)) return true;
- break;
- default:
- return true;
- break;
- }
-
- return false;
-}
-
-uint32_t
-DNBArchMachARM::NumSupportedHardwareBreakpoints()
-{
- // Set the init value to something that will let us know that we need to
- // autodetect how many breakpoints are supported dynamically...
- static uint32_t g_num_supported_hw_breakpoints = UINT_MAX;
- if (g_num_supported_hw_breakpoints == UINT_MAX)
- {
- // Set this to zero in case we can't tell if there are any HW breakpoints
- g_num_supported_hw_breakpoints = 0;
+static inline uint32_t bits(uint32_t value, uint32_t msbit, uint32_t lsbit) {
+ assert(msbit >= lsbit);
+ uint32_t shift_left = sizeof(value) * 8 - 1 - msbit;
+ value <<=
+ shift_left; // shift anything above the msbit off of the unsigned edge
+ value >>= (shift_left + lsbit); // shift it back again down to the lsbit
+ // (including undoing any shift from above)
+ return value; // return our result
+}
+
+bool DNBArchMachARM::ConditionPassed(uint8_t condition, uint32_t cpsr) {
+ uint32_t cpsr_n = bit(cpsr, 31); // Negative condition code flag
+ uint32_t cpsr_z = bit(cpsr, 30); // Zero condition code flag
+ uint32_t cpsr_c = bit(cpsr, 29); // Carry condition code flag
+ uint32_t cpsr_v = bit(cpsr, 28); // Overflow condition code flag
+
+ switch (condition) {
+ case COND_EQ: // (0x0)
+ if (cpsr_z == 1)
+ return true;
+ break;
+ case COND_NE: // (0x1)
+ if (cpsr_z == 0)
+ return true;
+ break;
+ case COND_CS: // (0x2)
+ if (cpsr_c == 1)
+ return true;
+ break;
+ case COND_CC: // (0x3)
+ if (cpsr_c == 0)
+ return true;
+ break;
+ case COND_MI: // (0x4)
+ if (cpsr_n == 1)
+ return true;
+ break;
+ case COND_PL: // (0x5)
+ if (cpsr_n == 0)
+ return true;
+ break;
+ case COND_VS: // (0x6)
+ if (cpsr_v == 1)
+ return true;
+ break;
+ case COND_VC: // (0x7)
+ if (cpsr_v == 0)
+ return true;
+ break;
+ case COND_HI: // (0x8)
+ if ((cpsr_c == 1) && (cpsr_z == 0))
+ return true;
+ break;
+ case COND_LS: // (0x9)
+ if ((cpsr_c == 0) || (cpsr_z == 1))
+ return true;
+ break;
+ case COND_GE: // (0xA)
+ if (cpsr_n == cpsr_v)
+ return true;
+ break;
+ case COND_LT: // (0xB)
+ if (cpsr_n != cpsr_v)
+ return true;
+ break;
+ case COND_GT: // (0xC)
+ if ((cpsr_z == 0) && (cpsr_n == cpsr_v))
+ return true;
+ break;
+ case COND_LE: // (0xD)
+ if ((cpsr_z == 1) || (cpsr_n != cpsr_v))
+ return true;
+ break;
+ default:
+ return true;
+ break;
+ }
+
+ return false;
+}
+
+uint32_t DNBArchMachARM::NumSupportedHardwareBreakpoints() {
+ // Set the init value to something that will let us know that we need to
+ // autodetect how many breakpoints are supported dynamically...
+ static uint32_t g_num_supported_hw_breakpoints = UINT_MAX;
+ if (g_num_supported_hw_breakpoints == UINT_MAX) {
+ // Set this to zero in case we can't tell if there are any HW breakpoints
+ g_num_supported_hw_breakpoints = 0;
+
+ size_t len;
+ uint32_t n = 0;
+ len = sizeof(n);
+ if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0) {
+ g_num_supported_hw_breakpoints = n;
+ DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n);
+ } else {
+#if !defined(__arm64__) && !defined(__aarch64__)
+ // Read the DBGDIDR to get the number of available hardware breakpoints
+ // However, in some of our current armv7 processors, hardware
+ // breakpoints/watchpoints were not properly connected. So detect those
+ // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
+ // field to distinguish CPU architectures. This is a hack until we can
+ // get <rdar://problem/6372672> fixed, at which point we will switch to
+ // using a different sysctl string that will tell us how many BRPs
+ // are available to us directly without having to read DBGDIDR.
+ uint32_t register_DBGDIDR;
+
+ asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
+ uint32_t numBRPs = bits(register_DBGDIDR, 27, 24);
+ // Zero is reserved for the BRP count, so don't increment it if it is zero
+ if (numBRPs > 0)
+ numBRPs++;
+ DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number BRP pairs = %u)",
+ register_DBGDIDR, numBRPs);
+
+ if (numBRPs > 0) {
+ uint32_t cpusubtype;
+ len = sizeof(cpusubtype);
+ // TODO: remove this hack and change to using hw.optional.xx when
+ // implmented
+ if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) {
+ DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=%d", cpusubtype);
+ if (cpusubtype == CPU_SUBTYPE_ARM_V7)
+ DNBLogThreadedIf(LOG_THREAD, "Hardware breakpoints disabled for "
+ "armv7 (rdar://problem/6372672)");
+ else
+ g_num_supported_hw_breakpoints = numBRPs;
+ }
+ }
+#endif
+ }
+ }
+ return g_num_supported_hw_breakpoints;
+}
+
+uint32_t DNBArchMachARM::NumSupportedHardwareWatchpoints() {
+ // Set the init value to something that will let us know that we need to
+ // autodetect how many watchpoints are supported dynamically...
+ static uint32_t g_num_supported_hw_watchpoints = UINT_MAX;
+ if (g_num_supported_hw_watchpoints == UINT_MAX) {
+ // Set this to zero in case we can't tell if there are any HW breakpoints
+ g_num_supported_hw_watchpoints = 0;
+
+ size_t len;
+ uint32_t n = 0;
+ len = sizeof(n);
+ if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
+ g_num_supported_hw_watchpoints = n;
+ DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n);
+ } else {
+#if !defined(__arm64__) && !defined(__aarch64__)
+ // Read the DBGDIDR to get the number of available hardware breakpoints
+ // However, in some of our current armv7 processors, hardware
+ // breakpoints/watchpoints were not properly connected. So detect those
+ // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
+ // field to distinguish CPU architectures. This is a hack until we can
+ // get <rdar://problem/6372672> fixed, at which point we will switch to
+ // using a different sysctl string that will tell us how many WRPs
+ // are available to us directly without having to read DBGDIDR.
+
+ uint32_t register_DBGDIDR;
+ asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
+ uint32_t numWRPs = bits(register_DBGDIDR, 31, 28) + 1;
+ DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number WRP pairs = %u)",
+ register_DBGDIDR, numWRPs);
+ if (numWRPs > 0) {
+ uint32_t cpusubtype;
size_t len;
- uint32_t n = 0;
- len = sizeof (n);
- if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0)
- {
- g_num_supported_hw_breakpoints = n;
- DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n);
- }
- else
- {
-#if !defined (__arm64__) && !defined (__aarch64__)
- // Read the DBGDIDR to get the number of available hardware breakpoints
- // However, in some of our current armv7 processors, hardware
- // breakpoints/watchpoints were not properly connected. So detect those
- // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
- // field to distinguish CPU architectures. This is a hack until we can
- // get <rdar://problem/6372672> fixed, at which point we will switch to
- // using a different sysctl string that will tell us how many BRPs
- // are available to us directly without having to read DBGDIDR.
- uint32_t register_DBGDIDR;
-
- asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
- uint32_t numBRPs = bits(register_DBGDIDR, 27, 24);
- // Zero is reserved for the BRP count, so don't increment it if it is zero
- if (numBRPs > 0)
- numBRPs++;
- DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number BRP pairs = %u)", register_DBGDIDR, numBRPs);
-
- if (numBRPs > 0)
- {
- uint32_t cpusubtype;
- len = sizeof(cpusubtype);
- // TODO: remove this hack and change to using hw.optional.xx when implmented
- if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0)
- {
- DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=%d", cpusubtype);
- if (cpusubtype == CPU_SUBTYPE_ARM_V7)
- DNBLogThreadedIf(LOG_THREAD, "Hardware breakpoints disabled for armv7 (rdar://problem/6372672)");
- else
- g_num_supported_hw_breakpoints = numBRPs;
- }
- }
-#endif
- }
- }
- return g_num_supported_hw_breakpoints;
-}
-
+ len = sizeof(cpusubtype);
+ // TODO: remove this hack and change to using hw.optional.xx when
+ // implmented
+ if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) {
+ DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=0x%d", cpusubtype);
-uint32_t
-DNBArchMachARM::NumSupportedHardwareWatchpoints()
-{
- // Set the init value to something that will let us know that we need to
- // autodetect how many watchpoints are supported dynamically...
- static uint32_t g_num_supported_hw_watchpoints = UINT_MAX;
- if (g_num_supported_hw_watchpoints == UINT_MAX)
- {
- // Set this to zero in case we can't tell if there are any HW breakpoints
- g_num_supported_hw_watchpoints = 0;
-
-
- size_t len;
- uint32_t n = 0;
- len = sizeof (n);
- if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0)
- {
- g_num_supported_hw_watchpoints = n;
- DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n);
+ if (cpusubtype == CPU_SUBTYPE_ARM_V7)
+ DNBLogThreadedIf(LOG_THREAD, "Hardware watchpoints disabled for "
+ "armv7 (rdar://problem/6372672)");
+ else
+ g_num_supported_hw_watchpoints = numWRPs;
}
- else
- {
-#if !defined (__arm64__) && !defined (__aarch64__)
- // Read the DBGDIDR to get the number of available hardware breakpoints
- // However, in some of our current armv7 processors, hardware
- // breakpoints/watchpoints were not properly connected. So detect those
- // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
- // field to distinguish CPU architectures. This is a hack until we can
- // get <rdar://problem/6372672> fixed, at which point we will switch to
- // using a different sysctl string that will tell us how many WRPs
- // are available to us directly without having to read DBGDIDR.
-
- uint32_t register_DBGDIDR;
- asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
- uint32_t numWRPs = bits(register_DBGDIDR, 31, 28) + 1;
- DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number WRP pairs = %u)", register_DBGDIDR, numWRPs);
-
- if (numWRPs > 0)
- {
- uint32_t cpusubtype;
- size_t len;
- len = sizeof(cpusubtype);
- // TODO: remove this hack and change to using hw.optional.xx when implmented
- if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0)
- {
- DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=0x%d", cpusubtype);
-
- if (cpusubtype == CPU_SUBTYPE_ARM_V7)
- DNBLogThreadedIf(LOG_THREAD, "Hardware watchpoints disabled for armv7 (rdar://problem/6372672)");
- else
- g_num_supported_hw_watchpoints = numWRPs;
- }
- }
+ }
#endif
- }
}
- return g_num_supported_hw_watchpoints;
+ }
+ return g_num_supported_hw_watchpoints;
}
-
-uint32_t
-DNBArchMachARM::EnableHardwareBreakpoint (nub_addr_t addr, nub_size_t size)
-{
- // Make sure our address isn't bogus
- if (addr & 1)
- return INVALID_NUB_HW_INDEX;
-
- kern_return_t kret = GetDBGState(false);
-
- if (kret == KERN_SUCCESS)
- {
- const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
- uint32_t i;
- for (i=0; i<num_hw_breakpoints; ++i)
- {
- if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0)
- break; // We found an available hw breakpoint slot (in i)
- }
-
- // See if we found an available hw breakpoint slot above
- if (i < num_hw_breakpoints)
- {
- // Make sure bits 1:0 are clear in our address
- m_state.dbg.__bvr[i] = addr & ~((nub_addr_t)3);
-
- if (size == 2 || addr & 2)
- {
- uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
-
- // We have a thumb breakpoint
- // We have an ARM breakpoint
- m_state.dbg.__bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
- byte_addr_select | // Set the correct byte address select so we only trigger on the correct opcode
- S_USER | // Which modes should this breakpoint stop in?
- BCR_ENABLE; // Enable this hardware breakpoint
- DNBLogThreadedIf (LOG_BREAKPOINTS, "DNBArchMachARM::EnableHardwareBreakpoint( addr = 0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (Thumb)",
- (uint64_t)addr,
- (uint64_t)size,
- i,
- i,
- m_state.dbg.__bvr[i],
- m_state.dbg.__bcr[i]);
- }
- else if (size == 4)
- {
- // We have an ARM breakpoint
- m_state.dbg.__bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
- BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
- S_USER | // Which modes should this breakpoint stop in?
- BCR_ENABLE; // Enable this hardware breakpoint
- DNBLogThreadedIf (LOG_BREAKPOINTS, "DNBArchMachARM::EnableHardwareBreakpoint( addr = 0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (ARM)",
- (uint64_t)addr,
- (uint64_t)size,
- i,
- i,
- m_state.dbg.__bvr[i],
- m_state.dbg.__bcr[i]);
- }
-
- kret = SetDBGState(false);
- DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::EnableHardwareBreakpoint() SetDBGState() => 0x%8.8x.", kret);
-
- if (kret == KERN_SUCCESS)
- return i;
- }
- else
- {
- DNBLogThreadedIf (LOG_BREAKPOINTS, "DNBArchMachARM::EnableHardwareBreakpoint(addr = 0x%8.8llx, size = %llu) => all hardware breakpoint resources are being used.", (uint64_t)addr, (uint64_t)size);
- }
- }
-
+uint32_t DNBArchMachARM::EnableHardwareBreakpoint(nub_addr_t addr,
+ nub_size_t size) {
+ // Make sure our address isn't bogus
+ if (addr & 1)
return INVALID_NUB_HW_INDEX;
-}
-bool
-DNBArchMachARM::DisableHardwareBreakpoint (uint32_t hw_index)
-{
- kern_return_t kret = GetDBGState(false);
-
- const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
- if (kret == KERN_SUCCESS)
- {
- if (hw_index < num_hw_points)
- {
- m_state.dbg.__bcr[hw_index] = 0;
- DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::SetHardwareBreakpoint( %u ) - BVR%u = 0x%8.8x BCR%u = 0x%8.8x",
- hw_index,
- hw_index,
- m_state.dbg.__bvr[hw_index],
- hw_index,
- m_state.dbg.__bcr[hw_index]);
+ kern_return_t kret = GetDBGState(false);
- kret = SetDBGState(false);
+ if (kret == KERN_SUCCESS) {
+ const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
+ uint32_t i;
+ for (i = 0; i < num_hw_breakpoints; ++i) {
+ if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0)
+ break; // We found an available hw breakpoint slot (in i)
+ }
+
+ // See if we found an available hw breakpoint slot above
+ if (i < num_hw_breakpoints) {
+ // Make sure bits 1:0 are clear in our address
+ m_state.dbg.__bvr[i] = addr & ~((nub_addr_t)3);
+
+ if (size == 2 || addr & 2) {
+ uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
+
+ // We have a thumb breakpoint
+ // We have an ARM breakpoint
+ m_state.dbg.__bcr[i] =
+ BCR_M_IMVA_MATCH | // Stop on address mismatch
+ byte_addr_select | // Set the correct byte address select so we only
+ // trigger on the correct opcode
+ S_USER | // Which modes should this breakpoint stop in?
+ BCR_ENABLE; // Enable this hardware breakpoint
+ DNBLogThreadedIf(LOG_BREAKPOINTS,
+ "DNBArchMachARM::EnableHardwareBreakpoint( addr = "
+ "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / "
+ "0x%8.8x (Thumb)",
+ (uint64_t)addr, (uint64_t)size, i, i,
+ m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]);
+ } else if (size == 4) {
+ // We have an ARM breakpoint
+ m_state.dbg.__bcr[i] =
+ BCR_M_IMVA_MATCH | // Stop on address mismatch
+ BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
+ S_USER | // Which modes should this breakpoint stop in?
+ BCR_ENABLE; // Enable this hardware breakpoint
+ DNBLogThreadedIf(LOG_BREAKPOINTS,
+ "DNBArchMachARM::EnableHardwareBreakpoint( addr = "
+ "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / "
+ "0x%8.8x (ARM)",
+ (uint64_t)addr, (uint64_t)size, i, i,
+ m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]);
+ }
+
+ kret = SetDBGState(false);
+ DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::"
+ "EnableHardwareBreakpoint() "
+ "SetDBGState() => 0x%8.8x.",
+ kret);
+
+ if (kret == KERN_SUCCESS)
+ return i;
+ } else {
+ DNBLogThreadedIf(LOG_BREAKPOINTS,
+ "DNBArchMachARM::EnableHardwareBreakpoint(addr = "
+ "0x%8.8llx, size = %llu) => all hardware breakpoint "
+ "resources are being used.",
+ (uint64_t)addr, (uint64_t)size);
+ }
+ }
+
+ return INVALID_NUB_HW_INDEX;
+}
+
+bool DNBArchMachARM::DisableHardwareBreakpoint(uint32_t hw_index) {
+ kern_return_t kret = GetDBGState(false);
+
+ const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
+ if (kret == KERN_SUCCESS) {
+ if (hw_index < num_hw_points) {
+ m_state.dbg.__bcr[hw_index] = 0;
+ DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::SetHardwareBreakpoint("
+ " %u ) - BVR%u = 0x%8.8x BCR%u = "
+ "0x%8.8x",
+ hw_index, hw_index, m_state.dbg.__bvr[hw_index],
+ hw_index, m_state.dbg.__bcr[hw_index]);
- if (kret == KERN_SUCCESS)
- return true;
- }
+ kret = SetDBGState(false);
+
+ if (kret == KERN_SUCCESS)
+ return true;
}
- return false;
+ }
+ return false;
}
// ARM v7 watchpoints may be either word-size or double-word-size.
@@ -1071,1092 +1080,1115 @@ DNBArchMachARM::DisableHardwareBreakpoin
// armv8 device, armv7 processes can watch dwords. But on a genuine armv7
// device I tried, only word watchpoints are supported.
-#if defined (__arm64__) || defined (__aarch64__)
+#if defined(__arm64__) || defined(__aarch64__)
#define WATCHPOINTS_ARE_DWORD 1
#else
#undef WATCHPOINTS_ARE_DWORD
#endif
-uint32_t
-DNBArchMachARM::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task)
-{
-
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint(addr = 0x%8.8llx, size = %zu, read = %u, write = %u)", (uint64_t)addr, size, read, write);
-
- const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
-
- // Can't watch zero bytes
- if (size == 0)
- return INVALID_NUB_HW_INDEX;
-
- // We must watch for either read or write
- if (read == false && write == false)
- return INVALID_NUB_HW_INDEX;
-
- // Otherwise, can't watch more than 8 bytes per WVR/WCR pair
- if (size > 8)
- return INVALID_NUB_HW_INDEX;
-
- // Treat arm watchpoints as having an 8-byte alignment requirement. You can put a watchpoint on a 4-byte
- // offset address but you can only watch 4 bytes with that watchpoint.
-
- // arm watchpoints on an 8-byte (double word) aligned addr can watch any bytes in that
- // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 3rd byte, etc, or any
- // combination therein by setting the bits in the BAS [12:5] (Byte Address Select) field of
- // the DBGWCRn_EL1 reg for the watchpoint.
-
- // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to monitor a larger region
- // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield then selects a larger
- // range of bytes, instead of individual bytes. See the ARMv8 Debug Architecture manual for details.
- // This implementation does not currently use the MASK bits; the largest single region watched by a single
- // watchpoint right now is 8-bytes.
-
-#if defined (WATCHPOINTS_ARE_DWORD)
- nub_addr_t aligned_wp_address = addr & ~0x7;
- uint32_t addr_dword_offset = addr & 0x7;
- const int max_watchpoint_size = 8;
-#else
- nub_addr_t aligned_wp_address = addr & ~0x3;
- uint32_t addr_dword_offset = addr & 0x3;
- const int max_watchpoint_size = 4;
-#endif
-
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint aligned_wp_address is 0x%llx and addr_dword_offset is 0x%x", (uint64_t)aligned_wp_address, addr_dword_offset);
-
- // Do we need to split up this logical watchpoint into two hardware watchpoint
- // registers?
- // e.g. a watchpoint of length 4 on address 6. We need do this with
- // one watchpoint on address 0 with bytes 6 & 7 being monitored
- // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored
-
- if (addr_dword_offset + size > max_watchpoint_size)
- {
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint(addr = 0x%8.8llx, size = %zu) needs two hardware watchpoints slots to monitor", (uint64_t)addr, size);
- int low_watchpoint_size = max_watchpoint_size - addr_dword_offset;
- int high_watchpoint_size = addr_dword_offset + size - max_watchpoint_size;
-
- uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, write, also_set_on_task);
- if (lo == INVALID_NUB_HW_INDEX)
- return INVALID_NUB_HW_INDEX;
- uint32_t hi = EnableHardwareWatchpoint (aligned_wp_address + max_watchpoint_size, high_watchpoint_size, read, write, also_set_on_task);
- if (hi == INVALID_NUB_HW_INDEX)
- {
- DisableHardwareWatchpoint (lo, also_set_on_task);
- return INVALID_NUB_HW_INDEX;
- }
- // Tag this lo->hi mapping in our database.
- LoHi[lo] = hi;
- return lo;
- }
-
- // At this point
- // 1 aligned_wp_address is the requested address rounded down to 8-byte alignment
- // 2 addr_dword_offset is the offset into that double word (8-byte) region that we are watching
- // 3 size is the number of bytes within that 8-byte region that we are watching
-
- // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the above.
- // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, etc, up to 0b11111111 for 8.
- // then we shift those bits left by the offset into this dword that we are interested in.
- // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 0b11110000.
- uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset;
-
- // Read the debug state
- kern_return_t kret = GetDBGState(true);
-
- if (kret == KERN_SUCCESS)
- {
- // Check to make sure we have the needed hardware support
- uint32_t i = 0;
-
- for (i=0; i<num_hw_watchpoints; ++i)
- {
- if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0)
- break; // We found an available hw watchpoint slot (in i)
- }
+uint32_t DNBArchMachARM::EnableHardwareWatchpoint(nub_addr_t addr,
+ nub_size_t size, bool read,
+ bool write,
+ bool also_set_on_task) {
+
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint("
+ "addr = 0x%8.8llx, size = %zu, read = %u, "
+ "write = %u)",
+ (uint64_t)addr, size, read, write);
- // See if we found an available hw watchpoint slot above
- if (i < num_hw_watchpoints)
- {
- //DumpDBGState(m_state.dbg);
-
- // Clear any previous LoHi joined-watchpoint that may have been in use
- LoHi[i] = 0;
-
- // shift our Byte Address Select bits up to the correct bit range for the DBGWCRn_EL1
- byte_address_select = byte_address_select << 5;
-
- // Make sure bits 1:0 are clear in our address
- m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address)
- m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow the DVA that we will watch
- S_USER | // Stop only in user mode
- (read ? WCR_LOAD : 0) | // Stop on read access?
- (write ? WCR_STORE : 0) | // Stop on write access?
- WCR_ENABLE; // Enable this watchpoint;
-
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint() adding watchpoint on address 0x%llx with control register value 0x%x", (uint64_t) m_state.dbg.__wvr[i], (uint32_t) m_state.dbg.__wcr[i]);
-
- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us automatically, don't need to do it here.
+ const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
- kret = SetDBGState(also_set_on_task);
- //DumpDBGState(m_state.dbg);
+ // Can't watch zero bytes
+ if (size == 0)
+ return INVALID_NUB_HW_INDEX;
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret);
+ // We must watch for either read or write
+ if (read == false && write == false)
+ return INVALID_NUB_HW_INDEX;
- if (kret == KERN_SUCCESS)
- return i;
- }
- else
- {
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
- }
- }
+ // Otherwise, can't watch more than 8 bytes per WVR/WCR pair
+ if (size > 8)
return INVALID_NUB_HW_INDEX;
-}
-bool
-DNBArchMachARM::ReenableHardwareWatchpoint (uint32_t hw_index)
-{
- // If this logical watchpoint # is actually implemented using
- // two hardware watchpoint registers, re-enable both of them.
+// Treat arm watchpoints as having an 8-byte alignment requirement. You can put
+// a watchpoint on a 4-byte
+// offset address but you can only watch 4 bytes with that watchpoint.
+
+// arm watchpoints on an 8-byte (double word) aligned addr can watch any bytes
+// in that
+// 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 3rd
+// byte, etc, or any
+// combination therein by setting the bits in the BAS [12:5] (Byte Address
+// Select) field of
+// the DBGWCRn_EL1 reg for the watchpoint.
+
+// If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to
+// monitor a larger region
+// of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield
+// then selects a larger
+// range of bytes, instead of individual bytes. See the ARMv8 Debug
+// Architecture manual for details.
+// This implementation does not currently use the MASK bits; the largest single
+// region watched by a single
+// watchpoint right now is 8-bytes.
+
+#if defined(WATCHPOINTS_ARE_DWORD)
+ nub_addr_t aligned_wp_address = addr & ~0x7;
+ uint32_t addr_dword_offset = addr & 0x7;
+ const int max_watchpoint_size = 8;
+#else
+ nub_addr_t aligned_wp_address = addr & ~0x3;
+ uint32_t addr_dword_offset = addr & 0x3;
+ const int max_watchpoint_size = 4;
+#endif
+
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint "
+ "aligned_wp_address is 0x%llx and "
+ "addr_dword_offset is 0x%x",
+ (uint64_t)aligned_wp_address, addr_dword_offset);
+
+ // Do we need to split up this logical watchpoint into two hardware watchpoint
+ // registers?
+ // e.g. a watchpoint of length 4 on address 6. We need do this with
+ // one watchpoint on address 0 with bytes 6 & 7 being monitored
+ // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored
+
+ if (addr_dword_offset + size > max_watchpoint_size) {
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
+ "EnableHardwareWatchpoint(addr = "
+ "0x%8.8llx, size = %zu) needs two "
+ "hardware watchpoints slots to monitor",
+ (uint64_t)addr, size);
+ int low_watchpoint_size = max_watchpoint_size - addr_dword_offset;
+ int high_watchpoint_size = addr_dword_offset + size - max_watchpoint_size;
+
+ uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read,
+ write, also_set_on_task);
+ if (lo == INVALID_NUB_HW_INDEX)
+ return INVALID_NUB_HW_INDEX;
+ uint32_t hi = EnableHardwareWatchpoint(
+ aligned_wp_address + max_watchpoint_size, high_watchpoint_size, read,
+ write, also_set_on_task);
+ if (hi == INVALID_NUB_HW_INDEX) {
+ DisableHardwareWatchpoint(lo, also_set_on_task);
+ return INVALID_NUB_HW_INDEX;
+ }
+ // Tag this lo->hi mapping in our database.
+ LoHi[lo] = hi;
+ return lo;
+ }
+
+ // At this point
+ // 1 aligned_wp_address is the requested address rounded down to 8-byte
+ // alignment
+ // 2 addr_dword_offset is the offset into that double word (8-byte) region
+ // that we are watching
+ // 3 size is the number of bytes within that 8-byte region that we are
+ // watching
+
+ // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the
+ // above.
+ // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4,
+ // etc, up to 0b11111111 for 8.
+ // then we shift those bits left by the offset into this dword that we are
+ // interested in.
+ // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of
+ // 0b11110000.
+ uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset;
- if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index])
- {
- return ReenableHardwareWatchpoint_helper (hw_index) && ReenableHardwareWatchpoint_helper (LoHi[hw_index]);
- }
- else
- {
- return ReenableHardwareWatchpoint_helper (hw_index);
- }
-}
+ // Read the debug state
+ kern_return_t kret = GetDBGState(true);
+
+ if (kret == KERN_SUCCESS) {
+ // Check to make sure we have the needed hardware support
+ uint32_t i = 0;
-bool
-DNBArchMachARM::ReenableHardwareWatchpoint_helper (uint32_t hw_index)
-{
- kern_return_t kret = GetDBGState(false);
- if (kret != KERN_SUCCESS)
- return false;
- const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
- if (hw_index >= num_hw_points)
- return false;
+ for (i = 0; i < num_hw_watchpoints; ++i) {
+ if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0)
+ break; // We found an available hw watchpoint slot (in i)
+ }
+
+ // See if we found an available hw watchpoint slot above
+ if (i < num_hw_watchpoints) {
+ // DumpDBGState(m_state.dbg);
+
+ // Clear any previous LoHi joined-watchpoint that may have been in use
+ LoHi[i] = 0;
+
+ // shift our Byte Address Select bits up to the correct bit range for the
+ // DBGWCRn_EL1
+ byte_address_select = byte_address_select << 5;
+
+ // Make sure bits 1:0 are clear in our address
+ m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address)
+ m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow
+ // the DVA that we will watch
+ S_USER | // Stop only in user mode
+ (read ? WCR_LOAD : 0) | // Stop on read access?
+ (write ? WCR_STORE : 0) | // Stop on write access?
+ WCR_ENABLE; // Enable this watchpoint;
+
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint() adding "
+ "watchpoint on address 0x%llx with control register "
+ "value 0x%x",
+ (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]);
+
+ // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
+ // automatically, don't need to do it here.
+
+ kret = SetDBGState(also_set_on_task);
+ // DumpDBGState(m_state.dbg);
+
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
+ "EnableHardwareWatchpoint() "
+ "SetDBGState() => 0x%8.8x.",
+ kret);
+
+ if (kret == KERN_SUCCESS)
+ return i;
+ } else {
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
+ "EnableHardwareWatchpoint(): All "
+ "hardware resources (%u) are in use.",
+ num_hw_watchpoints);
+ }
+ }
+ return INVALID_NUB_HW_INDEX;
+}
+
+bool DNBArchMachARM::ReenableHardwareWatchpoint(uint32_t hw_index) {
+ // If this logical watchpoint # is actually implemented using
+ // two hardware watchpoint registers, re-enable both of them.
+
+ if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
+ return ReenableHardwareWatchpoint_helper(hw_index) &&
+ ReenableHardwareWatchpoint_helper(LoHi[hw_index]);
+ } else {
+ return ReenableHardwareWatchpoint_helper(hw_index);
+ }
+}
+
+bool DNBArchMachARM::ReenableHardwareWatchpoint_helper(uint32_t hw_index) {
+ kern_return_t kret = GetDBGState(false);
+ if (kret != KERN_SUCCESS)
+ return false;
+ const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
+ if (hw_index >= num_hw_points)
+ return false;
- m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr;
- m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control;
+ m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr;
+ m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control;
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint( %u ) - WVR%u = 0x%8.8llx WCR%u = 0x%8.8llx",
- hw_index,
- hw_index,
- (uint64_t) m_state.dbg.__wvr[hw_index],
- hw_index,
- (uint64_t) m_state.dbg.__wcr[hw_index]);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint( "
+ "%u ) - WVR%u = 0x%8.8llx WCR%u = "
+ "0x%8.8llx",
+ hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
+ hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us automatically, don't need to do it here.
+ // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
+ // automatically, don't need to do it here.
- kret = SetDBGState(false);
+ kret = SetDBGState(false);
- return (kret == KERN_SUCCESS);
+ return (kret == KERN_SUCCESS);
}
-bool
-DNBArchMachARM::DisableHardwareWatchpoint (uint32_t hw_index, bool also_set_on_task)
-{
- if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index])
- {
- return DisableHardwareWatchpoint_helper (hw_index, also_set_on_task) && DisableHardwareWatchpoint_helper (LoHi[hw_index], also_set_on_task);
- }
- else
- {
- return DisableHardwareWatchpoint_helper (hw_index, also_set_on_task);
- }
+bool DNBArchMachARM::DisableHardwareWatchpoint(uint32_t hw_index,
+ bool also_set_on_task) {
+ if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
+ return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) &&
+ DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task);
+ } else {
+ return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task);
+ }
}
-bool
-DNBArchMachARM::DisableHardwareWatchpoint_helper (uint32_t hw_index, bool also_set_on_task)
-{
- kern_return_t kret = GetDBGState(false);
- if (kret != KERN_SUCCESS)
- return false;
+bool DNBArchMachARM::DisableHardwareWatchpoint_helper(uint32_t hw_index,
+ bool also_set_on_task) {
+ kern_return_t kret = GetDBGState(false);
+ if (kret != KERN_SUCCESS)
+ return false;
- const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
- if (hw_index >= num_hw_points)
- return false;
+ const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
+ if (hw_index >= num_hw_points)
+ return false;
- m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index];
- m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index];
+ m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index];
+ m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index];
- m_state.dbg.__wvr[hw_index] = 0;
- m_state.dbg.__wcr[hw_index] = 0;
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::DisableHardwareWatchpoint( %u ) - WVR%u = 0x%8.8llx WCR%u = 0x%8.8llx",
- hw_index,
- hw_index,
- (uint64_t) m_state.dbg.__wvr[hw_index],
- hw_index,
- (uint64_t) m_state.dbg.__wcr[hw_index]);
+ m_state.dbg.__wvr[hw_index] = 0;
+ m_state.dbg.__wcr[hw_index] = 0;
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::DisableHardwareWatchpoint("
+ " %u ) - WVR%u = 0x%8.8llx WCR%u = "
+ "0x%8.8llx",
+ hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
+ hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
- kret = SetDBGState(also_set_on_task);
+ kret = SetDBGState(also_set_on_task);
- return (kret == KERN_SUCCESS);
+ return (kret == KERN_SUCCESS);
}
// Returns -1 if the trailing bit patterns are not one of:
// { 0b???1, 0b??10, 0b?100, 0b1000 }.
-static inline
-int32_t
-LowestBitSet(uint32_t val)
-{
- for (unsigned i = 0; i < 4; ++i) {
- if (bit(val, i))
- return i;
- }
- return -1;
+static inline int32_t LowestBitSet(uint32_t val) {
+ for (unsigned i = 0; i < 4; ++i) {
+ if (bit(val, i))
+ return i;
+ }
+ return -1;
}
-// Iterate through the debug registers; return the index of the first watchpoint whose address matches.
-// As a side effect, the starting address as understood by the debugger is returned which could be
+// Iterate through the debug registers; return the index of the first watchpoint
+// whose address matches.
+// As a side effect, the starting address as understood by the debugger is
+// returned which could be
// different from 'addr' passed as an in/out argument.
-uint32_t
-DNBArchMachARM::GetHardwareWatchpointHit(nub_addr_t &addr)
-{
- // Read the debug state
- kern_return_t kret = GetDBGState(true);
- //DumpDBGState(m_state.dbg);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::GetHardwareWatchpointHit() addr = 0x%llx", (uint64_t)addr);
-
- // This is the watchpoint value to match against, i.e., word address.
-#if defined (WATCHPOINTS_ARE_DWORD)
- nub_addr_t wp_val = addr & ~((nub_addr_t)7);
+uint32_t DNBArchMachARM::GetHardwareWatchpointHit(nub_addr_t &addr) {
+ // Read the debug state
+ kern_return_t kret = GetDBGState(true);
+ // DumpDBGState(m_state.dbg);
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchMachARM::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.",
+ kret);
+ DNBLogThreadedIf(LOG_WATCHPOINTS,
+ "DNBArchMachARM::GetHardwareWatchpointHit() addr = 0x%llx",
+ (uint64_t)addr);
+
+// This is the watchpoint value to match against, i.e., word address.
+#if defined(WATCHPOINTS_ARE_DWORD)
+ nub_addr_t wp_val = addr & ~((nub_addr_t)7);
#else
- nub_addr_t wp_val = addr & ~((nub_addr_t)3);
+ nub_addr_t wp_val = addr & ~((nub_addr_t)3);
#endif
- if (kret == KERN_SUCCESS)
- {
- DBG &debug_state = m_state.dbg;
- uint32_t i, num = NumSupportedHardwareWatchpoints();
- for (i = 0; i < num; ++i)
- {
- nub_addr_t wp_addr = GetWatchAddress(debug_state, i);
- DNBLogThreadedIf(LOG_WATCHPOINTS,
- "DNBArchMachARM::GetHardwareWatchpointHit() slot: %u (addr = 0x%llx).",
- i, (uint64_t)wp_addr);
- if (wp_val == wp_addr) {
-#if defined (WATCHPOINTS_ARE_DWORD)
- uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5);
+ if (kret == KERN_SUCCESS) {
+ DBG &debug_state = m_state.dbg;
+ uint32_t i, num = NumSupportedHardwareWatchpoints();
+ for (i = 0; i < num; ++i) {
+ nub_addr_t wp_addr = GetWatchAddress(debug_state, i);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
+ "GetHardwareWatchpointHit() slot: %u "
+ "(addr = 0x%llx).",
+ i, (uint64_t)wp_addr);
+ if (wp_val == wp_addr) {
+#if defined(WATCHPOINTS_ARE_DWORD)
+ uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5);
#else
- uint32_t byte_mask = bits(debug_state.__wcr[i], 8, 5);
+ uint32_t byte_mask = bits(debug_state.__wcr[i], 8, 5);
#endif
- // Sanity check the byte_mask, first.
- if (LowestBitSet(byte_mask) < 0)
- continue;
+ // Sanity check the byte_mask, first.
+ if (LowestBitSet(byte_mask) < 0)
+ continue;
- // Compute the starting address (from the point of view of the debugger).
- addr = wp_addr + LowestBitSet(byte_mask);
- return i;
- }
- }
+ // Compute the starting address (from the point of view of the
+ // debugger).
+ addr = wp_addr + LowestBitSet(byte_mask);
+ return i;
+ }
}
- return INVALID_NUB_HW_INDEX;
+ }
+ return INVALID_NUB_HW_INDEX;
}
-nub_addr_t
-DNBArchMachARM::GetWatchpointAddressByIndex (uint32_t hw_index)
-{
- kern_return_t kret = GetDBGState(true);
- if (kret != KERN_SUCCESS)
- return INVALID_NUB_ADDRESS;
- const uint32_t num = NumSupportedHardwareWatchpoints();
- if (hw_index >= num)
- return INVALID_NUB_ADDRESS;
- if (IsWatchpointEnabled (m_state.dbg, hw_index))
- return GetWatchAddress (m_state.dbg, hw_index);
+nub_addr_t DNBArchMachARM::GetWatchpointAddressByIndex(uint32_t hw_index) {
+ kern_return_t kret = GetDBGState(true);
+ if (kret != KERN_SUCCESS)
return INVALID_NUB_ADDRESS;
-}
-
-bool
-DNBArchMachARM::IsWatchpointEnabled(const DBG &debug_state, uint32_t hw_index)
-{
- // Watchpoint Control Registers, bitfield definitions
- // ...
- // Bits Value Description
- // [0] 0 Watchpoint disabled
- // 1 Watchpoint enabled.
- return (debug_state.__wcr[hw_index] & 1u);
-}
-
-nub_addr_t
-DNBArchMachARM::GetWatchAddress(const DBG &debug_state, uint32_t hw_index)
-{
- // Watchpoint Value Registers, bitfield definitions
- // Bits Description
- // [31:2] Watchpoint value (word address, i.e., 4-byte aligned)
- // [1:0] RAZ/SBZP
- return bits(debug_state.__wvr[hw_index], 31, 0);
+ const uint32_t num = NumSupportedHardwareWatchpoints();
+ if (hw_index >= num)
+ return INVALID_NUB_ADDRESS;
+ if (IsWatchpointEnabled(m_state.dbg, hw_index))
+ return GetWatchAddress(m_state.dbg, hw_index);
+ return INVALID_NUB_ADDRESS;
+}
+
+bool DNBArchMachARM::IsWatchpointEnabled(const DBG &debug_state,
+ uint32_t hw_index) {
+ // Watchpoint Control Registers, bitfield definitions
+ // ...
+ // Bits Value Description
+ // [0] 0 Watchpoint disabled
+ // 1 Watchpoint enabled.
+ return (debug_state.__wcr[hw_index] & 1u);
+}
+
+nub_addr_t DNBArchMachARM::GetWatchAddress(const DBG &debug_state,
+ uint32_t hw_index) {
+ // Watchpoint Value Registers, bitfield definitions
+ // Bits Description
+ // [31:2] Watchpoint value (word address, i.e., 4-byte aligned)
+ // [1:0] RAZ/SBZP
+ return bits(debug_state.__wvr[hw_index], 31, 0);
}
//----------------------------------------------------------------------
// Register information definitions for 32 bit ARMV7.
//----------------------------------------------------------------------
-enum gpr_regnums
-{
- gpr_r0 = 0,
- gpr_r1,
- gpr_r2,
- gpr_r3,
- gpr_r4,
- gpr_r5,
- gpr_r6,
- gpr_r7,
- gpr_r8,
- gpr_r9,
- gpr_r10,
- gpr_r11,
- gpr_r12,
- gpr_sp,
- gpr_lr,
- gpr_pc,
- gpr_cpsr
+enum gpr_regnums {
+ gpr_r0 = 0,
+ gpr_r1,
+ gpr_r2,
+ gpr_r3,
+ gpr_r4,
+ gpr_r5,
+ gpr_r6,
+ gpr_r7,
+ gpr_r8,
+ gpr_r9,
+ gpr_r10,
+ gpr_r11,
+ gpr_r12,
+ gpr_sp,
+ gpr_lr,
+ gpr_pc,
+ gpr_cpsr
};
-enum
-{
- vfp_s0 = 0,
- vfp_s1,
- vfp_s2,
- vfp_s3,
- vfp_s4,
- vfp_s5,
- vfp_s6,
- vfp_s7,
- vfp_s8,
- vfp_s9,
- vfp_s10,
- vfp_s11,
- vfp_s12,
- vfp_s13,
- vfp_s14,
- vfp_s15,
- vfp_s16,
- vfp_s17,
- vfp_s18,
- vfp_s19,
- vfp_s20,
- vfp_s21,
- vfp_s22,
- vfp_s23,
- vfp_s24,
- vfp_s25,
- vfp_s26,
- vfp_s27,
- vfp_s28,
- vfp_s29,
- vfp_s30,
- vfp_s31,
- vfp_d0,
- vfp_d1,
- vfp_d2,
- vfp_d3,
- vfp_d4,
- vfp_d5,
- vfp_d6,
- vfp_d7,
- vfp_d8,
- vfp_d9,
- vfp_d10,
- vfp_d11,
- vfp_d12,
- vfp_d13,
- vfp_d14,
- vfp_d15,
- vfp_d16,
- vfp_d17,
- vfp_d18,
- vfp_d19,
- vfp_d20,
- vfp_d21,
- vfp_d22,
- vfp_d23,
- vfp_d24,
- vfp_d25,
- vfp_d26,
- vfp_d27,
- vfp_d28,
- vfp_d29,
- vfp_d30,
- vfp_d31,
- vfp_q0,
- vfp_q1,
- vfp_q2,
- vfp_q3,
- vfp_q4,
- vfp_q5,
- vfp_q6,
- vfp_q7,
- vfp_q8,
- vfp_q9,
- vfp_q10,
- vfp_q11,
- vfp_q12,
- vfp_q13,
- vfp_q14,
- vfp_q15,
-#if defined (__arm64__) || defined (__aarch64__)
- vfp_fpsr,
- vfp_fpcr,
+enum {
+ vfp_s0 = 0,
+ vfp_s1,
+ vfp_s2,
+ vfp_s3,
+ vfp_s4,
+ vfp_s5,
+ vfp_s6,
+ vfp_s7,
+ vfp_s8,
+ vfp_s9,
+ vfp_s10,
+ vfp_s11,
+ vfp_s12,
+ vfp_s13,
+ vfp_s14,
+ vfp_s15,
+ vfp_s16,
+ vfp_s17,
+ vfp_s18,
+ vfp_s19,
+ vfp_s20,
+ vfp_s21,
+ vfp_s22,
+ vfp_s23,
+ vfp_s24,
+ vfp_s25,
+ vfp_s26,
+ vfp_s27,
+ vfp_s28,
+ vfp_s29,
+ vfp_s30,
+ vfp_s31,
+ vfp_d0,
+ vfp_d1,
+ vfp_d2,
+ vfp_d3,
+ vfp_d4,
+ vfp_d5,
+ vfp_d6,
+ vfp_d7,
+ vfp_d8,
+ vfp_d9,
+ vfp_d10,
+ vfp_d11,
+ vfp_d12,
+ vfp_d13,
+ vfp_d14,
+ vfp_d15,
+ vfp_d16,
+ vfp_d17,
+ vfp_d18,
+ vfp_d19,
+ vfp_d20,
+ vfp_d21,
+ vfp_d22,
+ vfp_d23,
+ vfp_d24,
+ vfp_d25,
+ vfp_d26,
+ vfp_d27,
+ vfp_d28,
+ vfp_d29,
+ vfp_d30,
+ vfp_d31,
+ vfp_q0,
+ vfp_q1,
+ vfp_q2,
+ vfp_q3,
+ vfp_q4,
+ vfp_q5,
+ vfp_q6,
+ vfp_q7,
+ vfp_q8,
+ vfp_q9,
+ vfp_q10,
+ vfp_q11,
+ vfp_q12,
+ vfp_q13,
+ vfp_q14,
+ vfp_q15,
+#if defined(__arm64__) || defined(__aarch64__)
+ vfp_fpsr,
+ vfp_fpcr,
#else
- vfp_fpscr
+ vfp_fpscr
#endif
};
-enum
-{
- exc_exception,
- exc_fsr,
- exc_far,
+enum {
+ exc_exception,
+ exc_fsr,
+ exc_far,
};
-#define GPR_OFFSET_IDX(idx) (offsetof (DNBArchMachARM::GPR, __r[idx]))
-#define GPR_OFFSET_NAME(reg) (offsetof (DNBArchMachARM::GPR, __##reg))
+#define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM::GPR, __r[idx]))
+#define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM::GPR, __##reg))
-#define EXC_OFFSET(reg) (offsetof (DNBArchMachARM::EXC, __##reg) + offsetof (DNBArchMachARM::Context, exc))
+#define EXC_OFFSET(reg) \
+ (offsetof(DNBArchMachARM::EXC, __##reg) + \
+ offsetof(DNBArchMachARM::Context, exc))
// These macros will auto define the register name, alt name, register size,
// register offset, encoding, format and native register. This ensures that
// the register state structures are defined correctly and have the correct
// sizes and offsets.
-#define DEFINE_GPR_IDX(idx, reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL}
-#define DEFINE_GPR_NAME(reg, alt, gen, inval) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, inval}
+#define DEFINE_GPR_IDX(idx, reg, alt, gen) \
+ { \
+ e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), \
+ ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL \
+ }
+#define DEFINE_GPR_NAME(reg, alt, gen, inval) \
+ { \
+ e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), \
+ ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, inval \
+ }
// In case we are debugging to a debug target that the ability to
// change into the protected modes with folded registers (ABT, IRQ,
// FIQ, SYS, USR, etc..), we should invalidate r8-r14 if the CPSR
// gets modified.
-const char * g_invalidate_cpsr[] = { "r8", "r9", "r10", "r11", "r12", "sp", "lr", NULL };
+const char *g_invalidate_cpsr[] = {"r8", "r9", "r10", "r11",
+ "r12", "sp", "lr", NULL};
// General purpose registers
-const DNBRegisterInfo
-DNBArchMachARM::g_gpr_registers[] =
-{
- DEFINE_GPR_IDX ( 0, r0,"arg1", GENERIC_REGNUM_ARG1 ),
- DEFINE_GPR_IDX ( 1, r1,"arg2", GENERIC_REGNUM_ARG2 ),
- DEFINE_GPR_IDX ( 2, r2,"arg3", GENERIC_REGNUM_ARG3 ),
- DEFINE_GPR_IDX ( 3, r3,"arg4", GENERIC_REGNUM_ARG4 ),
- DEFINE_GPR_IDX ( 4, r4, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX ( 5, r5, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX ( 6, r6, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX ( 7, r7, "fp", GENERIC_REGNUM_FP ),
- DEFINE_GPR_IDX ( 8, r8, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX ( 9, r9, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (10, r10, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (11, r11, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (12, r12, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_NAME (sp, "r13", GENERIC_REGNUM_SP, NULL),
- DEFINE_GPR_NAME (lr, "r14", GENERIC_REGNUM_RA, NULL),
- DEFINE_GPR_NAME (pc, "r15", GENERIC_REGNUM_PC, NULL),
- DEFINE_GPR_NAME (cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr)
-};
-
-const char *g_contained_q0 [] { "q0", NULL };
-const char *g_contained_q1 [] { "q1", NULL };
-const char *g_contained_q2 [] { "q2", NULL };
-const char *g_contained_q3 [] { "q3", NULL };
-const char *g_contained_q4 [] { "q4", NULL };
-const char *g_contained_q5 [] { "q5", NULL };
-const char *g_contained_q6 [] { "q6", NULL };
-const char *g_contained_q7 [] { "q7", NULL };
-const char *g_contained_q8 [] { "q8", NULL };
-const char *g_contained_q9 [] { "q9", NULL };
-const char *g_contained_q10[] { "q10", NULL };
-const char *g_contained_q11[] { "q11", NULL };
-const char *g_contained_q12[] { "q12", NULL };
-const char *g_contained_q13[] { "q13", NULL };
-const char *g_contained_q14[] { "q14", NULL };
-const char *g_contained_q15[] { "q15", NULL };
-
-const char *g_invalidate_q0[] { "q0", "d0" , "d1" , "s0" , "s1" , "s2" , "s3" , NULL };
-const char *g_invalidate_q1[] { "q1", "d2" , "d3" , "s4" , "s5" , "s6" , "s7" , NULL };
-const char *g_invalidate_q2[] { "q2", "d4" , "d5" , "s8" , "s9" , "s10", "s11", NULL };
-const char *g_invalidate_q3[] { "q3", "d6" , "d7" , "s12", "s13", "s14", "s15", NULL };
-const char *g_invalidate_q4[] { "q4", "d8" , "d9" , "s16", "s17", "s18", "s19", NULL };
-const char *g_invalidate_q5[] { "q5", "d10", "d11", "s20", "s21", "s22", "s23", NULL };
-const char *g_invalidate_q6[] { "q6", "d12", "d13", "s24", "s25", "s26", "s27", NULL };
-const char *g_invalidate_q7[] { "q7", "d14", "d15", "s28", "s29", "s30", "s31", NULL };
-const char *g_invalidate_q8[] { "q8", "d16", "d17", NULL };
-const char *g_invalidate_q9[] { "q9", "d18", "d19", NULL };
-const char *g_invalidate_q10[] { "q10", "d20", "d21", NULL };
-const char *g_invalidate_q11[] { "q11", "d22", "d23", NULL };
-const char *g_invalidate_q12[] { "q12", "d24", "d25", NULL };
-const char *g_invalidate_q13[] { "q13", "d26", "d27", NULL };
-const char *g_invalidate_q14[] { "q14", "d28", "d29", NULL };
-const char *g_invalidate_q15[] { "q15", "d30", "d31", NULL };
-
-#define VFP_S_OFFSET_IDX(idx) (((idx) % 4) * 4) // offset into q reg: 0, 4, 8, 12
-#define VFP_D_OFFSET_IDX(idx) (((idx) % 2) * 8) // offset into q reg: 0, 8
-#define VFP_Q_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX ((idx) * 4))
-
-#define VFP_OFFSET_NAME(reg) (offsetof (DNBArchMachARM::FPU, __##reg) + offsetof (DNBArchMachARM::Context, vfp))
+const DNBRegisterInfo DNBArchMachARM::g_gpr_registers[] = {
+ DEFINE_GPR_IDX(0, r0, "arg1", GENERIC_REGNUM_ARG1),
+ DEFINE_GPR_IDX(1, r1, "arg2", GENERIC_REGNUM_ARG2),
+ DEFINE_GPR_IDX(2, r2, "arg3", GENERIC_REGNUM_ARG3),
+ DEFINE_GPR_IDX(3, r3, "arg4", GENERIC_REGNUM_ARG4),
+ DEFINE_GPR_IDX(4, r4, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(5, r5, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(6, r6, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(7, r7, "fp", GENERIC_REGNUM_FP),
+ DEFINE_GPR_IDX(8, r8, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(9, r9, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(10, r10, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(11, r11, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(12, r12, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_NAME(sp, "r13", GENERIC_REGNUM_SP, NULL),
+ DEFINE_GPR_NAME(lr, "r14", GENERIC_REGNUM_RA, NULL),
+ DEFINE_GPR_NAME(pc, "r15", GENERIC_REGNUM_PC, NULL),
+ DEFINE_GPR_NAME(cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr)};
+
+const char *g_contained_q0[]{"q0", NULL};
+const char *g_contained_q1[]{"q1", NULL};
+const char *g_contained_q2[]{"q2", NULL};
+const char *g_contained_q3[]{"q3", NULL};
+const char *g_contained_q4[]{"q4", NULL};
+const char *g_contained_q5[]{"q5", NULL};
+const char *g_contained_q6[]{"q6", NULL};
+const char *g_contained_q7[]{"q7", NULL};
+const char *g_contained_q8[]{"q8", NULL};
+const char *g_contained_q9[]{"q9", NULL};
+const char *g_contained_q10[]{"q10", NULL};
+const char *g_contained_q11[]{"q11", NULL};
+const char *g_contained_q12[]{"q12", NULL};
+const char *g_contained_q13[]{"q13", NULL};
+const char *g_contained_q14[]{"q14", NULL};
+const char *g_contained_q15[]{"q15", NULL};
+
+const char *g_invalidate_q0[]{"q0", "d0", "d1", "s0", "s1", "s2", "s3", NULL};
+const char *g_invalidate_q1[]{"q1", "d2", "d3", "s4", "s5", "s6", "s7", NULL};
+const char *g_invalidate_q2[]{"q2", "d4", "d5", "s8", "s9", "s10", "s11", NULL};
+const char *g_invalidate_q3[]{"q3", "d6", "d7", "s12",
+ "s13", "s14", "s15", NULL};
+const char *g_invalidate_q4[]{"q4", "d8", "d9", "s16",
+ "s17", "s18", "s19", NULL};
+const char *g_invalidate_q5[]{"q5", "d10", "d11", "s20",
+ "s21", "s22", "s23", NULL};
+const char *g_invalidate_q6[]{"q6", "d12", "d13", "s24",
+ "s25", "s26", "s27", NULL};
+const char *g_invalidate_q7[]{"q7", "d14", "d15", "s28",
+ "s29", "s30", "s31", NULL};
+const char *g_invalidate_q8[]{"q8", "d16", "d17", NULL};
+const char *g_invalidate_q9[]{"q9", "d18", "d19", NULL};
+const char *g_invalidate_q10[]{"q10", "d20", "d21", NULL};
+const char *g_invalidate_q11[]{"q11", "d22", "d23", NULL};
+const char *g_invalidate_q12[]{"q12", "d24", "d25", NULL};
+const char *g_invalidate_q13[]{"q13", "d26", "d27", NULL};
+const char *g_invalidate_q14[]{"q14", "d28", "d29", NULL};
+const char *g_invalidate_q15[]{"q15", "d30", "d31", NULL};
+
+#define VFP_S_OFFSET_IDX(idx) \
+ (((idx) % 4) * 4) // offset into q reg: 0, 4, 8, 12
+#define VFP_D_OFFSET_IDX(idx) (((idx) % 2) * 8) // offset into q reg: 0, 8
+#define VFP_Q_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX((idx)*4))
+
+#define VFP_OFFSET_NAME(reg) \
+ (offsetof(DNBArchMachARM::FPU, __##reg) + \
+ offsetof(DNBArchMachARM::Context, vfp))
#define FLOAT_FORMAT Float
-#define DEFINE_VFP_S_IDX(idx) e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
-#define DEFINE_VFP_D_IDX(idx) e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
-#define DEFINE_VFP_Q_IDX(idx) e_regSetVFP, vfp_q##idx, "q" #idx, NULL, Vector, VectorOfUInt8, 16, VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
+#define DEFINE_VFP_S_IDX(idx) \
+ e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, \
+ VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
+#define DEFINE_VFP_D_IDX(idx) \
+ e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, \
+ VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
+#define DEFINE_VFP_Q_IDX(idx) \
+ e_regSetVFP, vfp_q##idx, "q" #idx, NULL, Vector, VectorOfUInt8, 16, \
+ VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
// Floating point registers
-const DNBRegisterInfo
-DNBArchMachARM::g_vfp_registers[] =
-{
- { DEFINE_VFP_S_IDX ( 0), g_contained_q0, g_invalidate_q0 },
- { DEFINE_VFP_S_IDX ( 1), g_contained_q0, g_invalidate_q0 },
- { DEFINE_VFP_S_IDX ( 2), g_contained_q0, g_invalidate_q0 },
- { DEFINE_VFP_S_IDX ( 3), g_contained_q0, g_invalidate_q0 },
- { DEFINE_VFP_S_IDX ( 4), g_contained_q1, g_invalidate_q1 },
- { DEFINE_VFP_S_IDX ( 5), g_contained_q1, g_invalidate_q1 },
- { DEFINE_VFP_S_IDX ( 6), g_contained_q1, g_invalidate_q1 },
- { DEFINE_VFP_S_IDX ( 7), g_contained_q1, g_invalidate_q1 },
- { DEFINE_VFP_S_IDX ( 8), g_contained_q2, g_invalidate_q2 },
- { DEFINE_VFP_S_IDX ( 9), g_contained_q2, g_invalidate_q2 },
- { DEFINE_VFP_S_IDX (10), g_contained_q2, g_invalidate_q2 },
- { DEFINE_VFP_S_IDX (11), g_contained_q2, g_invalidate_q2 },
- { DEFINE_VFP_S_IDX (12), g_contained_q3, g_invalidate_q3 },
- { DEFINE_VFP_S_IDX (13), g_contained_q3, g_invalidate_q3 },
- { DEFINE_VFP_S_IDX (14), g_contained_q3, g_invalidate_q3 },
- { DEFINE_VFP_S_IDX (15), g_contained_q3, g_invalidate_q3 },
- { DEFINE_VFP_S_IDX (16), g_contained_q4, g_invalidate_q4 },
- { DEFINE_VFP_S_IDX (17), g_contained_q4, g_invalidate_q4 },
- { DEFINE_VFP_S_IDX (18), g_contained_q4, g_invalidate_q4 },
- { DEFINE_VFP_S_IDX (19), g_contained_q4, g_invalidate_q4 },
- { DEFINE_VFP_S_IDX (20), g_contained_q5, g_invalidate_q5 },
- { DEFINE_VFP_S_IDX (21), g_contained_q5, g_invalidate_q5 },
- { DEFINE_VFP_S_IDX (22), g_contained_q5, g_invalidate_q5 },
- { DEFINE_VFP_S_IDX (23), g_contained_q5, g_invalidate_q5 },
- { DEFINE_VFP_S_IDX (24), g_contained_q6, g_invalidate_q6 },
- { DEFINE_VFP_S_IDX (25), g_contained_q6, g_invalidate_q6 },
- { DEFINE_VFP_S_IDX (26), g_contained_q6, g_invalidate_q6 },
- { DEFINE_VFP_S_IDX (27), g_contained_q6, g_invalidate_q6 },
- { DEFINE_VFP_S_IDX (28), g_contained_q7, g_invalidate_q7 },
- { DEFINE_VFP_S_IDX (29), g_contained_q7, g_invalidate_q7 },
- { DEFINE_VFP_S_IDX (30), g_contained_q7, g_invalidate_q7 },
- { DEFINE_VFP_S_IDX (31), g_contained_q7, g_invalidate_q7 },
-
- { DEFINE_VFP_D_IDX (0), g_contained_q0, g_invalidate_q0 },
- { DEFINE_VFP_D_IDX (1), g_contained_q0, g_invalidate_q0 },
- { DEFINE_VFP_D_IDX (2), g_contained_q1, g_invalidate_q1 },
- { DEFINE_VFP_D_IDX (3), g_contained_q1, g_invalidate_q1 },
- { DEFINE_VFP_D_IDX (4), g_contained_q2, g_invalidate_q2 },
- { DEFINE_VFP_D_IDX (5), g_contained_q2, g_invalidate_q2 },
- { DEFINE_VFP_D_IDX (6), g_contained_q3, g_invalidate_q3 },
- { DEFINE_VFP_D_IDX (7), g_contained_q3, g_invalidate_q3 },
- { DEFINE_VFP_D_IDX (8), g_contained_q4, g_invalidate_q4 },
- { DEFINE_VFP_D_IDX (9), g_contained_q4, g_invalidate_q4 },
- { DEFINE_VFP_D_IDX (10), g_contained_q5, g_invalidate_q5 },
- { DEFINE_VFP_D_IDX (11), g_contained_q5, g_invalidate_q5 },
- { DEFINE_VFP_D_IDX (12), g_contained_q6, g_invalidate_q6 },
- { DEFINE_VFP_D_IDX (13), g_contained_q6, g_invalidate_q6 },
- { DEFINE_VFP_D_IDX (14), g_contained_q7, g_invalidate_q7 },
- { DEFINE_VFP_D_IDX (15), g_contained_q7, g_invalidate_q7 },
- { DEFINE_VFP_D_IDX (16), g_contained_q8, g_invalidate_q8 },
- { DEFINE_VFP_D_IDX (17), g_contained_q8, g_invalidate_q8 },
- { DEFINE_VFP_D_IDX (18), g_contained_q9, g_invalidate_q9 },
- { DEFINE_VFP_D_IDX (19), g_contained_q9, g_invalidate_q9 },
- { DEFINE_VFP_D_IDX (20), g_contained_q10, g_invalidate_q10 },
- { DEFINE_VFP_D_IDX (21), g_contained_q10, g_invalidate_q10 },
- { DEFINE_VFP_D_IDX (22), g_contained_q11, g_invalidate_q11 },
- { DEFINE_VFP_D_IDX (23), g_contained_q11, g_invalidate_q11 },
- { DEFINE_VFP_D_IDX (24), g_contained_q12, g_invalidate_q12 },
- { DEFINE_VFP_D_IDX (25), g_contained_q12, g_invalidate_q12 },
- { DEFINE_VFP_D_IDX (26), g_contained_q13, g_invalidate_q13 },
- { DEFINE_VFP_D_IDX (27), g_contained_q13, g_invalidate_q13 },
- { DEFINE_VFP_D_IDX (28), g_contained_q14, g_invalidate_q14 },
- { DEFINE_VFP_D_IDX (29), g_contained_q14, g_invalidate_q14 },
- { DEFINE_VFP_D_IDX (30), g_contained_q15, g_invalidate_q15 },
- { DEFINE_VFP_D_IDX (31), g_contained_q15, g_invalidate_q15 },
-
- { DEFINE_VFP_Q_IDX (0), NULL, g_invalidate_q0 },
- { DEFINE_VFP_Q_IDX (1), NULL, g_invalidate_q1 },
- { DEFINE_VFP_Q_IDX (2), NULL, g_invalidate_q2 },
- { DEFINE_VFP_Q_IDX (3), NULL, g_invalidate_q3 },
- { DEFINE_VFP_Q_IDX (4), NULL, g_invalidate_q4 },
- { DEFINE_VFP_Q_IDX (5), NULL, g_invalidate_q5 },
- { DEFINE_VFP_Q_IDX (6), NULL, g_invalidate_q6 },
- { DEFINE_VFP_Q_IDX (7), NULL, g_invalidate_q7 },
- { DEFINE_VFP_Q_IDX (8), NULL, g_invalidate_q8 },
- { DEFINE_VFP_Q_IDX (9), NULL, g_invalidate_q9 },
- { DEFINE_VFP_Q_IDX (10), NULL, g_invalidate_q10 },
- { DEFINE_VFP_Q_IDX (11), NULL, g_invalidate_q11 },
- { DEFINE_VFP_Q_IDX (12), NULL, g_invalidate_q12 },
- { DEFINE_VFP_Q_IDX (13), NULL, g_invalidate_q13 },
- { DEFINE_VFP_Q_IDX (14), NULL, g_invalidate_q14 },
- { DEFINE_VFP_Q_IDX (15), NULL, g_invalidate_q15 },
-
-#if defined (__arm64__) || defined (__aarch64__)
- { e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
- { e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpcr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL }
+const DNBRegisterInfo DNBArchMachARM::g_vfp_registers[] = {
+ {DEFINE_VFP_S_IDX(0), g_contained_q0, g_invalidate_q0},
+ {DEFINE_VFP_S_IDX(1), g_contained_q0, g_invalidate_q0},
+ {DEFINE_VFP_S_IDX(2), g_contained_q0, g_invalidate_q0},
+ {DEFINE_VFP_S_IDX(3), g_contained_q0, g_invalidate_q0},
+ {DEFINE_VFP_S_IDX(4), g_contained_q1, g_invalidate_q1},
+ {DEFINE_VFP_S_IDX(5), g_contained_q1, g_invalidate_q1},
+ {DEFINE_VFP_S_IDX(6), g_contained_q1, g_invalidate_q1},
+ {DEFINE_VFP_S_IDX(7), g_contained_q1, g_invalidate_q1},
+ {DEFINE_VFP_S_IDX(8), g_contained_q2, g_invalidate_q2},
+ {DEFINE_VFP_S_IDX(9), g_contained_q2, g_invalidate_q2},
+ {DEFINE_VFP_S_IDX(10), g_contained_q2, g_invalidate_q2},
+ {DEFINE_VFP_S_IDX(11), g_contained_q2, g_invalidate_q2},
+ {DEFINE_VFP_S_IDX(12), g_contained_q3, g_invalidate_q3},
+ {DEFINE_VFP_S_IDX(13), g_contained_q3, g_invalidate_q3},
+ {DEFINE_VFP_S_IDX(14), g_contained_q3, g_invalidate_q3},
+ {DEFINE_VFP_S_IDX(15), g_contained_q3, g_invalidate_q3},
+ {DEFINE_VFP_S_IDX(16), g_contained_q4, g_invalidate_q4},
+ {DEFINE_VFP_S_IDX(17), g_contained_q4, g_invalidate_q4},
+ {DEFINE_VFP_S_IDX(18), g_contained_q4, g_invalidate_q4},
+ {DEFINE_VFP_S_IDX(19), g_contained_q4, g_invalidate_q4},
+ {DEFINE_VFP_S_IDX(20), g_contained_q5, g_invalidate_q5},
+ {DEFINE_VFP_S_IDX(21), g_contained_q5, g_invalidate_q5},
+ {DEFINE_VFP_S_IDX(22), g_contained_q5, g_invalidate_q5},
+ {DEFINE_VFP_S_IDX(23), g_contained_q5, g_invalidate_q5},
+ {DEFINE_VFP_S_IDX(24), g_contained_q6, g_invalidate_q6},
+ {DEFINE_VFP_S_IDX(25), g_contained_q6, g_invalidate_q6},
+ {DEFINE_VFP_S_IDX(26), g_contained_q6, g_invalidate_q6},
+ {DEFINE_VFP_S_IDX(27), g_contained_q6, g_invalidate_q6},
+ {DEFINE_VFP_S_IDX(28), g_contained_q7, g_invalidate_q7},
+ {DEFINE_VFP_S_IDX(29), g_contained_q7, g_invalidate_q7},
+ {DEFINE_VFP_S_IDX(30), g_contained_q7, g_invalidate_q7},
+ {DEFINE_VFP_S_IDX(31), g_contained_q7, g_invalidate_q7},
+
+ {DEFINE_VFP_D_IDX(0), g_contained_q0, g_invalidate_q0},
+ {DEFINE_VFP_D_IDX(1), g_contained_q0, g_invalidate_q0},
+ {DEFINE_VFP_D_IDX(2), g_contained_q1, g_invalidate_q1},
+ {DEFINE_VFP_D_IDX(3), g_contained_q1, g_invalidate_q1},
+ {DEFINE_VFP_D_IDX(4), g_contained_q2, g_invalidate_q2},
+ {DEFINE_VFP_D_IDX(5), g_contained_q2, g_invalidate_q2},
+ {DEFINE_VFP_D_IDX(6), g_contained_q3, g_invalidate_q3},
+ {DEFINE_VFP_D_IDX(7), g_contained_q3, g_invalidate_q3},
+ {DEFINE_VFP_D_IDX(8), g_contained_q4, g_invalidate_q4},
+ {DEFINE_VFP_D_IDX(9), g_contained_q4, g_invalidate_q4},
+ {DEFINE_VFP_D_IDX(10), g_contained_q5, g_invalidate_q5},
+ {DEFINE_VFP_D_IDX(11), g_contained_q5, g_invalidate_q5},
+ {DEFINE_VFP_D_IDX(12), g_contained_q6, g_invalidate_q6},
+ {DEFINE_VFP_D_IDX(13), g_contained_q6, g_invalidate_q6},
+ {DEFINE_VFP_D_IDX(14), g_contained_q7, g_invalidate_q7},
+ {DEFINE_VFP_D_IDX(15), g_contained_q7, g_invalidate_q7},
+ {DEFINE_VFP_D_IDX(16), g_contained_q8, g_invalidate_q8},
+ {DEFINE_VFP_D_IDX(17), g_contained_q8, g_invalidate_q8},
+ {DEFINE_VFP_D_IDX(18), g_contained_q9, g_invalidate_q9},
+ {DEFINE_VFP_D_IDX(19), g_contained_q9, g_invalidate_q9},
+ {DEFINE_VFP_D_IDX(20), g_contained_q10, g_invalidate_q10},
+ {DEFINE_VFP_D_IDX(21), g_contained_q10, g_invalidate_q10},
+ {DEFINE_VFP_D_IDX(22), g_contained_q11, g_invalidate_q11},
+ {DEFINE_VFP_D_IDX(23), g_contained_q11, g_invalidate_q11},
+ {DEFINE_VFP_D_IDX(24), g_contained_q12, g_invalidate_q12},
+ {DEFINE_VFP_D_IDX(25), g_contained_q12, g_invalidate_q12},
+ {DEFINE_VFP_D_IDX(26), g_contained_q13, g_invalidate_q13},
+ {DEFINE_VFP_D_IDX(27), g_contained_q13, g_invalidate_q13},
+ {DEFINE_VFP_D_IDX(28), g_contained_q14, g_invalidate_q14},
+ {DEFINE_VFP_D_IDX(29), g_contained_q14, g_invalidate_q14},
+ {DEFINE_VFP_D_IDX(30), g_contained_q15, g_invalidate_q15},
+ {DEFINE_VFP_D_IDX(31), g_contained_q15, g_invalidate_q15},
+
+ {DEFINE_VFP_Q_IDX(0), NULL, g_invalidate_q0},
+ {DEFINE_VFP_Q_IDX(1), NULL, g_invalidate_q1},
+ {DEFINE_VFP_Q_IDX(2), NULL, g_invalidate_q2},
+ {DEFINE_VFP_Q_IDX(3), NULL, g_invalidate_q3},
+ {DEFINE_VFP_Q_IDX(4), NULL, g_invalidate_q4},
+ {DEFINE_VFP_Q_IDX(5), NULL, g_invalidate_q5},
+ {DEFINE_VFP_Q_IDX(6), NULL, g_invalidate_q6},
+ {DEFINE_VFP_Q_IDX(7), NULL, g_invalidate_q7},
+ {DEFINE_VFP_Q_IDX(8), NULL, g_invalidate_q8},
+ {DEFINE_VFP_Q_IDX(9), NULL, g_invalidate_q9},
+ {DEFINE_VFP_Q_IDX(10), NULL, g_invalidate_q10},
+ {DEFINE_VFP_Q_IDX(11), NULL, g_invalidate_q11},
+ {DEFINE_VFP_Q_IDX(12), NULL, g_invalidate_q12},
+ {DEFINE_VFP_Q_IDX(13), NULL, g_invalidate_q13},
+ {DEFINE_VFP_Q_IDX(14), NULL, g_invalidate_q14},
+ {DEFINE_VFP_Q_IDX(15), NULL, g_invalidate_q15},
+
+#if defined(__arm64__) || defined(__aarch64__)
+ {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpsr),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpcr),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL}
#else
- { e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL }
+ {e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4,
+ VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}
#endif
};
// Exception registers
-const DNBRegisterInfo
-DNBArchMachARM::g_exc_registers[] =
-{
- { e_regSetVFP, exc_exception , "exception" , NULL, Uint, Hex, 4, EXC_OFFSET(exception) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM },
- { e_regSetVFP, exc_fsr , "fsr" , NULL, Uint, Hex, 4, EXC_OFFSET(fsr) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM },
- { e_regSetVFP, exc_far , "far" , NULL, Uint, Hex, 4, EXC_OFFSET(far) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM }
-};
+const DNBRegisterInfo DNBArchMachARM::g_exc_registers[] = {
+ {e_regSetVFP, exc_exception, "exception", NULL, Uint, Hex, 4,
+ EXC_OFFSET(exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM},
+ {e_regSetVFP, exc_fsr, "fsr", NULL, Uint, Hex, 4, EXC_OFFSET(fsr),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM},
+ {e_regSetVFP, exc_far, "far", NULL, Uint, Hex, 4, EXC_OFFSET(far),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM}};
// Number of registers in each register set
-const size_t DNBArchMachARM::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchMachARM::k_num_vfp_registers = sizeof(g_vfp_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchMachARM::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchMachARM::k_num_all_registers = k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers;
+const size_t DNBArchMachARM::k_num_gpr_registers =
+ sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchMachARM::k_num_vfp_registers =
+ sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchMachARM::k_num_exc_registers =
+ sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchMachARM::k_num_all_registers =
+ k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers;
//----------------------------------------------------------------------
// Register set definitions. The first definitions at register set index
// of zero is for all registers, followed by other registers sets. The
// register information for the all register set need not be filled in.
//----------------------------------------------------------------------
-const DNBRegisterSetInfo
-DNBArchMachARM::g_reg_sets[] =
-{
- { "ARM Registers", NULL, k_num_all_registers },
- { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers },
- { "Floating Point Registers", g_vfp_registers, k_num_vfp_registers },
- { "Exception State Registers", g_exc_registers, k_num_exc_registers }
-};
+const DNBRegisterSetInfo DNBArchMachARM::g_reg_sets[] = {
+ {"ARM Registers", NULL, k_num_all_registers},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
// Total number of register sets for this architecture
-const size_t DNBArchMachARM::k_num_register_sets = sizeof(g_reg_sets)/sizeof(DNBRegisterSetInfo);
-
+const size_t DNBArchMachARM::k_num_register_sets =
+ sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo);
const DNBRegisterSetInfo *
-DNBArchMachARM::GetRegisterSetInfo(nub_size_t *num_reg_sets)
-{
- *num_reg_sets = k_num_register_sets;
- return g_reg_sets;
-}
-
-bool
-DNBArchMachARM::GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value)
-{
- if (set == REGISTER_SET_GENERIC)
- {
- switch (reg)
- {
- case GENERIC_REGNUM_PC: // Program Counter
- set = e_regSetGPR;
- reg = gpr_pc;
- break;
-
- case GENERIC_REGNUM_SP: // Stack Pointer
- set = e_regSetGPR;
- reg = gpr_sp;
- break;
-
- case GENERIC_REGNUM_FP: // Frame Pointer
- set = e_regSetGPR;
- reg = gpr_r7; // is this the right reg?
- break;
-
- case GENERIC_REGNUM_RA: // Return Address
- set = e_regSetGPR;
- reg = gpr_lr;
- break;
-
- case GENERIC_REGNUM_FLAGS: // Processor flags register
- set = e_regSetGPR;
- reg = gpr_cpsr;
- break;
+DNBArchMachARM::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
+ *num_reg_sets = k_num_register_sets;
+ return g_reg_sets;
+}
+
+bool DNBArchMachARM::GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value) {
+ if (set == REGISTER_SET_GENERIC) {
+ switch (reg) {
+ case GENERIC_REGNUM_PC: // Program Counter
+ set = e_regSetGPR;
+ reg = gpr_pc;
+ break;
+
+ case GENERIC_REGNUM_SP: // Stack Pointer
+ set = e_regSetGPR;
+ reg = gpr_sp;
+ break;
+
+ case GENERIC_REGNUM_FP: // Frame Pointer
+ set = e_regSetGPR;
+ reg = gpr_r7; // is this the right reg?
+ break;
+
+ case GENERIC_REGNUM_RA: // Return Address
+ set = e_regSetGPR;
+ reg = gpr_lr;
+ break;
+
+ case GENERIC_REGNUM_FLAGS: // Processor flags register
+ set = e_regSetGPR;
+ reg = gpr_cpsr;
+ break;
- default:
- return false;
- }
+ default:
+ return false;
}
+ }
- if (GetRegisterState(set, false) != KERN_SUCCESS)
- return false;
+ if (GetRegisterState(set, false) != KERN_SUCCESS)
+ return false;
+
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ value->info = *regInfo;
+ switch (set) {
+ case e_regSetGPR:
+ if (reg < k_num_gpr_registers) {
+ value->value.uint32 = m_state.context.gpr.__r[reg];
+ return true;
+ }
+ break;
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- value->info = *regInfo;
- switch (set)
- {
- case e_regSetGPR:
- if (reg < k_num_gpr_registers)
- {
- value->value.uint32 = m_state.context.gpr.__r[reg];
- return true;
- }
- break;
-
- case e_regSetVFP:
- // "reg" is an index into the floating point register set at this point.
- // We need to translate it up so entry 0 in the fp reg set is the same as vfp_s0
- // in the enumerated values for case statement below.
- if (reg >= vfp_s0 && reg <= vfp_s31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- uint32_t *s_reg = ((uint32_t *) &m_state.context.vfp.__v[0]) + (reg - vfp_s0);
- memcpy (&value->value.v_uint8, s_reg, 4);
+ case e_regSetVFP:
+ // "reg" is an index into the floating point register set at this point.
+ // We need to translate it up so entry 0 in the fp reg set is the same as
+ // vfp_s0
+ // in the enumerated values for case statement below.
+ if (reg >= vfp_s0 && reg <= vfp_s31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ uint32_t *s_reg =
+ ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0);
+ memcpy(&value->value.v_uint8, s_reg, 4);
#else
- value->value.uint32 = m_state.context.vfp.__r[reg];
+ value->value.uint32 = m_state.context.vfp.__r[reg];
#endif
- return true;
- }
- else if (reg >= vfp_d0 && reg <= vfp_d31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- uint64_t *d_reg = ((uint64_t *) &m_state.context.vfp.__v[0]) + (reg - vfp_d0);
- memcpy (&value->value.v_uint8, d_reg, 8);
+ return true;
+ } else if (reg >= vfp_d0 && reg <= vfp_d31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ uint64_t *d_reg =
+ ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0);
+ memcpy(&value->value.v_uint8, d_reg, 8);
#else
- uint32_t d_reg_idx = reg - vfp_d0;
- uint32_t s_reg_idx = d_reg_idx * 2;
- value->value.v_sint32[0] = m_state.context.vfp.__r[s_reg_idx + 0];
- value->value.v_sint32[1] = m_state.context.vfp.__r[s_reg_idx + 1];
-#endif
- return true;
- }
- else if (reg >= vfp_q0 && reg <= vfp_q15)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&value->value.v_uint8, (uint8_t *) &m_state.context.vfp.__v[reg - vfp_q0], 16);
+ uint32_t d_reg_idx = reg - vfp_d0;
+ uint32_t s_reg_idx = d_reg_idx * 2;
+ value->value.v_sint32[0] = m_state.context.vfp.__r[s_reg_idx + 0];
+ value->value.v_sint32[1] = m_state.context.vfp.__r[s_reg_idx + 1];
+#endif
+ return true;
+ } else if (reg >= vfp_q0 && reg <= vfp_q15) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&value->value.v_uint8,
+ (uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0], 16);
#else
- uint32_t s_reg_idx = (reg - vfp_q0) * 4;
- memcpy (&value->value.v_uint8, (uint8_t *) &m_state.context.vfp.__r[s_reg_idx], 16);
+ uint32_t s_reg_idx = (reg - vfp_q0) * 4;
+ memcpy(&value->value.v_uint8,
+ (uint8_t *)&m_state.context.vfp.__r[s_reg_idx], 16);
#endif
- return true;
- }
-#if defined (__arm64__) || defined (__aarch64__)
- else if (reg == vfp_fpsr)
- {
- value->value.uint32 = m_state.context.vfp.__fpsr;
- return true;
- }
- else if (reg == vfp_fpcr)
- {
- value->value.uint32 = m_state.context.vfp.__fpcr;
- return true;
- }
+ return true;
+ }
+#if defined(__arm64__) || defined(__aarch64__)
+ else if (reg == vfp_fpsr) {
+ value->value.uint32 = m_state.context.vfp.__fpsr;
+ return true;
+ } else if (reg == vfp_fpcr) {
+ value->value.uint32 = m_state.context.vfp.__fpcr;
+ return true;
+ }
#else
- else if (reg == vfp_fpscr)
- {
- value->value.uint32 = m_state.context.vfp.__fpscr;
- return true;
- }
-#endif
- break;
-
- case e_regSetEXC:
- if (reg < k_num_exc_registers)
- {
- value->value.uint32 = (&m_state.context.exc.__exception)[reg];
- return true;
- }
- break;
- }
+ else if (reg == vfp_fpscr) {
+ value->value.uint32 = m_state.context.vfp.__fpscr;
+ return true;
+ }
+#endif
+ break;
+
+ case e_regSetEXC:
+ if (reg < k_num_exc_registers) {
+ value->value.uint32 = (&m_state.context.exc.__exception)[reg];
+ return true;
+ }
+ break;
}
- return false;
+ }
+ return false;
}
-bool
-DNBArchMachARM::SetRegisterValue(uint32_t set, uint32_t reg, const DNBRegisterValue *value)
-{
- if (set == REGISTER_SET_GENERIC)
- {
- switch (reg)
- {
- case GENERIC_REGNUM_PC: // Program Counter
- set = e_regSetGPR;
- reg = gpr_pc;
- break;
-
- case GENERIC_REGNUM_SP: // Stack Pointer
- set = e_regSetGPR;
- reg = gpr_sp;
- break;
-
- case GENERIC_REGNUM_FP: // Frame Pointer
- set = e_regSetGPR;
- reg = gpr_r7;
- break;
-
- case GENERIC_REGNUM_RA: // Return Address
- set = e_regSetGPR;
- reg = gpr_lr;
- break;
-
- case GENERIC_REGNUM_FLAGS: // Processor flags register
- set = e_regSetGPR;
- reg = gpr_cpsr;
- break;
+bool DNBArchMachARM::SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value) {
+ if (set == REGISTER_SET_GENERIC) {
+ switch (reg) {
+ case GENERIC_REGNUM_PC: // Program Counter
+ set = e_regSetGPR;
+ reg = gpr_pc;
+ break;
+
+ case GENERIC_REGNUM_SP: // Stack Pointer
+ set = e_regSetGPR;
+ reg = gpr_sp;
+ break;
+
+ case GENERIC_REGNUM_FP: // Frame Pointer
+ set = e_regSetGPR;
+ reg = gpr_r7;
+ break;
+
+ case GENERIC_REGNUM_RA: // Return Address
+ set = e_regSetGPR;
+ reg = gpr_lr;
+ break;
+
+ case GENERIC_REGNUM_FLAGS: // Processor flags register
+ set = e_regSetGPR;
+ reg = gpr_cpsr;
+ break;
- default:
- return false;
- }
+ default:
+ return false;
}
+ }
- if (GetRegisterState(set, false) != KERN_SUCCESS)
- return false;
+ if (GetRegisterState(set, false) != KERN_SUCCESS)
+ return false;
- bool success = false;
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- switch (set)
- {
- case e_regSetGPR:
- if (reg < k_num_gpr_registers)
- {
- m_state.context.gpr.__r[reg] = value->value.uint32;
- success = true;
- }
- break;
-
- case e_regSetVFP:
- // "reg" is an index into the floating point register set at this point.
- // We need to translate it up so entry 0 in the fp reg set is the same as vfp_s0
- // in the enumerated values for case statement below.
- if (reg >= vfp_s0 && reg <= vfp_s31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- uint32_t *s_reg = ((uint32_t *) &m_state.context.vfp.__v[0]) + (reg - vfp_s0);
- memcpy (s_reg, &value->value.v_uint8, 4);
+ bool success = false;
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ switch (set) {
+ case e_regSetGPR:
+ if (reg < k_num_gpr_registers) {
+ m_state.context.gpr.__r[reg] = value->value.uint32;
+ success = true;
+ }
+ break;
+
+ case e_regSetVFP:
+ // "reg" is an index into the floating point register set at this point.
+ // We need to translate it up so entry 0 in the fp reg set is the same as
+ // vfp_s0
+ // in the enumerated values for case statement below.
+ if (reg >= vfp_s0 && reg <= vfp_s31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ uint32_t *s_reg =
+ ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0);
+ memcpy(s_reg, &value->value.v_uint8, 4);
#else
- m_state.context.vfp.__r[reg] = value->value.uint32;
+ m_state.context.vfp.__r[reg] = value->value.uint32;
#endif
- success = true;
- }
- else if (reg >= vfp_d0 && reg <= vfp_d31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- uint64_t *d_reg = ((uint64_t *) &m_state.context.vfp.__v[0]) + (reg - vfp_d0);
- memcpy (d_reg, &value->value.v_uint8, 8);
+ success = true;
+ } else if (reg >= vfp_d0 && reg <= vfp_d31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ uint64_t *d_reg =
+ ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0);
+ memcpy(d_reg, &value->value.v_uint8, 8);
#else
- uint32_t d_reg_idx = reg - vfp_d0;
- uint32_t s_reg_idx = d_reg_idx * 2;
- m_state.context.vfp.__r[s_reg_idx + 0] = value->value.v_sint32[0];
- m_state.context.vfp.__r[s_reg_idx + 1] = value->value.v_sint32[1];
-#endif
- success = true;
- }
- else if (reg >= vfp_q0 && reg <= vfp_q15)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy ((uint8_t *) &m_state.context.vfp.__v[reg - vfp_q0], &value->value.v_uint8, 16);
+ uint32_t d_reg_idx = reg - vfp_d0;
+ uint32_t s_reg_idx = d_reg_idx * 2;
+ m_state.context.vfp.__r[s_reg_idx + 0] = value->value.v_sint32[0];
+ m_state.context.vfp.__r[s_reg_idx + 1] = value->value.v_sint32[1];
+#endif
+ success = true;
+ } else if (reg >= vfp_q0 && reg <= vfp_q15) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy((uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0],
+ &value->value.v_uint8, 16);
#else
- uint32_t s_reg_idx = (reg - vfp_q0) * 4;
- memcpy ((uint8_t *) &m_state.context.vfp.__r[s_reg_idx], &value->value.v_uint8, 16);
-#endif
- success = true;
- }
-#if defined (__arm64__) || defined (__aarch64__)
- else if (reg == vfp_fpsr)
- {
- m_state.context.vfp.__fpsr = value->value.uint32;
- success = true;
- }
- else if (reg == vfp_fpcr)
- {
- m_state.context.vfp.__fpcr = value->value.uint32;
- success = true;
- }
+ uint32_t s_reg_idx = (reg - vfp_q0) * 4;
+ memcpy((uint8_t *)&m_state.context.vfp.__r[s_reg_idx],
+ &value->value.v_uint8, 16);
+#endif
+ success = true;
+ }
+#if defined(__arm64__) || defined(__aarch64__)
+ else if (reg == vfp_fpsr) {
+ m_state.context.vfp.__fpsr = value->value.uint32;
+ success = true;
+ } else if (reg == vfp_fpcr) {
+ m_state.context.vfp.__fpcr = value->value.uint32;
+ success = true;
+ }
#else
- else if (reg == vfp_fpscr)
- {
- m_state.context.vfp.__fpscr = value->value.uint32;
- success = true;
- }
-#endif
- break;
-
- case e_regSetEXC:
- if (reg < k_num_exc_registers)
- {
- (&m_state.context.exc.__exception)[reg] = value->value.uint32;
- success = true;
- }
- break;
- }
-
- }
- if (success)
- return SetRegisterState(set) == KERN_SUCCESS;
- return false;
-}
-
-kern_return_t
-DNBArchMachARM::GetRegisterState(int set, bool force)
-{
- switch (set)
- {
- case e_regSetALL: return GetGPRState(force) |
- GetVFPState(force) |
- GetEXCState(force) |
- GetDBGState(force);
- case e_regSetGPR: return GetGPRState(force);
- case e_regSetVFP: return GetVFPState(force);
- case e_regSetEXC: return GetEXCState(force);
- case e_regSetDBG: return GetDBGState(force);
- default: break;
- }
- return KERN_INVALID_ARGUMENT;
-}
-
-kern_return_t
-DNBArchMachARM::SetRegisterState(int set)
-{
- // Make sure we have a valid context to set.
- kern_return_t err = GetRegisterState(set, false);
- if (err != KERN_SUCCESS)
- return err;
-
- switch (set)
- {
- case e_regSetALL: return SetGPRState() |
- SetVFPState() |
- SetEXCState() |
- SetDBGState(false);
- case e_regSetGPR: return SetGPRState();
- case e_regSetVFP: return SetVFPState();
- case e_regSetEXC: return SetEXCState();
- case e_regSetDBG: return SetDBGState(false);
- default: break;
- }
- return KERN_INVALID_ARGUMENT;
-}
-
-bool
-DNBArchMachARM::RegisterSetStateIsValid (int set) const
-{
- return m_state.RegsAreValid(set);
-}
-
-
-nub_size_t
-DNBArchMachARM::GetRegisterContext (void *buf, nub_size_t buf_len)
-{
- nub_size_t size = sizeof (m_state.context.gpr) +
- sizeof (m_state.context.vfp) +
- sizeof (m_state.context.exc);
-
- if (buf && buf_len)
- {
- if (size > buf_len)
- size = buf_len;
-
- bool force = false;
- if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
- return 0;
-
- // Copy each struct individually to avoid any padding that might be between the structs in m_state.context
- uint8_t *p = (uint8_t *)buf;
- ::memcpy (p, &m_state.context.gpr, sizeof(m_state.context.gpr));
- p += sizeof(m_state.context.gpr);
- ::memcpy (p, &m_state.context.vfp, sizeof(m_state.context.vfp));
- p += sizeof(m_state.context.vfp);
- ::memcpy (p, &m_state.context.exc, sizeof(m_state.context.exc));
- p += sizeof(m_state.context.exc);
-
- size_t bytes_written = p - (uint8_t *)buf;
- UNUSED_IF_ASSERT_DISABLED(bytes_written);
- assert (bytes_written == size);
-
- }
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::GetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
- // Return the size of the register context even if NULL was passed in
- return size;
-}
-
-nub_size_t
-DNBArchMachARM::SetRegisterContext (const void *buf, nub_size_t buf_len)
-{
- nub_size_t size = sizeof (m_state.context.gpr) +
- sizeof (m_state.context.vfp) +
- sizeof (m_state.context.exc);
-
- if (buf == NULL || buf_len == 0)
- size = 0;
-
- if (size)
- {
- if (size > buf_len)
- size = buf_len;
-
- // Copy each struct individually to avoid any padding that might be between the structs in m_state.context
- uint8_t *p = (uint8_t *)buf;
- ::memcpy (&m_state.context.gpr, p, sizeof(m_state.context.gpr));
- p += sizeof(m_state.context.gpr);
- ::memcpy (&m_state.context.vfp, p, sizeof(m_state.context.vfp));
- p += sizeof(m_state.context.vfp);
- ::memcpy (&m_state.context.exc, p, sizeof(m_state.context.exc));
- p += sizeof(m_state.context.exc);
-
- size_t bytes_written = p - (uint8_t *)buf;
- UNUSED_IF_ASSERT_DISABLED(bytes_written);
- assert (bytes_written == size);
-
- if (SetGPRState() | SetVFPState() | SetEXCState())
- return 0;
- }
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::SetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
- return size;
-}
-
-
-uint32_t
-DNBArchMachARM::SaveRegisterState ()
-{
- kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
- DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
-
- // Always re-read the registers because above we call thread_abort_safely();
- bool force = true;
-
- if ((kret = GetGPRState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: GPR regs failed to read: %u ", kret);
- }
- else if ((kret = GetVFPState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: %s regs failed to read: %u", "VFP", kret);
- }
- else
- {
- const uint32_t save_id = GetNextRegisterStateSaveID ();
- m_saved_register_states[save_id] = m_state.context;
- return save_id;
- }
- return UINT32_MAX;
-}
-
-bool
-DNBArchMachARM::RestoreRegisterState (uint32_t save_id)
-{
- SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
- if (pos != m_saved_register_states.end())
- {
- m_state.context.gpr = pos->second.gpr;
- m_state.context.vfp = pos->second.vfp;
- kern_return_t kret;
- bool success = true;
- if ((kret = SetGPRState()) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::RestoreRegisterState (save_id = %u) error: GPR regs failed to write: %u", save_id, kret);
- success = false;
- }
- else if ((kret = SetVFPState()) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::RestoreRegisterState (save_id = %u) error: %s regs failed to write: %u", save_id, "VFP", kret);
- success = false;
- }
- m_saved_register_states.erase(pos);
- return success;
+ else if (reg == vfp_fpscr) {
+ m_state.context.vfp.__fpscr = value->value.uint32;
+ success = true;
+ }
+#endif
+ break;
+
+ case e_regSetEXC:
+ if (reg < k_num_exc_registers) {
+ (&m_state.context.exc.__exception)[reg] = value->value.uint32;
+ success = true;
+ }
+ break;
+ }
+ }
+ if (success)
+ return SetRegisterState(set) == KERN_SUCCESS;
+ return false;
+}
+
+kern_return_t DNBArchMachARM::GetRegisterState(int set, bool force) {
+ switch (set) {
+ case e_regSetALL:
+ return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) |
+ GetDBGState(force);
+ case e_regSetGPR:
+ return GetGPRState(force);
+ case e_regSetVFP:
+ return GetVFPState(force);
+ case e_regSetEXC:
+ return GetEXCState(force);
+ case e_regSetDBG:
+ return GetDBGState(force);
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
+}
+
+kern_return_t DNBArchMachARM::SetRegisterState(int set) {
+ // Make sure we have a valid context to set.
+ kern_return_t err = GetRegisterState(set, false);
+ if (err != KERN_SUCCESS)
+ return err;
+
+ switch (set) {
+ case e_regSetALL:
+ return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false);
+ case e_regSetGPR:
+ return SetGPRState();
+ case e_regSetVFP:
+ return SetVFPState();
+ case e_regSetEXC:
+ return SetEXCState();
+ case e_regSetDBG:
+ return SetDBGState(false);
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
+}
+
+bool DNBArchMachARM::RegisterSetStateIsValid(int set) const {
+ return m_state.RegsAreValid(set);
+}
+
+nub_size_t DNBArchMachARM::GetRegisterContext(void *buf, nub_size_t buf_len) {
+ nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
+ sizeof(m_state.context.exc);
+
+ if (buf && buf_len) {
+ if (size > buf_len)
+ size = buf_len;
+
+ bool force = false;
+ if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
+ return 0;
+
+ // Copy each struct individually to avoid any padding that might be between
+ // the structs in m_state.context
+ uint8_t *p = (uint8_t *)buf;
+ ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr));
+ p += sizeof(m_state.context.gpr);
+ ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp));
+ p += sizeof(m_state.context.vfp);
+ ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc));
+ p += sizeof(m_state.context.exc);
+
+ size_t bytes_written = p - (uint8_t *)buf;
+ UNUSED_IF_ASSERT_DISABLED(bytes_written);
+ assert(bytes_written == size);
+ }
+ DNBLogThreadedIf(
+ LOG_THREAD,
+ "DNBArchMachARM::GetRegisterContext (buf = %p, len = %llu) => %llu", buf,
+ (uint64_t)buf_len, (uint64_t)size);
+ // Return the size of the register context even if NULL was passed in
+ return size;
+}
+
+nub_size_t DNBArchMachARM::SetRegisterContext(const void *buf,
+ nub_size_t buf_len) {
+ nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
+ sizeof(m_state.context.exc);
+
+ if (buf == NULL || buf_len == 0)
+ size = 0;
+
+ if (size) {
+ if (size > buf_len)
+ size = buf_len;
+
+ // Copy each struct individually to avoid any padding that might be between
+ // the structs in m_state.context
+ uint8_t *p = (uint8_t *)buf;
+ ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr));
+ p += sizeof(m_state.context.gpr);
+ ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp));
+ p += sizeof(m_state.context.vfp);
+ ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc));
+ p += sizeof(m_state.context.exc);
+
+ size_t bytes_written = p - (uint8_t *)buf;
+ UNUSED_IF_ASSERT_DISABLED(bytes_written);
+ assert(bytes_written == size);
+
+ if (SetGPRState() | SetVFPState() | SetEXCState())
+ return 0;
+ }
+ DNBLogThreadedIf(
+ LOG_THREAD,
+ "DNBArchMachARM::SetRegisterContext (buf = %p, len = %llu) => %llu", buf,
+ (uint64_t)buf_len, (uint64_t)size);
+ return size;
+}
+
+uint32_t DNBArchMachARM::SaveRegisterState() {
+ kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
+ DNBLogThreadedIf(
+ LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
+ "(SetGPRState() for stop_count = %u)",
+ m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
+
+ // Always re-read the registers because above we call thread_abort_safely();
+ bool force = true;
+
+ if ((kret = GetGPRState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: "
+ "GPR regs failed to read: %u ",
+ kret);
+ } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: "
+ "%s regs failed to read: %u",
+ "VFP", kret);
+ } else {
+ const uint32_t save_id = GetNextRegisterStateSaveID();
+ m_saved_register_states[save_id] = m_state.context;
+ return save_id;
+ }
+ return UINT32_MAX;
+}
+
+bool DNBArchMachARM::RestoreRegisterState(uint32_t save_id) {
+ SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
+ if (pos != m_saved_register_states.end()) {
+ m_state.context.gpr = pos->second.gpr;
+ m_state.context.vfp = pos->second.vfp;
+ kern_return_t kret;
+ bool success = true;
+ if ((kret = SetGPRState()) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState "
+ "(save_id = %u) error: GPR regs failed to "
+ "write: %u",
+ save_id, kret);
+ success = false;
+ } else if ((kret = SetVFPState()) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState "
+ "(save_id = %u) error: %s regs failed to "
+ "write: %u",
+ save_id, "VFP", kret);
+ success = false;
}
- return false;
+ m_saved_register_states.erase(pos);
+ return success;
+ }
+ return false;
}
-
-#endif // #if defined (__arm__)
-
+#endif // #if defined (__arm__)
Modified: lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.h Tue Sep 6 15:57:50 2016
@@ -14,7 +14,7 @@
#ifndef __DebugNubArchMachARM_h__
#define __DebugNubArchMachARM_h__
-#if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
+#if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
#include "DNBArch.h"
@@ -22,261 +22,254 @@
class MachThread;
-class DNBArchMachARM : public DNBArchProtocol
-{
+class DNBArchMachARM : public DNBArchProtocol {
public:
- enum { kMaxNumThumbITBreakpoints = 4 };
+ enum { kMaxNumThumbITBreakpoints = 4 };
- DNBArchMachARM(MachThread *thread) :
- m_thread(thread),
- m_state(),
- m_disabled_watchpoints(),
+ DNBArchMachARM(MachThread *thread)
+ : m_thread(thread), m_state(), m_disabled_watchpoints(),
m_hw_single_chained_step_addr(INVALID_NUB_ADDRESS),
- m_last_decode_pc(INVALID_NUB_ADDRESS),
- m_watchpoint_hw_index(-1),
+ m_last_decode_pc(INVALID_NUB_ADDRESS), m_watchpoint_hw_index(-1),
m_watchpoint_did_occur(false),
m_watchpoint_resume_single_step_enabled(false),
- m_saved_register_states()
- {
- m_disabled_watchpoints.resize (16);
- memset(&m_dbg_save, 0, sizeof(m_dbg_save));
-#if defined (USE_ARM_DISASSEMBLER_FRAMEWORK)
- ThumbStaticsInit(&m_last_decode_thumb);
+ m_saved_register_states() {
+ m_disabled_watchpoints.resize(16);
+ memset(&m_dbg_save, 0, sizeof(m_dbg_save));
+#if defined(USE_ARM_DISASSEMBLER_FRAMEWORK)
+ ThumbStaticsInit(&m_last_decode_thumb);
#endif
- }
+ }
- virtual ~DNBArchMachARM()
- {
- }
+ virtual ~DNBArchMachARM() {}
- static void Initialize();
- static const DNBRegisterSetInfo *
- GetRegisterSetInfo(nub_size_t *num_reg_sets);
-
- virtual bool GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value);
- virtual bool SetRegisterValue(uint32_t set, uint32_t reg, const DNBRegisterValue *value);
- virtual nub_size_t GetRegisterContext (void *buf, nub_size_t buf_len);
- virtual nub_size_t SetRegisterContext (const void *buf, nub_size_t buf_len);
- virtual uint32_t SaveRegisterState ();
- virtual bool RestoreRegisterState (uint32_t save_id);
-
- virtual kern_return_t GetRegisterState (int set, bool force);
- virtual kern_return_t SetRegisterState (int set);
- virtual bool RegisterSetStateIsValid (int set) const;
-
- virtual uint64_t GetPC(uint64_t failValue); // Get program counter
- virtual kern_return_t SetPC(uint64_t value);
- virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
- virtual void ThreadWillResume();
- virtual bool ThreadDidStop();
- virtual bool NotifyException(MachException::Data& exc);
-
- static DNBArchProtocol *Create (MachThread *thread);
- static const uint8_t * SoftwareBreakpointOpcode (nub_size_t byte_size);
- static uint32_t GetCPUType();
-
- virtual uint32_t NumSupportedHardwareBreakpoints();
- virtual uint32_t NumSupportedHardwareWatchpoints();
- virtual uint32_t EnableHardwareBreakpoint (nub_addr_t addr, nub_size_t size);
- virtual bool DisableHardwareBreakpoint (uint32_t hw_break_index);
-
- virtual uint32_t EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task);
- virtual bool DisableHardwareWatchpoint (uint32_t hw_break_index, bool also_set_on_task);
- virtual bool DisableHardwareWatchpoint_helper (uint32_t hw_break_index, bool also_set_on_task);
- virtual bool ReenableHardwareWatchpoint (uint32_t hw_break_index);
- virtual bool ReenableHardwareWatchpoint_helper (uint32_t hw_break_index);
+ static void Initialize();
+ static const DNBRegisterSetInfo *GetRegisterSetInfo(nub_size_t *num_reg_sets);
- virtual bool StepNotComplete ();
- virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
+ virtual bool GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value);
+ virtual bool SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value);
+ virtual nub_size_t GetRegisterContext(void *buf, nub_size_t buf_len);
+ virtual nub_size_t SetRegisterContext(const void *buf, nub_size_t buf_len);
+ virtual uint32_t SaveRegisterState();
+ virtual bool RestoreRegisterState(uint32_t save_id);
+
+ virtual kern_return_t GetRegisterState(int set, bool force);
+ virtual kern_return_t SetRegisterState(int set);
+ virtual bool RegisterSetStateIsValid(int set) const;
+
+ virtual uint64_t GetPC(uint64_t failValue); // Get program counter
+ virtual kern_return_t SetPC(uint64_t value);
+ virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
+ virtual void ThreadWillResume();
+ virtual bool ThreadDidStop();
+ virtual bool NotifyException(MachException::Data &exc);
+
+ static DNBArchProtocol *Create(MachThread *thread);
+ static const uint8_t *SoftwareBreakpointOpcode(nub_size_t byte_size);
+ static uint32_t GetCPUType();
+
+ virtual uint32_t NumSupportedHardwareBreakpoints();
+ virtual uint32_t NumSupportedHardwareWatchpoints();
+ virtual uint32_t EnableHardwareBreakpoint(nub_addr_t addr, nub_size_t size);
+ virtual bool DisableHardwareBreakpoint(uint32_t hw_break_index);
+
+ virtual uint32_t EnableHardwareWatchpoint(nub_addr_t addr, nub_size_t size,
+ bool read, bool write,
+ bool also_set_on_task);
+ virtual bool DisableHardwareWatchpoint(uint32_t hw_break_index,
+ bool also_set_on_task);
+ virtual bool DisableHardwareWatchpoint_helper(uint32_t hw_break_index,
+ bool also_set_on_task);
+ virtual bool ReenableHardwareWatchpoint(uint32_t hw_break_index);
+ virtual bool ReenableHardwareWatchpoint_helper(uint32_t hw_break_index);
-#if defined (ARM_DEBUG_STATE32) && (defined (__arm64__) || defined (__aarch64__))
- typedef arm_debug_state32_t DBG;
+ virtual bool StepNotComplete();
+ virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
+
+#if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
+ typedef arm_debug_state32_t DBG;
#else
- typedef arm_debug_state_t DBG;
+ typedef arm_debug_state_t DBG;
#endif
protected:
+ kern_return_t EnableHardwareSingleStep(bool enable);
+ kern_return_t SetSingleStepSoftwareBreakpoints();
-
- kern_return_t EnableHardwareSingleStep (bool enable);
- kern_return_t SetSingleStepSoftwareBreakpoints ();
-
- bool ConditionPassed(uint8_t condition, uint32_t cpsr);
-#if defined (USE_ARM_DISASSEMBLER_FRAMEWORK)
- bool ComputeNextPC(nub_addr_t currentPC, arm_decoded_instruction_t decodedInstruction, bool currentPCIsThumb, nub_addr_t *targetPC);
- arm_error_t DecodeInstructionUsingDisassembler(nub_addr_t curr_pc, uint32_t curr_cpsr, arm_decoded_instruction_t *decodedInstruction, thumb_static_data_t *thumbStaticData, nub_addr_t *next_pc);
- void DecodeITBlockInstructions(nub_addr_t curr_pc);
+ bool ConditionPassed(uint8_t condition, uint32_t cpsr);
+#if defined(USE_ARM_DISASSEMBLER_FRAMEWORK)
+ bool ComputeNextPC(nub_addr_t currentPC,
+ arm_decoded_instruction_t decodedInstruction,
+ bool currentPCIsThumb, nub_addr_t *targetPC);
+ arm_error_t DecodeInstructionUsingDisassembler(
+ nub_addr_t curr_pc, uint32_t curr_cpsr,
+ arm_decoded_instruction_t *decodedInstruction,
+ thumb_static_data_t *thumbStaticData, nub_addr_t *next_pc);
+ void DecodeITBlockInstructions(nub_addr_t curr_pc);
#endif
- void EvaluateNextInstructionForSoftwareBreakpointSetup(nub_addr_t currentPC, uint32_t cpsr, bool currentPCIsThumb, nub_addr_t *nextPC, bool *nextPCIsThumb);
-
-
- typedef enum RegisterSetTag
- {
- e_regSetALL = REGISTER_SET_ALL,
- e_regSetGPR, // ARM_THREAD_STATE
- e_regSetVFP, // ARM_VFP_STATE (ARM_NEON_STATE if defined __arm64__)
- e_regSetEXC, // ARM_EXCEPTION_STATE
- e_regSetDBG, // ARM_DEBUG_STATE (ARM_DEBUG_STATE32 if defined __arm64__)
- kNumRegisterSets
- } RegisterSet;
-
- enum
- {
- Read = 0,
- Write = 1,
- kNumErrors = 2
- };
-
- typedef arm_thread_state_t GPR;
-#if defined (__arm64__) || defined (__aarch64__)
- typedef arm_neon_state_t FPU;
+ void EvaluateNextInstructionForSoftwareBreakpointSetup(nub_addr_t currentPC,
+ uint32_t cpsr,
+ bool currentPCIsThumb,
+ nub_addr_t *nextPC,
+ bool *nextPCIsThumb);
+
+ typedef enum RegisterSetTag {
+ e_regSetALL = REGISTER_SET_ALL,
+ e_regSetGPR, // ARM_THREAD_STATE
+ e_regSetVFP, // ARM_VFP_STATE (ARM_NEON_STATE if defined __arm64__)
+ e_regSetEXC, // ARM_EXCEPTION_STATE
+ e_regSetDBG, // ARM_DEBUG_STATE (ARM_DEBUG_STATE32 if defined __arm64__)
+ kNumRegisterSets
+ } RegisterSet;
+
+ enum { Read = 0, Write = 1, kNumErrors = 2 };
+
+ typedef arm_thread_state_t GPR;
+#if defined(__arm64__) || defined(__aarch64__)
+ typedef arm_neon_state_t FPU;
#else
- typedef arm_vfp_state_t FPU;
+ typedef arm_vfp_state_t FPU;
#endif
- typedef arm_exception_state_t EXC;
+ typedef arm_exception_state_t EXC;
- static const DNBRegisterInfo g_gpr_registers[];
- static const DNBRegisterInfo g_vfp_registers[];
- static const DNBRegisterInfo g_exc_registers[];
- static const DNBRegisterSetInfo g_reg_sets[];
-
- static const size_t k_num_gpr_registers;
- static const size_t k_num_vfp_registers;
- static const size_t k_num_exc_registers;
- static const size_t k_num_all_registers;
- static const size_t k_num_register_sets;
-
- struct Context
- {
- GPR gpr;
- FPU vfp;
- EXC exc;
- };
-
- struct State
- {
- Context context;
- DBG dbg;
- kern_return_t gpr_errs[2]; // Read/Write errors
- kern_return_t vfp_errs[2]; // Read/Write errors
- kern_return_t exc_errs[2]; // Read/Write errors
- kern_return_t dbg_errs[2]; // Read/Write errors
- State()
- {
- uint32_t i;
- for (i=0; i<kNumErrors; i++)
- {
- gpr_errs[i] = -1;
- vfp_errs[i] = -1;
- exc_errs[i] = -1;
- dbg_errs[i] = -1;
- }
- }
- void InvalidateRegisterSetState(int set)
- {
- SetError (set, Read, -1);
- }
- kern_return_t GetError (int set, uint32_t err_idx) const
- {
- if (err_idx < kNumErrors)
- {
- switch (set)
- {
- // When getting all errors, just OR all values together to see if
- // we got any kind of error.
- case e_regSetALL: return gpr_errs[err_idx] |
- vfp_errs[err_idx] |
- exc_errs[err_idx] |
- dbg_errs[err_idx] ;
- case e_regSetGPR: return gpr_errs[err_idx];
- case e_regSetVFP: return vfp_errs[err_idx];
- case e_regSetEXC: return exc_errs[err_idx];
- case e_regSetDBG: return dbg_errs[err_idx];
- default: break;
- }
- }
- return -1;
- }
- bool SetError (int set, uint32_t err_idx, kern_return_t err)
- {
- if (err_idx < kNumErrors)
- {
- switch (set)
- {
- case e_regSetALL:
- gpr_errs[err_idx] = err;
- vfp_errs[err_idx] = err;
- dbg_errs[err_idx] = err;
- exc_errs[err_idx] = err;
- return true;
-
- case e_regSetGPR:
- gpr_errs[err_idx] = err;
- return true;
-
- case e_regSetVFP:
- vfp_errs[err_idx] = err;
- return true;
-
- case e_regSetEXC:
- exc_errs[err_idx] = err;
- return true;
-
- case e_regSetDBG:
- dbg_errs[err_idx] = err;
- return true;
- default: break;
- }
- }
- return false;
+ static const DNBRegisterInfo g_gpr_registers[];
+ static const DNBRegisterInfo g_vfp_registers[];
+ static const DNBRegisterInfo g_exc_registers[];
+ static const DNBRegisterSetInfo g_reg_sets[];
+
+ static const size_t k_num_gpr_registers;
+ static const size_t k_num_vfp_registers;
+ static const size_t k_num_exc_registers;
+ static const size_t k_num_all_registers;
+ static const size_t k_num_register_sets;
+
+ struct Context {
+ GPR gpr;
+ FPU vfp;
+ EXC exc;
+ };
+
+ struct State {
+ Context context;
+ DBG dbg;
+ kern_return_t gpr_errs[2]; // Read/Write errors
+ kern_return_t vfp_errs[2]; // Read/Write errors
+ kern_return_t exc_errs[2]; // Read/Write errors
+ kern_return_t dbg_errs[2]; // Read/Write errors
+ State() {
+ uint32_t i;
+ for (i = 0; i < kNumErrors; i++) {
+ gpr_errs[i] = -1;
+ vfp_errs[i] = -1;
+ exc_errs[i] = -1;
+ dbg_errs[i] = -1;
+ }
+ }
+ void InvalidateRegisterSetState(int set) { SetError(set, Read, -1); }
+ kern_return_t GetError(int set, uint32_t err_idx) const {
+ if (err_idx < kNumErrors) {
+ switch (set) {
+ // When getting all errors, just OR all values together to see if
+ // we got any kind of error.
+ case e_regSetALL:
+ return gpr_errs[err_idx] | vfp_errs[err_idx] | exc_errs[err_idx] |
+ dbg_errs[err_idx];
+ case e_regSetGPR:
+ return gpr_errs[err_idx];
+ case e_regSetVFP:
+ return vfp_errs[err_idx];
+ case e_regSetEXC:
+ return exc_errs[err_idx];
+ case e_regSetDBG:
+ return dbg_errs[err_idx];
+ default:
+ break;
}
- bool RegsAreValid (int set) const
- {
- return GetError(set, Read) == KERN_SUCCESS;
+ }
+ return -1;
+ }
+ bool SetError(int set, uint32_t err_idx, kern_return_t err) {
+ if (err_idx < kNumErrors) {
+ switch (set) {
+ case e_regSetALL:
+ gpr_errs[err_idx] = err;
+ vfp_errs[err_idx] = err;
+ dbg_errs[err_idx] = err;
+ exc_errs[err_idx] = err;
+ return true;
+
+ case e_regSetGPR:
+ gpr_errs[err_idx] = err;
+ return true;
+
+ case e_regSetVFP:
+ vfp_errs[err_idx] = err;
+ return true;
+
+ case e_regSetEXC:
+ exc_errs[err_idx] = err;
+ return true;
+
+ case e_regSetDBG:
+ dbg_errs[err_idx] = err;
+ return true;
+ default:
+ break;
}
- };
+ }
+ return false;
+ }
+ bool RegsAreValid(int set) const {
+ return GetError(set, Read) == KERN_SUCCESS;
+ }
+ };
- kern_return_t GetGPRState (bool force);
- kern_return_t GetVFPState (bool force);
- kern_return_t GetEXCState (bool force);
- kern_return_t GetDBGState (bool force);
-
- kern_return_t SetGPRState ();
- kern_return_t SetVFPState ();
- kern_return_t SetEXCState ();
- kern_return_t SetDBGState (bool also_set_on_task);
-
- bool IsWatchpointEnabled(const DBG &debug_state, uint32_t hw_index);
- nub_addr_t GetWatchpointAddressByIndex (uint32_t hw_index);
- nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
-
- class disabled_watchpoint {
- public:
- disabled_watchpoint () { addr = 0; control = 0; }
- nub_addr_t addr;
- uint32_t control;
- };
+ kern_return_t GetGPRState(bool force);
+ kern_return_t GetVFPState(bool force);
+ kern_return_t GetEXCState(bool force);
+ kern_return_t GetDBGState(bool force);
+
+ kern_return_t SetGPRState();
+ kern_return_t SetVFPState();
+ kern_return_t SetEXCState();
+ kern_return_t SetDBGState(bool also_set_on_task);
+
+ bool IsWatchpointEnabled(const DBG &debug_state, uint32_t hw_index);
+ nub_addr_t GetWatchpointAddressByIndex(uint32_t hw_index);
+ nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
+
+ class disabled_watchpoint {
+ public:
+ disabled_watchpoint() {
+ addr = 0;
+ control = 0;
+ }
+ nub_addr_t addr;
+ uint32_t control;
+ };
protected:
- MachThread * m_thread;
- State m_state;
- DBG m_dbg_save;
-
- // armv8 doesn't keep the disabled watchpoint values in the debug register context like armv7;
- // we need to save them aside when we disable them temporarily.
- std::vector<disabled_watchpoint> m_disabled_watchpoints;
-
- nub_addr_t m_hw_single_chained_step_addr;
- nub_addr_t m_last_decode_pc;
-
- // The following member variables should be updated atomically.
- int32_t m_watchpoint_hw_index;
- bool m_watchpoint_did_occur;
- bool m_watchpoint_resume_single_step_enabled;
+ MachThread *m_thread;
+ State m_state;
+ DBG m_dbg_save;
+
+ // armv8 doesn't keep the disabled watchpoint values in the debug register
+ // context like armv7;
+ // we need to save them aside when we disable them temporarily.
+ std::vector<disabled_watchpoint> m_disabled_watchpoints;
+
+ nub_addr_t m_hw_single_chained_step_addr;
+ nub_addr_t m_last_decode_pc;
+
+ // The following member variables should be updated atomically.
+ int32_t m_watchpoint_hw_index;
+ bool m_watchpoint_did_occur;
+ bool m_watchpoint_resume_single_step_enabled;
- typedef std::map<uint32_t, Context> SaveRegisterStates;
- SaveRegisterStates m_saved_register_states;
+ typedef std::map<uint32_t, Context> SaveRegisterStates;
+ SaveRegisterStates m_saved_register_states;
};
-#endif // #if defined (__arm__)
-#endif // #ifndef __DebugNubArchMachARM_h__
+#endif // #if defined (__arm__)
+#endif // #ifndef __DebugNubArchMachARM_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.cpp Tue Sep 6 15:57:50 2016
@@ -11,1349 +11,1359 @@
//
//===----------------------------------------------------------------------===//
-#if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
+#if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
#include "MacOSX/arm64/DNBArchImplARM64.h"
-#if defined (ARM_THREAD_STATE64_COUNT)
+#if defined(ARM_THREAD_STATE64_COUNT)
-#include "MacOSX/MachProcess.h"
-#include "MacOSX/MachThread.h"
+#include "DNB.h"
#include "DNBBreakpoint.h"
#include "DNBLog.h"
#include "DNBRegisterInfo.h"
-#include "DNB.h"
+#include "MacOSX/MachProcess.h"
+#include "MacOSX/MachThread.h"
#include <inttypes.h>
#include <sys/sysctl.h>
// Break only in privileged or user mode
// (PAC bits in the DBGWVRn_EL1 watchpoint control register)
-#define S_USER ((uint32_t)(2u << 1))
+#define S_USER ((uint32_t)(2u << 1))
-#define BCR_ENABLE ((uint32_t)(1u))
-#define WCR_ENABLE ((uint32_t)(1u))
+#define BCR_ENABLE ((uint32_t)(1u))
+#define WCR_ENABLE ((uint32_t)(1u))
// Watchpoint load/store
// (LSC bits in the DBGWVRn_EL1 watchpoint control register)
-#define WCR_LOAD ((uint32_t)(1u << 3))
-#define WCR_STORE ((uint32_t)(1u << 4))
+#define WCR_LOAD ((uint32_t)(1u << 3))
+#define WCR_STORE ((uint32_t)(1u << 4))
// Enable breakpoint, watchpoint, and vector catch debug exceptions.
-// (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in DBGDSCRext in Aarch32)
+// (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in
+// DBGDSCRext in Aarch32)
#define MDE_ENABLE ((uint32_t)(1u << 15))
// Single instruction step
// (SS bit in the MDSCR_EL1 register)
#define SS_ENABLE ((uint32_t)(1u))
-static const uint8_t g_arm64_breakpoint_opcode[] = { 0x00, 0x00, 0x20, 0xD4 }; // "brk #0", 0xd4200000 in BE byte order
-static const uint8_t g_arm_breakpoint_opcode[] = { 0xFE, 0xDE, 0xFF, 0xE7 }; // this armv7 insn also works in arm64
+static const uint8_t g_arm64_breakpoint_opcode[] = {
+ 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order
+static const uint8_t g_arm_breakpoint_opcode[] = {
+ 0xFE, 0xDE, 0xFF, 0xE7}; // this armv7 insn also works in arm64
// If we need to set one logical watchpoint by using
// two hardware watchpoint registers, the watchpoint
// will be split into a "high" and "low" watchpoint.
// Record both of them in the LoHi array.
-// It's safe to initialize to all 0's since
+// It's safe to initialize to all 0's since
// hi > lo and therefore LoHi[i] cannot be 0.
-static uint32_t LoHi[16] = { 0 };
+static uint32_t LoHi[16] = {0};
+void DNBArchMachARM64::Initialize() {
+ DNBArchPluginInfo arch_plugin_info = {
+ CPU_TYPE_ARM64, DNBArchMachARM64::Create,
+ DNBArchMachARM64::GetRegisterSetInfo,
+ DNBArchMachARM64::SoftwareBreakpointOpcode};
-void
-DNBArchMachARM64::Initialize()
-{
- DNBArchPluginInfo arch_plugin_info =
- {
- CPU_TYPE_ARM64,
- DNBArchMachARM64::Create,
- DNBArchMachARM64::GetRegisterSetInfo,
- DNBArchMachARM64::SoftwareBreakpointOpcode
- };
-
- // Register this arch plug-in with the main protocol class
- DNBArchProtocol::RegisterArchPlugin (arch_plugin_info);
+ // Register this arch plug-in with the main protocol class
+ DNBArchProtocol::RegisterArchPlugin(arch_plugin_info);
}
+DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) {
+ DNBArchMachARM64 *obj = new DNBArchMachARM64(thread);
-DNBArchProtocol *
-DNBArchMachARM64::Create (MachThread *thread)
-{
- DNBArchMachARM64 *obj = new DNBArchMachARM64 (thread);
-
- return obj;
+ return obj;
}
const uint8_t *
-DNBArchMachARM64::SoftwareBreakpointOpcode (nub_size_t byte_size)
-{
- return g_arm_breakpoint_opcode;
-}
-
-uint32_t
-DNBArchMachARM64::GetCPUType()
-{
- return CPU_TYPE_ARM64;
-}
-
-uint64_t
-DNBArchMachARM64::GetPC(uint64_t failValue)
-{
- // Get program counter
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.context.gpr.__pc;
- return failValue;
-}
-
-kern_return_t
-DNBArchMachARM64::SetPC(uint64_t value)
-{
- // Get program counter
- kern_return_t err = GetGPRState(false);
- if (err == KERN_SUCCESS)
- {
- m_state.context.gpr.__pc = value;
- err = SetGPRState();
- }
- return err == KERN_SUCCESS;
+DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) {
+ return g_arm_breakpoint_opcode;
}
-uint64_t
-DNBArchMachARM64::GetSP(uint64_t failValue)
-{
- // Get stack pointer
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.context.gpr.__sp;
- return failValue;
-}
-
-kern_return_t
-DNBArchMachARM64::GetGPRState(bool force)
-{
- int set = e_regSetGPR;
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
- mach_msg_type_number_t count = e_regSetGPRCount;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, (thread_state_t)&m_state.context.gpr, &count);
- if (DNBLogEnabledForAny (LOG_THREAD))
- {
- uint64_t *x = &m_state.context.gpr.__x[0];
- DNBLogThreaded("thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs"
- "\n x0=%16.16llx"
- "\n x1=%16.16llx"
- "\n x2=%16.16llx"
- "\n x3=%16.16llx"
- "\n x4=%16.16llx"
- "\n x5=%16.16llx"
- "\n x6=%16.16llx"
- "\n x7=%16.16llx"
- "\n x8=%16.16llx"
- "\n x9=%16.16llx"
- "\n x10=%16.16llx"
- "\n x11=%16.16llx"
- "\n x12=%16.16llx"
- "\n x13=%16.16llx"
- "\n x14=%16.16llx"
- "\n x15=%16.16llx"
- "\n x16=%16.16llx"
- "\n x17=%16.16llx"
- "\n x18=%16.16llx"
- "\n x19=%16.16llx"
- "\n x20=%16.16llx"
- "\n x21=%16.16llx"
- "\n x22=%16.16llx"
- "\n x23=%16.16llx"
- "\n x24=%16.16llx"
- "\n x25=%16.16llx"
- "\n x26=%16.16llx"
- "\n x27=%16.16llx"
- "\n x28=%16.16llx"
- "\n fp=%16.16llx"
- "\n lr=%16.16llx"
- "\n sp=%16.16llx"
- "\n pc=%16.16llx"
- "\n cpsr=%8.8x",
- m_thread->MachPortNumber(),
- e_regSetGPR,
- e_regSetGPRCount,
- kret,
- count,
- x[0],
- x[1],
- x[2],
- x[3],
- x[4],
- x[5],
- x[6],
- x[7],
- x[8],
- x[9],
- x[0],
- x[11],
- x[12],
- x[13],
- x[14],
- x[15],
- x[16],
- x[17],
- x[18],
- x[19],
- x[20],
- x[21],
- x[22],
- x[23],
- x[24],
- x[25],
- x[26],
- x[27],
- x[28],
- m_state.context.gpr.__fp,
- m_state.context.gpr.__lr,
- m_state.context.gpr.__sp,
- m_state.context.gpr.__pc,
- m_state.context.gpr.__cpsr);
- }
- m_state.SetError(set, Read, kret);
- return kret;
-}
+uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; }
-kern_return_t
-DNBArchMachARM64::GetVFPState(bool force)
-{
- int set = e_regSetVFP;
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
- mach_msg_type_number_t count = e_regSetVFPCount;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, (thread_state_t)&m_state.context.vfp, &count);
- if (DNBLogEnabledForAny (LOG_THREAD))
- {
-#if defined (__arm64__) || defined (__aarch64__)
- DNBLogThreaded("thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
- "\n q0 = 0x%16.16llx%16.16llx"
- "\n q1 = 0x%16.16llx%16.16llx"
- "\n q2 = 0x%16.16llx%16.16llx"
- "\n q3 = 0x%16.16llx%16.16llx"
- "\n q4 = 0x%16.16llx%16.16llx"
- "\n q5 = 0x%16.16llx%16.16llx"
- "\n q6 = 0x%16.16llx%16.16llx"
- "\n q7 = 0x%16.16llx%16.16llx"
- "\n q8 = 0x%16.16llx%16.16llx"
- "\n q9 = 0x%16.16llx%16.16llx"
- "\n q10 = 0x%16.16llx%16.16llx"
- "\n q11 = 0x%16.16llx%16.16llx"
- "\n q12 = 0x%16.16llx%16.16llx"
- "\n q13 = 0x%16.16llx%16.16llx"
- "\n q14 = 0x%16.16llx%16.16llx"
- "\n q15 = 0x%16.16llx%16.16llx"
- "\n q16 = 0x%16.16llx%16.16llx"
- "\n q17 = 0x%16.16llx%16.16llx"
- "\n q18 = 0x%16.16llx%16.16llx"
- "\n q19 = 0x%16.16llx%16.16llx"
- "\n q20 = 0x%16.16llx%16.16llx"
- "\n q21 = 0x%16.16llx%16.16llx"
- "\n q22 = 0x%16.16llx%16.16llx"
- "\n q23 = 0x%16.16llx%16.16llx"
- "\n q24 = 0x%16.16llx%16.16llx"
- "\n q25 = 0x%16.16llx%16.16llx"
- "\n q26 = 0x%16.16llx%16.16llx"
- "\n q27 = 0x%16.16llx%16.16llx"
- "\n q28 = 0x%16.16llx%16.16llx"
- "\n q29 = 0x%16.16llx%16.16llx"
- "\n q30 = 0x%16.16llx%16.16llx"
- "\n q31 = 0x%16.16llx%16.16llx"
- "\n fpsr = 0x%8.8x"
- "\n fpcr = 0x%8.8x\n\n",
- m_thread->MachPortNumber(),
- e_regSetVFP,
- e_regSetVFPCount,
- kret,
- count,
- ((uint64_t *)&m_state.context.vfp.__v[0])[0] , ((uint64_t *)&m_state.context.vfp.__v[0])[1],
- ((uint64_t *)&m_state.context.vfp.__v[1])[0] , ((uint64_t *)&m_state.context.vfp.__v[1])[1],
- ((uint64_t *)&m_state.context.vfp.__v[2])[0] , ((uint64_t *)&m_state.context.vfp.__v[2])[1],
- ((uint64_t *)&m_state.context.vfp.__v[3])[0] , ((uint64_t *)&m_state.context.vfp.__v[3])[1],
- ((uint64_t *)&m_state.context.vfp.__v[4])[0] , ((uint64_t *)&m_state.context.vfp.__v[4])[1],
- ((uint64_t *)&m_state.context.vfp.__v[5])[0] , ((uint64_t *)&m_state.context.vfp.__v[5])[1],
- ((uint64_t *)&m_state.context.vfp.__v[6])[0] , ((uint64_t *)&m_state.context.vfp.__v[6])[1],
- ((uint64_t *)&m_state.context.vfp.__v[7])[0] , ((uint64_t *)&m_state.context.vfp.__v[7])[1],
- ((uint64_t *)&m_state.context.vfp.__v[8])[0] , ((uint64_t *)&m_state.context.vfp.__v[8])[1],
- ((uint64_t *)&m_state.context.vfp.__v[9])[0] , ((uint64_t *)&m_state.context.vfp.__v[9])[1],
- ((uint64_t *)&m_state.context.vfp.__v[10])[0], ((uint64_t *)&m_state.context.vfp.__v[10])[1],
- ((uint64_t *)&m_state.context.vfp.__v[11])[0], ((uint64_t *)&m_state.context.vfp.__v[11])[1],
- ((uint64_t *)&m_state.context.vfp.__v[12])[0], ((uint64_t *)&m_state.context.vfp.__v[12])[1],
- ((uint64_t *)&m_state.context.vfp.__v[13])[0], ((uint64_t *)&m_state.context.vfp.__v[13])[1],
- ((uint64_t *)&m_state.context.vfp.__v[14])[0], ((uint64_t *)&m_state.context.vfp.__v[14])[1],
- ((uint64_t *)&m_state.context.vfp.__v[15])[0], ((uint64_t *)&m_state.context.vfp.__v[15])[1],
- ((uint64_t *)&m_state.context.vfp.__v[16])[0], ((uint64_t *)&m_state.context.vfp.__v[16])[1],
- ((uint64_t *)&m_state.context.vfp.__v[17])[0], ((uint64_t *)&m_state.context.vfp.__v[17])[1],
- ((uint64_t *)&m_state.context.vfp.__v[18])[0], ((uint64_t *)&m_state.context.vfp.__v[18])[1],
- ((uint64_t *)&m_state.context.vfp.__v[19])[0], ((uint64_t *)&m_state.context.vfp.__v[19])[1],
- ((uint64_t *)&m_state.context.vfp.__v[20])[0], ((uint64_t *)&m_state.context.vfp.__v[20])[1],
- ((uint64_t *)&m_state.context.vfp.__v[21])[0], ((uint64_t *)&m_state.context.vfp.__v[21])[1],
- ((uint64_t *)&m_state.context.vfp.__v[22])[0], ((uint64_t *)&m_state.context.vfp.__v[22])[1],
- ((uint64_t *)&m_state.context.vfp.__v[23])[0], ((uint64_t *)&m_state.context.vfp.__v[23])[1],
- ((uint64_t *)&m_state.context.vfp.__v[24])[0], ((uint64_t *)&m_state.context.vfp.__v[24])[1],
- ((uint64_t *)&m_state.context.vfp.__v[25])[0], ((uint64_t *)&m_state.context.vfp.__v[25])[1],
- ((uint64_t *)&m_state.context.vfp.__v[26])[0], ((uint64_t *)&m_state.context.vfp.__v[26])[1],
- ((uint64_t *)&m_state.context.vfp.__v[27])[0], ((uint64_t *)&m_state.context.vfp.__v[27])[1],
- ((uint64_t *)&m_state.context.vfp.__v[28])[0], ((uint64_t *)&m_state.context.vfp.__v[28])[1],
- ((uint64_t *)&m_state.context.vfp.__v[29])[0], ((uint64_t *)&m_state.context.vfp.__v[29])[1],
- ((uint64_t *)&m_state.context.vfp.__v[30])[0], ((uint64_t *)&m_state.context.vfp.__v[30])[1],
- ((uint64_t *)&m_state.context.vfp.__v[31])[0], ((uint64_t *)&m_state.context.vfp.__v[31])[1],
- m_state.context.vfp.__fpsr,
- m_state.context.vfp.__fpcr);
+uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) {
+ // Get program counter
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.context.gpr.__pc;
+ return failValue;
+}
+
+kern_return_t DNBArchMachARM64::SetPC(uint64_t value) {
+ // Get program counter
+ kern_return_t err = GetGPRState(false);
+ if (err == KERN_SUCCESS) {
+ m_state.context.gpr.__pc = value;
+ err = SetGPRState();
+ }
+ return err == KERN_SUCCESS;
+}
+
+uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) {
+ // Get stack pointer
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.context.gpr.__sp;
+ return failValue;
+}
+
+kern_return_t DNBArchMachARM64::GetGPRState(bool force) {
+ int set = e_regSetGPR;
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ // Read the registers from our thread
+ mach_msg_type_number_t count = e_regSetGPRCount;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64,
+ (thread_state_t)&m_state.context.gpr, &count);
+ if (DNBLogEnabledForAny(LOG_THREAD)) {
+ uint64_t *x = &m_state.context.gpr.__x[0];
+ DNBLogThreaded(
+ "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs"
+ "\n x0=%16.16llx"
+ "\n x1=%16.16llx"
+ "\n x2=%16.16llx"
+ "\n x3=%16.16llx"
+ "\n x4=%16.16llx"
+ "\n x5=%16.16llx"
+ "\n x6=%16.16llx"
+ "\n x7=%16.16llx"
+ "\n x8=%16.16llx"
+ "\n x9=%16.16llx"
+ "\n x10=%16.16llx"
+ "\n x11=%16.16llx"
+ "\n x12=%16.16llx"
+ "\n x13=%16.16llx"
+ "\n x14=%16.16llx"
+ "\n x15=%16.16llx"
+ "\n x16=%16.16llx"
+ "\n x17=%16.16llx"
+ "\n x18=%16.16llx"
+ "\n x19=%16.16llx"
+ "\n x20=%16.16llx"
+ "\n x21=%16.16llx"
+ "\n x22=%16.16llx"
+ "\n x23=%16.16llx"
+ "\n x24=%16.16llx"
+ "\n x25=%16.16llx"
+ "\n x26=%16.16llx"
+ "\n x27=%16.16llx"
+ "\n x28=%16.16llx"
+ "\n fp=%16.16llx"
+ "\n lr=%16.16llx"
+ "\n sp=%16.16llx"
+ "\n pc=%16.16llx"
+ "\n cpsr=%8.8x",
+ m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count,
+ x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11],
+ x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21],
+ x[22], x[23], x[24], x[25], x[26], x[27], x[28],
+ m_state.context.gpr.__fp, m_state.context.gpr.__lr,
+ m_state.context.gpr.__sp, m_state.context.gpr.__pc,
+ m_state.context.gpr.__cpsr);
+ }
+ m_state.SetError(set, Read, kret);
+ return kret;
+}
+
+kern_return_t DNBArchMachARM64::GetVFPState(bool force) {
+ int set = e_regSetVFP;
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ // Read the registers from our thread
+ mach_msg_type_number_t count = e_regSetVFPCount;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64,
+ (thread_state_t)&m_state.context.vfp, &count);
+ if (DNBLogEnabledForAny(LOG_THREAD)) {
+#if defined(__arm64__) || defined(__aarch64__)
+ DNBLogThreaded(
+ "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
+ "\n q0 = 0x%16.16llx%16.16llx"
+ "\n q1 = 0x%16.16llx%16.16llx"
+ "\n q2 = 0x%16.16llx%16.16llx"
+ "\n q3 = 0x%16.16llx%16.16llx"
+ "\n q4 = 0x%16.16llx%16.16llx"
+ "\n q5 = 0x%16.16llx%16.16llx"
+ "\n q6 = 0x%16.16llx%16.16llx"
+ "\n q7 = 0x%16.16llx%16.16llx"
+ "\n q8 = 0x%16.16llx%16.16llx"
+ "\n q9 = 0x%16.16llx%16.16llx"
+ "\n q10 = 0x%16.16llx%16.16llx"
+ "\n q11 = 0x%16.16llx%16.16llx"
+ "\n q12 = 0x%16.16llx%16.16llx"
+ "\n q13 = 0x%16.16llx%16.16llx"
+ "\n q14 = 0x%16.16llx%16.16llx"
+ "\n q15 = 0x%16.16llx%16.16llx"
+ "\n q16 = 0x%16.16llx%16.16llx"
+ "\n q17 = 0x%16.16llx%16.16llx"
+ "\n q18 = 0x%16.16llx%16.16llx"
+ "\n q19 = 0x%16.16llx%16.16llx"
+ "\n q20 = 0x%16.16llx%16.16llx"
+ "\n q21 = 0x%16.16llx%16.16llx"
+ "\n q22 = 0x%16.16llx%16.16llx"
+ "\n q23 = 0x%16.16llx%16.16llx"
+ "\n q24 = 0x%16.16llx%16.16llx"
+ "\n q25 = 0x%16.16llx%16.16llx"
+ "\n q26 = 0x%16.16llx%16.16llx"
+ "\n q27 = 0x%16.16llx%16.16llx"
+ "\n q28 = 0x%16.16llx%16.16llx"
+ "\n q29 = 0x%16.16llx%16.16llx"
+ "\n q30 = 0x%16.16llx%16.16llx"
+ "\n q31 = 0x%16.16llx%16.16llx"
+ "\n fpsr = 0x%8.8x"
+ "\n fpcr = 0x%8.8x\n\n",
+ m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count,
+ ((uint64_t *)&m_state.context.vfp.__v[0])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[0])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[1])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[1])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[2])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[2])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[3])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[3])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[4])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[4])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[5])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[5])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[6])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[6])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[7])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[7])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[8])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[8])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[9])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[9])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[10])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[10])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[11])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[11])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[12])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[12])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[13])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[13])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[14])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[14])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[15])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[15])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[16])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[16])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[17])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[17])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[18])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[18])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[19])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[19])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[20])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[20])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[21])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[21])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[22])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[22])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[23])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[23])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[24])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[24])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[25])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[25])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[26])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[26])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[27])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[27])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[28])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[28])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[29])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[29])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[30])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[30])[1],
+ ((uint64_t *)&m_state.context.vfp.__v[31])[0],
+ ((uint64_t *)&m_state.context.vfp.__v[31])[1],
+ m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
#endif
+ }
+ m_state.SetError(set, Read, kret);
+ return kret;
+}
+
+kern_return_t DNBArchMachARM64::GetEXCState(bool force) {
+ int set = e_regSetEXC;
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ // Read the registers from our thread
+ mach_msg_type_number_t count = e_regSetEXCCount;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64,
+ (thread_state_t)&m_state.context.exc, &count);
+ m_state.SetError(set, Read, kret);
+ return kret;
+}
+
+static void DumpDBGState(const arm_debug_state_t &dbg) {
+ uint32_t i = 0;
+ for (i = 0; i < 16; i++)
+ DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } "
+ "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
+ i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i],
+ dbg.__wcr[i]);
+}
+
+kern_return_t DNBArchMachARM64::GetDBGState(bool force) {
+ int set = e_regSetDBG;
+
+ // Check if we have valid cached registers
+ if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
+ return KERN_SUCCESS;
+
+ // Read the registers from our thread
+ mach_msg_type_number_t count = e_regSetDBGCount;
+ kern_return_t kret =
+ ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64,
+ (thread_state_t)&m_state.dbg, &count);
+ m_state.SetError(set, Read, kret);
+
+ return kret;
+}
+
+kern_return_t DNBArchMachARM64::SetGPRState() {
+ int set = e_regSetGPR;
+ kern_return_t kret = ::thread_set_state(
+ m_thread->MachPortNumber(), ARM_THREAD_STATE64,
+ (thread_state_t)&m_state.context.gpr, e_regSetGPRCount);
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+kern_return_t DNBArchMachARM64::SetVFPState() {
+ int set = e_regSetVFP;
+ kern_return_t kret = ::thread_set_state(
+ m_thread->MachPortNumber(), ARM_NEON_STATE64,
+ (thread_state_t)&m_state.context.vfp, e_regSetVFPCount);
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+kern_return_t DNBArchMachARM64::SetEXCState() {
+ int set = e_regSetEXC;
+ kern_return_t kret = ::thread_set_state(
+ m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64,
+ (thread_state_t)&m_state.context.exc, e_regSetEXCCount);
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+ return kret; // Return the error code
+}
+
+kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) {
+ int set = e_regSetDBG;
+ kern_return_t kret =
+ ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64,
+ (thread_state_t)&m_state.dbg, e_regSetDBGCount);
+ if (also_set_on_task) {
+ kern_return_t task_kret = task_set_state(
+ m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64,
+ (thread_state_t)&m_state.dbg, e_regSetDBGCount);
+ if (task_kret != KERN_SUCCESS)
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed "
+ "to set debug control register state: "
+ "0x%8.8x.",
+ task_kret);
+ }
+ m_state.SetError(set, Write,
+ kret); // Set the current write error for this register set
+ m_state.InvalidateRegisterSetState(set); // Invalidate the current register
+ // state in case registers are read
+ // back differently
+
+ return kret; // Return the error code
+}
+
+void DNBArchMachARM64::ThreadWillResume() {
+ // Do we need to step this thread? If so, let the mach thread tell us so.
+ if (m_thread->IsStepping()) {
+ EnableHardwareSingleStep(true);
+ }
+
+ // Disable the triggered watchpoint temporarily before we resume.
+ // Plus, we try to enable hardware single step to execute past the instruction
+ // which triggered our watchpoint.
+ if (m_watchpoint_did_occur) {
+ if (m_watchpoint_hw_index >= 0) {
+ kern_return_t kret = GetDBGState(false);
+ if (kret == KERN_SUCCESS &&
+ !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) {
+ // The watchpoint might have been disabled by the user. We don't need
+ // to do anything at all
+ // to enable hardware single stepping.
+ m_watchpoint_did_occur = false;
+ m_watchpoint_hw_index = -1;
+ return;
+ }
+
+ DisableHardwareWatchpoint(m_watchpoint_hw_index, false);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
+ "DisableHardwareWatchpoint(%d) called",
+ m_watchpoint_hw_index);
+
+ // Enable hardware single step to move past the watchpoint-triggering
+ // instruction.
+ m_watchpoint_resume_single_step_enabled =
+ (EnableHardwareSingleStep(true) == KERN_SUCCESS);
+
+ // If we are not able to enable single step to move past the
+ // watchpoint-triggering instruction,
+ // at least we should reset the two watchpoint member variables so that
+ // the next time around
+ // this callback function is invoked, the enclosing logical branch is
+ // skipped.
+ if (!m_watchpoint_resume_single_step_enabled) {
+ // Reset the two watchpoint member variables.
+ m_watchpoint_did_occur = false;
+ m_watchpoint_hw_index = -1;
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchMachARM::ThreadWillResume() failed to enable single step");
+ } else
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
+ "succeeded to enable single step");
+ }
+ }
+}
+
+bool DNBArchMachARM64::NotifyException(MachException::Data &exc) {
+
+ switch (exc.exc_type) {
+ default:
+ break;
+ case EXC_BREAKPOINT:
+ if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) {
+ // The data break address is passed as exc_data[1].
+ nub_addr_t addr = exc.exc_data[1];
+ // Find the hardware index with the side effect of possibly massaging the
+ // addr to return the starting address as seen from the debugger side.
+ uint32_t hw_index = GetHardwareWatchpointHit(addr);
+
+ // One logical watchpoint was split into two watchpoint locations because
+ // it was too big. If the watchpoint exception is indicating the 2nd half
+ // of the two-parter, find the address of the 1st half and report that --
+ // that's what lldb is going to expect to see.
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
+ "watchpoint %d was hit on address "
+ "0x%llx",
+ hw_index, (uint64_t)addr);
+ const int num_watchpoints = NumSupportedHardwareWatchpoints();
+ for (int i = 0; i < num_watchpoints; i++) {
+ if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i &&
+ GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) {
+ addr = GetWatchpointAddressByIndex(i);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
+ "It is a linked watchpoint; "
+ "rewritten to index %d addr 0x%llx",
+ LoHi[i], (uint64_t)addr);
+ }
+ }
+
+ if (hw_index != INVALID_NUB_HW_INDEX) {
+ m_watchpoint_did_occur = true;
+ m_watchpoint_hw_index = hw_index;
+ exc.exc_data[1] = addr;
+ // Piggyback the hw_index in the exc.data.
+ exc.exc_data.push_back(hw_index);
+ }
+
+ return true;
+ }
+ break;
+ }
+ return false;
+}
+
+bool DNBArchMachARM64::ThreadDidStop() {
+ bool success = true;
+
+ m_state.InvalidateAllRegisterStates();
+
+ if (m_watchpoint_resume_single_step_enabled) {
+ // Great! We now disable the hardware single step as well as re-enable the
+ // hardware watchpoint.
+ // See also ThreadWillResume().
+ if (EnableHardwareSingleStep(false) == KERN_SUCCESS) {
+ if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) {
+ ReenableHardwareWatchpoint(m_watchpoint_hw_index);
+ m_watchpoint_resume_single_step_enabled = false;
+ m_watchpoint_did_occur = false;
+ m_watchpoint_hw_index = -1;
+ } else {
+ DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
+ "is true but (m_watchpoint_did_occur && "
+ "m_watchpoint_hw_index >= 0) does not hold!");
+ }
+ } else {
+ DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
+ "is true but unable to disable single step!");
+ }
+ }
+
+ // Are we stepping a single instruction?
+ if (GetGPRState(true) == KERN_SUCCESS) {
+ // We are single stepping, was this the primary thread?
+ if (m_thread->IsStepping()) {
+ // This was the primary thread, we need to clear the trace
+ // bit if so.
+ success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
+ } else {
+ // The MachThread will automatically restore the suspend count
+ // in ThreadDidStop(), so we don't need to do anything here if
+ // we weren't the primary thread the last time
}
- m_state.SetError(set, Read, kret);
- return kret;
+ }
+ return success;
}
-kern_return_t
-DNBArchMachARM64::GetEXCState(bool force)
-{
- int set = e_regSetEXC;
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
- mach_msg_type_number_t count = e_regSetEXCCount;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, (thread_state_t)&m_state.context.exc, &count);
- m_state.SetError(set, Read, kret);
- return kret;
-}
-
-static void
-DumpDBGState(const arm_debug_state_t& dbg)
-{
- uint32_t i = 0;
- for (i=0; i<16; i++)
- DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
- i, i, dbg.__bvr[i], dbg.__bcr[i],
- i, i, dbg.__wvr[i], dbg.__wcr[i]);
-}
-
-kern_return_t
-DNBArchMachARM64::GetDBGState(bool force)
-{
- int set = e_regSetDBG;
-
- // Check if we have valid cached registers
- if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
- return KERN_SUCCESS;
-
- // Read the registers from our thread
- mach_msg_type_number_t count = e_regSetDBGCount;
- kern_return_t kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, (thread_state_t)&m_state.dbg, &count);
- m_state.SetError(set, Read, kret);
-
- return kret;
-}
-
-kern_return_t
-DNBArchMachARM64::SetGPRState()
-{
- int set = e_regSetGPR;
- kern_return_t kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, (thread_state_t)&m_state.context.gpr, e_regSetGPRCount);
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-kern_return_t
-DNBArchMachARM64::SetVFPState()
-{
- int set = e_regSetVFP;
- kern_return_t kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_NEON_STATE64, (thread_state_t)&m_state.context.vfp, e_regSetVFPCount);
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-kern_return_t
-DNBArchMachARM64::SetEXCState()
-{
- int set = e_regSetEXC;
- kern_return_t kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, (thread_state_t)&m_state.context.exc, e_regSetEXCCount);
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
- return kret; // Return the error code
-}
-
-kern_return_t
-DNBArchMachARM64::SetDBGState(bool also_set_on_task)
-{
- int set = e_regSetDBG;
- kern_return_t kret = ::thread_set_state (m_thread->MachPortNumber(), ARM_DEBUG_STATE64, (thread_state_t)&m_state.dbg, e_regSetDBGCount);
- if (also_set_on_task)
- {
- kern_return_t task_kret = task_set_state (m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, (thread_state_t)&m_state.dbg, e_regSetDBGCount);
- if (task_kret != KERN_SUCCESS)
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed to set debug control register state: 0x%8.8x.", task_kret);
- }
- m_state.SetError(set, Write, kret); // Set the current write error for this register set
- m_state.InvalidateRegisterSetState(set); // Invalidate the current register state in case registers are read back differently
+// Set the single step bit in the processor status register.
+kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) {
+ DNBError err;
+ DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable);
+
+ err = GetGPRState(false);
+
+ if (err.Fail()) {
+ err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__);
+ return err.Error();
+ }
+
+ err = GetDBGState(false);
+
+ if (err.Fail()) {
+ err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__);
+ return err.Error();
+ }
+
+ if (enable) {
+ DNBLogThreadedIf(LOG_STEP,
+ "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx",
+ __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
+ m_state.dbg.__mdscr_el1 |= SS_ENABLE;
+ } else {
+ DNBLogThreadedIf(LOG_STEP,
+ "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx",
+ __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
+ m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE);
+ }
- return kret; // Return the error code
+ return SetDBGState(false);
}
-void
-DNBArchMachARM64::ThreadWillResume()
-{
- // Do we need to step this thread? If so, let the mach thread tell us so.
- if (m_thread->IsStepping())
- {
- EnableHardwareSingleStep(true);
- }
-
- // Disable the triggered watchpoint temporarily before we resume.
- // Plus, we try to enable hardware single step to execute past the instruction which triggered our watchpoint.
- if (m_watchpoint_did_occur)
- {
- if (m_watchpoint_hw_index >= 0)
- {
- kern_return_t kret = GetDBGState(false);
- if (kret == KERN_SUCCESS && !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) {
- // The watchpoint might have been disabled by the user. We don't need to do anything at all
- // to enable hardware single stepping.
- m_watchpoint_did_occur = false;
- m_watchpoint_hw_index = -1;
- return;
- }
-
- DisableHardwareWatchpoint(m_watchpoint_hw_index, false);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() DisableHardwareWatchpoint(%d) called",
- m_watchpoint_hw_index);
-
- // Enable hardware single step to move past the watchpoint-triggering instruction.
- m_watchpoint_resume_single_step_enabled = (EnableHardwareSingleStep(true) == KERN_SUCCESS);
-
- // If we are not able to enable single step to move past the watchpoint-triggering instruction,
- // at least we should reset the two watchpoint member variables so that the next time around
- // this callback function is invoked, the enclosing logical branch is skipped.
- if (!m_watchpoint_resume_single_step_enabled) {
- // Reset the two watchpoint member variables.
- m_watchpoint_did_occur = false;
- m_watchpoint_hw_index = -1;
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() failed to enable single step");
- }
- else
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() succeeded to enable single step");
- }
- }
+// return 1 if bit "BIT" is set in "value"
+static inline uint32_t bit(uint32_t value, uint32_t bit) {
+ return (value >> bit) & 1u;
}
-bool
-DNBArchMachARM64::NotifyException(MachException::Data& exc)
-{
-
- switch (exc.exc_type)
- {
- default:
- break;
- case EXC_BREAKPOINT:
- if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG)
- {
- // The data break address is passed as exc_data[1].
- nub_addr_t addr = exc.exc_data[1];
- // Find the hardware index with the side effect of possibly massaging the
- // addr to return the starting address as seen from the debugger side.
- uint32_t hw_index = GetHardwareWatchpointHit(addr);
-
- // One logical watchpoint was split into two watchpoint locations because
- // it was too big. If the watchpoint exception is indicating the 2nd half
- // of the two-parter, find the address of the 1st half and report that --
- // that's what lldb is going to expect to see.
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException watchpoint %d was hit on address 0x%llx", hw_index, (uint64_t) addr);
- const int num_watchpoints = NumSupportedHardwareWatchpoints ();
- for (int i = 0; i < num_watchpoints; i++)
- {
- if (LoHi[i] != 0
- && LoHi[i] == hw_index
- && LoHi[i] != i
- && GetWatchpointAddressByIndex (i) != INVALID_NUB_ADDRESS)
- {
- addr = GetWatchpointAddressByIndex (i);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException It is a linked watchpoint; rewritten to index %d addr 0x%llx", LoHi[i], (uint64_t) addr);
- }
- }
-
- if (hw_index != INVALID_NUB_HW_INDEX)
- {
- m_watchpoint_did_occur = true;
- m_watchpoint_hw_index = hw_index;
- exc.exc_data[1] = addr;
- // Piggyback the hw_index in the exc.data.
- exc.exc_data.push_back(hw_index);
- }
-
- return true;
- }
- break;
+// return the bitfield "value[msbit:lsbit]".
+static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) {
+ assert(msbit >= lsbit);
+ uint64_t shift_left = sizeof(value) * 8 - 1 - msbit;
+ value <<=
+ shift_left; // shift anything above the msbit off of the unsigned edge
+ value >>= shift_left + lsbit; // shift it back again down to the lsbit
+ // (including undoing any shift from above)
+ return value; // return our result
+}
+
+uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() {
+ // Set the init value to something that will let us know that we need to
+ // autodetect how many watchpoints are supported dynamically...
+ static uint32_t g_num_supported_hw_watchpoints = UINT_MAX;
+ if (g_num_supported_hw_watchpoints == UINT_MAX) {
+ // Set this to zero in case we can't tell if there are any HW breakpoints
+ g_num_supported_hw_watchpoints = 0;
+
+ size_t len;
+ uint32_t n = 0;
+ len = sizeof(n);
+ if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
+ g_num_supported_hw_watchpoints = n;
+ DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n);
+ } else {
+// For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in
+// EL0 so it can't
+// access that reg. The kernel should have filled in the sysctls based on it
+// though.
+#if defined(__arm__)
+ uint32_t register_DBGDIDR;
+
+ asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
+ uint32_t numWRPs = bits(register_DBGDIDR, 31, 28);
+ // Zero is reserved for the WRP count, so don't increment it if it is zero
+ if (numWRPs > 0)
+ numWRPs++;
+ g_num_supported_hw_watchpoints = numWRPs;
+ DNBLogThreadedIf(LOG_THREAD,
+ "Number of supported hw watchpoints via asm(): %d",
+ g_num_supported_hw_watchpoints);
+#endif
}
- return false;
+ }
+ return g_num_supported_hw_watchpoints;
}
-bool
-DNBArchMachARM64::ThreadDidStop()
-{
- bool success = true;
-
- m_state.InvalidateAllRegisterStates();
+uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr,
+ nub_size_t size, bool read,
+ bool write,
+ bool also_set_on_task) {
+ DNBLogThreadedIf(LOG_WATCHPOINTS,
+ "DNBArchMachARM64::EnableHardwareWatchpoint(addr = "
+ "0x%8.8llx, size = %zu, read = %u, write = %u)",
+ (uint64_t)addr, size, read, write);
- if (m_watchpoint_resume_single_step_enabled)
- {
- // Great! We now disable the hardware single step as well as re-enable the hardware watchpoint.
- // See also ThreadWillResume().
- if (EnableHardwareSingleStep(false) == KERN_SUCCESS)
- {
- if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0)
- {
- ReenableHardwareWatchpoint(m_watchpoint_hw_index);
- m_watchpoint_resume_single_step_enabled = false;
- m_watchpoint_did_occur = false;
- m_watchpoint_hw_index = -1;
- }
- else
- {
- DNBLogError("internal error detected: m_watchpoint_resume_step_enabled is true but (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) does not hold!");
- }
- }
- else
- {
- DNBLogError("internal error detected: m_watchpoint_resume_step_enabled is true but unable to disable single step!");
- }
- }
-
- // Are we stepping a single instruction?
- if (GetGPRState(true) == KERN_SUCCESS)
- {
- // We are single stepping, was this the primary thread?
- if (m_thread->IsStepping())
- {
- // This was the primary thread, we need to clear the trace
- // bit if so.
- success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
- }
- else
- {
- // The MachThread will automatically restore the suspend count
- // in ThreadDidStop(), so we don't need to do anything here if
- // we weren't the primary thread the last time
- }
- }
- return success;
-}
+ const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
-// Set the single step bit in the processor status register.
-kern_return_t
-DNBArchMachARM64::EnableHardwareSingleStep (bool enable)
-{
- DNBError err;
- DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable);
-
- err = GetGPRState(false);
-
- if (err.Fail())
- {
- err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__);
- return err.Error();
- }
+ // Can't watch zero bytes
+ if (size == 0)
+ return INVALID_NUB_HW_INDEX;
- err = GetDBGState(false);
+ // We must watch for either read or write
+ if (read == false && write == false)
+ return INVALID_NUB_HW_INDEX;
- if (err.Fail())
- {
- err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__);
- return err.Error();
- }
+ // Otherwise, can't watch more than 8 bytes per WVR/WCR pair
+ if (size > 8)
+ return INVALID_NUB_HW_INDEX;
- if (enable)
- {
- DNBLogThreadedIf(LOG_STEP, "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", __FUNCTION__, (uint64_t) m_state.context.gpr.__pc);
- m_state.dbg.__mdscr_el1 |= SS_ENABLE;
- }
- else
- {
- DNBLogThreadedIf(LOG_STEP, "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", __FUNCTION__, (uint64_t) m_state.context.gpr.__pc);
- m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE);
- }
+ // arm64 watchpoints really have an 8-byte alignment requirement. You can put
+ // a watchpoint on a 4-byte
+ // offset address but you can only watch 4 bytes with that watchpoint.
+
+ // arm64 watchpoints on an 8-byte (double word) aligned addr can watch any
+ // bytes in that
+ // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte,
+ // 3rd byte, etc, or any
+ // combination therein by setting the bits in the BAS [12:5] (Byte Address
+ // Select) field of
+ // the DBGWCRn_EL1 reg for the watchpoint.
+
+ // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to
+ // monitor a larger region
+ // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield
+ // then selects a larger
+ // range of bytes, instead of individual bytes. See the ARMv8 Debug
+ // Architecture manual for details.
+ // This implementation does not currently use the MASK bits; the largest
+ // single region watched by a single
+ // watchpoint right now is 8-bytes.
+
+ nub_addr_t aligned_wp_address = addr & ~0x7;
+ uint32_t addr_dword_offset = addr & 0x7;
+
+ // Do we need to split up this logical watchpoint into two hardware watchpoint
+ // registers?
+ // e.g. a watchpoint of length 4 on address 6. We need do this with
+ // one watchpoint on address 0 with bytes 6 & 7 being monitored
+ // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored
+
+ if (addr_dword_offset + size > 8) {
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::"
+ "EnableHardwareWatchpoint(addr = "
+ "0x%8.8llx, size = %zu) needs two "
+ "hardware watchpoints slots to monitor",
+ (uint64_t)addr, size);
+ int low_watchpoint_size = 8 - addr_dword_offset;
+ int high_watchpoint_size = addr_dword_offset + size - 8;
+
+ uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read,
+ write, also_set_on_task);
+ if (lo == INVALID_NUB_HW_INDEX)
+ return INVALID_NUB_HW_INDEX;
+ uint32_t hi =
+ EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size,
+ read, write, also_set_on_task);
+ if (hi == INVALID_NUB_HW_INDEX) {
+ DisableHardwareWatchpoint(lo, also_set_on_task);
+ return INVALID_NUB_HW_INDEX;
+ }
+ // Tag this lo->hi mapping in our database.
+ LoHi[lo] = hi;
+ return lo;
+ }
+
+ // At this point
+ // 1 aligned_wp_address is the requested address rounded down to 8-byte
+ // alignment
+ // 2 addr_dword_offset is the offset into that double word (8-byte) region
+ // that we are watching
+ // 3 size is the number of bytes within that 8-byte region that we are
+ // watching
+
+ // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the
+ // above.
+ // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4,
+ // etc, up to 0b11111111 for 8.
+ // then we shift those bits left by the offset into this dword that we are
+ // interested in.
+ // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of
+ // 0b11110000.
+ uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset;
- return SetDBGState(false);
-}
+ // Read the debug state
+ kern_return_t kret = GetDBGState(false);
-// return 1 if bit "BIT" is set in "value"
-static inline uint32_t bit(uint32_t value, uint32_t bit)
-{
- return (value >> bit) & 1u;
-}
+ if (kret == KERN_SUCCESS) {
+ // Check to make sure we have the needed hardware support
+ uint32_t i = 0;
-// return the bitfield "value[msbit:lsbit]".
-static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit)
-{
- assert(msbit >= lsbit);
- uint64_t shift_left = sizeof(value) * 8 - 1 - msbit;
- value <<= shift_left; // shift anything above the msbit off of the unsigned edge
- value >>= shift_left + lsbit; // shift it back again down to the lsbit (including undoing any shift from above)
- return value; // return our result
-}
-
-uint32_t
-DNBArchMachARM64::NumSupportedHardwareWatchpoints()
-{
- // Set the init value to something that will let us know that we need to
- // autodetect how many watchpoints are supported dynamically...
- static uint32_t g_num_supported_hw_watchpoints = UINT_MAX;
- if (g_num_supported_hw_watchpoints == UINT_MAX)
- {
- // Set this to zero in case we can't tell if there are any HW breakpoints
- g_num_supported_hw_watchpoints = 0;
-
-
- size_t len;
- uint32_t n = 0;
- len = sizeof (n);
- if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0)
- {
- g_num_supported_hw_watchpoints = n;
- DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n);
- }
- else
- {
- // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in EL0 so it can't
- // access that reg. The kernel should have filled in the sysctls based on it though.
-#if defined (__arm__)
- uint32_t register_DBGDIDR;
-
- asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
- uint32_t numWRPs = bits(register_DBGDIDR, 31, 28);
- // Zero is reserved for the WRP count, so don't increment it if it is zero
- if (numWRPs > 0)
- numWRPs++;
- g_num_supported_hw_watchpoints = numWRPs;
- DNBLogThreadedIf(LOG_THREAD, "Number of supported hw watchpoints via asm(): %d", g_num_supported_hw_watchpoints);
-#endif
- }
- }
- return g_num_supported_hw_watchpoints;
-}
+ for (i = 0; i < num_hw_watchpoints; ++i) {
+ if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0)
+ break; // We found an available hw watchpoint slot (in i)
+ }
+
+ // See if we found an available hw watchpoint slot above
+ if (i < num_hw_watchpoints) {
+ // DumpDBGState(m_state.dbg);
+
+ // Clear any previous LoHi joined-watchpoint that may have been in use
+ LoHi[i] = 0;
+
+ // shift our Byte Address Select bits up to the correct bit range for the
+ // DBGWCRn_EL1
+ byte_address_select = byte_address_select << 5;
+
+ // Make sure bits 1:0 are clear in our address
+ m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address)
+ m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow
+ // the DVA that we will watch
+ S_USER | // Stop only in user mode
+ (read ? WCR_LOAD : 0) | // Stop on read access?
+ (write ? WCR_STORE : 0) | // Stop on write access?
+ WCR_ENABLE; // Enable this watchpoint;
+
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() "
+ "adding watchpoint on address 0x%llx with control "
+ "register value 0x%x",
+ (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]);
+
+ // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
+ // automatically, don't need to do it here.
+
+ kret = SetDBGState(also_set_on_task);
+ // DumpDBGState(m_state.dbg);
+
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::"
+ "EnableHardwareWatchpoint() "
+ "SetDBGState() => 0x%8.8x.",
+ kret);
+
+ if (kret == KERN_SUCCESS)
+ return i;
+ } else {
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::"
+ "EnableHardwareWatchpoint(): All "
+ "hardware resources (%u) are in use.",
+ num_hw_watchpoints);
+ }
+ }
+ return INVALID_NUB_HW_INDEX;
+}
+
+bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) {
+ // If this logical watchpoint # is actually implemented using
+ // two hardware watchpoint registers, re-enable both of them.
+
+ if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
+ return ReenableHardwareWatchpoint_helper(hw_index) &&
+ ReenableHardwareWatchpoint_helper(LoHi[hw_index]);
+ } else {
+ return ReenableHardwareWatchpoint_helper(hw_index);
+ }
+}
+
+bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) {
+ kern_return_t kret = GetDBGState(false);
+ if (kret != KERN_SUCCESS)
+ return false;
-uint32_t
-DNBArchMachARM64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task)
-{
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint(addr = 0x%8.8llx, size = %zu, read = %u, write = %u)", (uint64_t)addr, size, read, write);
-
- const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
-
- // Can't watch zero bytes
- if (size == 0)
- return INVALID_NUB_HW_INDEX;
-
- // We must watch for either read or write
- if (read == false && write == false)
- return INVALID_NUB_HW_INDEX;
-
- // Otherwise, can't watch more than 8 bytes per WVR/WCR pair
- if (size > 8)
- return INVALID_NUB_HW_INDEX;
-
- // arm64 watchpoints really have an 8-byte alignment requirement. You can put a watchpoint on a 4-byte
- // offset address but you can only watch 4 bytes with that watchpoint.
-
- // arm64 watchpoints on an 8-byte (double word) aligned addr can watch any bytes in that
- // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 3rd byte, etc, or any
- // combination therein by setting the bits in the BAS [12:5] (Byte Address Select) field of
- // the DBGWCRn_EL1 reg for the watchpoint.
-
- // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to monitor a larger region
- // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield then selects a larger
- // range of bytes, instead of individual bytes. See the ARMv8 Debug Architecture manual for details.
- // This implementation does not currently use the MASK bits; the largest single region watched by a single
- // watchpoint right now is 8-bytes.
-
- nub_addr_t aligned_wp_address = addr & ~0x7;
- uint32_t addr_dword_offset = addr & 0x7;
-
- // Do we need to split up this logical watchpoint into two hardware watchpoint
- // registers?
- // e.g. a watchpoint of length 4 on address 6. We need do this with
- // one watchpoint on address 0 with bytes 6 & 7 being monitored
- // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored
-
- if (addr_dword_offset + size > 8)
- {
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint(addr = 0x%8.8llx, size = %zu) needs two hardware watchpoints slots to monitor", (uint64_t)addr, size);
- int low_watchpoint_size = 8 - addr_dword_offset;
- int high_watchpoint_size = addr_dword_offset + size - 8;
-
- uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, write, also_set_on_task);
- if (lo == INVALID_NUB_HW_INDEX)
- return INVALID_NUB_HW_INDEX;
- uint32_t hi = EnableHardwareWatchpoint (aligned_wp_address + 8, high_watchpoint_size, read, write, also_set_on_task);
- if (hi == INVALID_NUB_HW_INDEX)
- {
- DisableHardwareWatchpoint (lo, also_set_on_task);
- return INVALID_NUB_HW_INDEX;
- }
- // Tag this lo->hi mapping in our database.
- LoHi[lo] = hi;
- return lo;
- }
+ const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
+ if (hw_index >= num_hw_points)
+ return false;
- // At this point
- // 1 aligned_wp_address is the requested address rounded down to 8-byte alignment
- // 2 addr_dword_offset is the offset into that double word (8-byte) region that we are watching
- // 3 size is the number of bytes within that 8-byte region that we are watching
-
- // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the above.
- // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, etc, up to 0b11111111 for 8.
- // then we shift those bits left by the offset into this dword that we are interested in.
- // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 0b11110000.
- uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset;
-
- // Read the debug state
- kern_return_t kret = GetDBGState(false);
-
- if (kret == KERN_SUCCESS)
- {
- // Check to make sure we have the needed hardware support
- uint32_t i = 0;
-
- for (i=0; i<num_hw_watchpoints; ++i)
- {
- if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0)
- break; // We found an available hw watchpoint slot (in i)
- }
+ m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr;
+ m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control;
- // See if we found an available hw watchpoint slot above
- if (i < num_hw_watchpoints)
- {
- //DumpDBGState(m_state.dbg);
-
- // Clear any previous LoHi joined-watchpoint that may have been in use
- LoHi[i] = 0;
-
- // shift our Byte Address Select bits up to the correct bit range for the DBGWCRn_EL1
- byte_address_select = byte_address_select << 5;
-
- // Make sure bits 1:0 are clear in our address
- m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address)
- m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow the DVA that we will watch
- S_USER | // Stop only in user mode
- (read ? WCR_LOAD : 0) | // Stop on read access?
- (write ? WCR_STORE : 0) | // Stop on write access?
- WCR_ENABLE; // Enable this watchpoint;
-
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() adding watchpoint on address 0x%llx with control register value 0x%x", (uint64_t) m_state.dbg.__wvr[i], (uint32_t) m_state.dbg.__wcr[i]);
-
- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us automatically, don't need to do it here.
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::"
+ "EnableHardwareWatchpoint( %u ) - WVR%u = "
+ "0x%8.8llx WCR%u = 0x%8.8llx",
+ hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
+ hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
- kret = SetDBGState(also_set_on_task);
- //DumpDBGState(m_state.dbg);
+ // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
+ // automatically, don't need to do it here.
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret);
+ kret = SetDBGState(false);
- if (kret == KERN_SUCCESS)
- return i;
- }
- else
- {
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
- }
- }
- return INVALID_NUB_HW_INDEX;
+ return (kret == KERN_SUCCESS);
}
-bool
-DNBArchMachARM64::ReenableHardwareWatchpoint (uint32_t hw_index)
-{
- // If this logical watchpoint # is actually implemented using
- // two hardware watchpoint registers, re-enable both of them.
-
- if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index])
- {
- return ReenableHardwareWatchpoint_helper (hw_index) && ReenableHardwareWatchpoint_helper (LoHi[hw_index]);
- }
- else
- {
- return ReenableHardwareWatchpoint_helper (hw_index);
- }
+bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index,
+ bool also_set_on_task) {
+ if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
+ return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) &&
+ DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task);
+ } else {
+ return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task);
+ }
}
-bool
-DNBArchMachARM64::ReenableHardwareWatchpoint_helper (uint32_t hw_index)
-{
- kern_return_t kret = GetDBGState(false);
- if (kret != KERN_SUCCESS)
- return false;
-
- const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
- if (hw_index >= num_hw_points)
- return false;
-
- m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr;
- m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control;
-
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint( %u ) - WVR%u = 0x%8.8llx WCR%u = 0x%8.8llx",
- hw_index,
- hw_index,
- (uint64_t) m_state.dbg.__wvr[hw_index],
- hw_index,
- (uint64_t) m_state.dbg.__wcr[hw_index]);
-
- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us automatically, don't need to do it here.
-
- kret = SetDBGState(false);
-
- return (kret == KERN_SUCCESS);
-}
-
-bool
-DNBArchMachARM64::DisableHardwareWatchpoint (uint32_t hw_index, bool also_set_on_task)
-{
- if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index])
- {
- return DisableHardwareWatchpoint_helper (hw_index, also_set_on_task) && DisableHardwareWatchpoint_helper (LoHi[hw_index], also_set_on_task);
- }
- else
- {
- return DisableHardwareWatchpoint_helper (hw_index, also_set_on_task);
- }
-}
+bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index,
+ bool also_set_on_task) {
+ kern_return_t kret = GetDBGState(false);
+ if (kret != KERN_SUCCESS)
+ return false;
-bool
-DNBArchMachARM64::DisableHardwareWatchpoint_helper (uint32_t hw_index, bool also_set_on_task)
-{
- kern_return_t kret = GetDBGState(false);
- if (kret != KERN_SUCCESS)
- return false;
-
- const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
- if (hw_index >= num_hw_points)
- return false;
-
- m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index];
- m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index];
-
- m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::DisableHardwareWatchpoint( %u ) - WVR%u = 0x%8.8llx WCR%u = 0x%8.8llx",
- hw_index,
- hw_index,
- (uint64_t) m_state.dbg.__wvr[hw_index],
- hw_index,
- (uint64_t) m_state.dbg.__wcr[hw_index]);
+ const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
+ if (hw_index >= num_hw_points)
+ return false;
+
+ m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index];
+ m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index];
+
+ m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::"
+ "DisableHardwareWatchpoint( %u ) - WVR%u = "
+ "0x%8.8llx WCR%u = 0x%8.8llx",
+ hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
+ hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
- kret = SetDBGState(also_set_on_task);
+ kret = SetDBGState(also_set_on_task);
- return (kret == KERN_SUCCESS);
+ return (kret == KERN_SUCCESS);
}
-// This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control register.
+// This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control
+// register.
// Returns -1 if the trailing bit patterns are not one of:
-// { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 0b?1000000, 0b10000000 }.
-static inline
-int32_t
-LowestBitSet(uint32_t val)
-{
- for (unsigned i = 0; i < 8; ++i) {
- if (bit(val, i))
- return i;
- }
- return -1;
+// { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000,
+// 0b?1000000, 0b10000000 }.
+static inline int32_t LowestBitSet(uint32_t val) {
+ for (unsigned i = 0; i < 8; ++i) {
+ if (bit(val, i))
+ return i;
+ }
+ return -1;
}
-// Iterate through the debug registers; return the index of the first watchpoint whose address matches.
-// As a side effect, the starting address as understood by the debugger is returned which could be
+// Iterate through the debug registers; return the index of the first watchpoint
+// whose address matches.
+// As a side effect, the starting address as understood by the debugger is
+// returned which could be
// different from 'addr' passed as an in/out argument.
-uint32_t
-DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr)
-{
- // Read the debug state
- kern_return_t kret = GetDBGState(true);
- //DumpDBGState(m_state.dbg);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", (uint64_t)addr);
-
- // This is the watchpoint value to match against, i.e., word address.
- nub_addr_t wp_val = addr & ~((nub_addr_t)3);
- if (kret == KERN_SUCCESS)
- {
- DBG &debug_state = m_state.dbg;
- uint32_t i, num = NumSupportedHardwareWatchpoints();
- for (i = 0; i < num; ++i)
- {
- nub_addr_t wp_addr = GetWatchAddress(debug_state, i);
- DNBLogThreadedIf(LOG_WATCHPOINTS,
- "DNBArchMachARM64::GetHardwareWatchpointHit() slot: %u (addr = 0x%llx).",
- i, (uint64_t)wp_addr);
- if (wp_val == wp_addr) {
- uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5);
-
- // Sanity check the byte_mask, first.
- if (LowestBitSet(byte_mask) < 0)
- continue;
-
- // Check that the watchpoint is enabled.
- if (!IsWatchpointEnabled(debug_state, i))
- continue;
-
- // Compute the starting address (from the point of view of the debugger).
- addr = wp_addr + LowestBitSet(byte_mask);
- return i;
- }
- }
- }
- return INVALID_NUB_HW_INDEX;
-}
-
-nub_addr_t
-DNBArchMachARM64::GetWatchpointAddressByIndex (uint32_t hw_index)
-{
- kern_return_t kret = GetDBGState(true);
- if (kret != KERN_SUCCESS)
- return INVALID_NUB_ADDRESS;
- const uint32_t num = NumSupportedHardwareWatchpoints();
- if (hw_index >= num)
- return INVALID_NUB_ADDRESS;
- if (IsWatchpointEnabled (m_state.dbg, hw_index))
- return GetWatchAddress (m_state.dbg, hw_index);
+uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) {
+ // Read the debug state
+ kern_return_t kret = GetDBGState(true);
+ // DumpDBGState(m_state.dbg);
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.",
+ kret);
+ DNBLogThreadedIf(LOG_WATCHPOINTS,
+ "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx",
+ (uint64_t)addr);
+
+ // This is the watchpoint value to match against, i.e., word address.
+ nub_addr_t wp_val = addr & ~((nub_addr_t)3);
+ if (kret == KERN_SUCCESS) {
+ DBG &debug_state = m_state.dbg;
+ uint32_t i, num = NumSupportedHardwareWatchpoints();
+ for (i = 0; i < num; ++i) {
+ nub_addr_t wp_addr = GetWatchAddress(debug_state, i);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::"
+ "GetHardwareWatchpointHit() slot: %u "
+ "(addr = 0x%llx).",
+ i, (uint64_t)wp_addr);
+ if (wp_val == wp_addr) {
+ uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5);
+
+ // Sanity check the byte_mask, first.
+ if (LowestBitSet(byte_mask) < 0)
+ continue;
+
+ // Check that the watchpoint is enabled.
+ if (!IsWatchpointEnabled(debug_state, i))
+ continue;
+
+ // Compute the starting address (from the point of view of the
+ // debugger).
+ addr = wp_addr + LowestBitSet(byte_mask);
+ return i;
+ }
+ }
+ }
+ return INVALID_NUB_HW_INDEX;
+}
+
+nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) {
+ kern_return_t kret = GetDBGState(true);
+ if (kret != KERN_SUCCESS)
return INVALID_NUB_ADDRESS;
-}
-
-bool
-DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, uint32_t hw_index)
-{
- // Watchpoint Control Registers, bitfield definitions
- // ...
- // Bits Value Description
- // [0] 0 Watchpoint disabled
- // 1 Watchpoint enabled.
- return (debug_state.__wcr[hw_index] & 1u);
-}
-
-nub_addr_t
-DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, uint32_t hw_index)
-{
- // Watchpoint Value Registers, bitfield definitions
- // Bits Description
- // [31:2] Watchpoint value (word address, i.e., 4-byte aligned)
- // [1:0] RAZ/SBZP
- return bits(debug_state.__wvr[hw_index], 63, 0);
+ const uint32_t num = NumSupportedHardwareWatchpoints();
+ if (hw_index >= num)
+ return INVALID_NUB_ADDRESS;
+ if (IsWatchpointEnabled(m_state.dbg, hw_index))
+ return GetWatchAddress(m_state.dbg, hw_index);
+ return INVALID_NUB_ADDRESS;
+}
+
+bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state,
+ uint32_t hw_index) {
+ // Watchpoint Control Registers, bitfield definitions
+ // ...
+ // Bits Value Description
+ // [0] 0 Watchpoint disabled
+ // 1 Watchpoint enabled.
+ return (debug_state.__wcr[hw_index] & 1u);
+}
+
+nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state,
+ uint32_t hw_index) {
+ // Watchpoint Value Registers, bitfield definitions
+ // Bits Description
+ // [31:2] Watchpoint value (word address, i.e., 4-byte aligned)
+ // [1:0] RAZ/SBZP
+ return bits(debug_state.__wvr[hw_index], 63, 0);
}
//----------------------------------------------------------------------
// Register information definitions for 64 bit ARMv8.
//----------------------------------------------------------------------
-enum gpr_regnums
-{
- gpr_x0 = 0,
- gpr_x1,
- gpr_x2,
- gpr_x3,
- gpr_x4,
- gpr_x5,
- gpr_x6,
- gpr_x7,
- gpr_x8,
- gpr_x9,
- gpr_x10,
- gpr_x11,
- gpr_x12,
- gpr_x13,
- gpr_x14,
- gpr_x15,
- gpr_x16,
- gpr_x17,
- gpr_x18,
- gpr_x19,
- gpr_x20,
- gpr_x21,
- gpr_x22,
- gpr_x23,
- gpr_x24,
- gpr_x25,
- gpr_x26,
- gpr_x27,
- gpr_x28,
- gpr_fp, gpr_x29 = gpr_fp,
- gpr_lr, gpr_x30 = gpr_lr,
- gpr_sp, gpr_x31 = gpr_sp,
- gpr_pc,
- gpr_cpsr,
- gpr_w0,
- gpr_w1,
- gpr_w2,
- gpr_w3,
- gpr_w4,
- gpr_w5,
- gpr_w6,
- gpr_w7,
- gpr_w8,
- gpr_w9,
- gpr_w10,
- gpr_w11,
- gpr_w12,
- gpr_w13,
- gpr_w14,
- gpr_w15,
- gpr_w16,
- gpr_w17,
- gpr_w18,
- gpr_w19,
- gpr_w20,
- gpr_w21,
- gpr_w22,
- gpr_w23,
- gpr_w24,
- gpr_w25,
- gpr_w26,
- gpr_w27,
- gpr_w28
+enum gpr_regnums {
+ gpr_x0 = 0,
+ gpr_x1,
+ gpr_x2,
+ gpr_x3,
+ gpr_x4,
+ gpr_x5,
+ gpr_x6,
+ gpr_x7,
+ gpr_x8,
+ gpr_x9,
+ gpr_x10,
+ gpr_x11,
+ gpr_x12,
+ gpr_x13,
+ gpr_x14,
+ gpr_x15,
+ gpr_x16,
+ gpr_x17,
+ gpr_x18,
+ gpr_x19,
+ gpr_x20,
+ gpr_x21,
+ gpr_x22,
+ gpr_x23,
+ gpr_x24,
+ gpr_x25,
+ gpr_x26,
+ gpr_x27,
+ gpr_x28,
+ gpr_fp,
+ gpr_x29 = gpr_fp,
+ gpr_lr,
+ gpr_x30 = gpr_lr,
+ gpr_sp,
+ gpr_x31 = gpr_sp,
+ gpr_pc,
+ gpr_cpsr,
+ gpr_w0,
+ gpr_w1,
+ gpr_w2,
+ gpr_w3,
+ gpr_w4,
+ gpr_w5,
+ gpr_w6,
+ gpr_w7,
+ gpr_w8,
+ gpr_w9,
+ gpr_w10,
+ gpr_w11,
+ gpr_w12,
+ gpr_w13,
+ gpr_w14,
+ gpr_w15,
+ gpr_w16,
+ gpr_w17,
+ gpr_w18,
+ gpr_w19,
+ gpr_w20,
+ gpr_w21,
+ gpr_w22,
+ gpr_w23,
+ gpr_w24,
+ gpr_w25,
+ gpr_w26,
+ gpr_w27,
+ gpr_w28
};
-enum
-{
- vfp_v0 = 0,
- vfp_v1,
- vfp_v2,
- vfp_v3,
- vfp_v4,
- vfp_v5,
- vfp_v6,
- vfp_v7,
- vfp_v8,
- vfp_v9,
- vfp_v10,
- vfp_v11,
- vfp_v12,
- vfp_v13,
- vfp_v14,
- vfp_v15,
- vfp_v16,
- vfp_v17,
- vfp_v18,
- vfp_v19,
- vfp_v20,
- vfp_v21,
- vfp_v22,
- vfp_v23,
- vfp_v24,
- vfp_v25,
- vfp_v26,
- vfp_v27,
- vfp_v28,
- vfp_v29,
- vfp_v30,
- vfp_v31,
- vfp_fpsr,
- vfp_fpcr,
-
- // lower 32 bits of the corresponding vfp_v<n> reg.
- vfp_s0,
- vfp_s1,
- vfp_s2,
- vfp_s3,
- vfp_s4,
- vfp_s5,
- vfp_s6,
- vfp_s7,
- vfp_s8,
- vfp_s9,
- vfp_s10,
- vfp_s11,
- vfp_s12,
- vfp_s13,
- vfp_s14,
- vfp_s15,
- vfp_s16,
- vfp_s17,
- vfp_s18,
- vfp_s19,
- vfp_s20,
- vfp_s21,
- vfp_s22,
- vfp_s23,
- vfp_s24,
- vfp_s25,
- vfp_s26,
- vfp_s27,
- vfp_s28,
- vfp_s29,
- vfp_s30,
- vfp_s31,
-
- // lower 64 bits of the corresponding vfp_v<n> reg.
- vfp_d0,
- vfp_d1,
- vfp_d2,
- vfp_d3,
- vfp_d4,
- vfp_d5,
- vfp_d6,
- vfp_d7,
- vfp_d8,
- vfp_d9,
- vfp_d10,
- vfp_d11,
- vfp_d12,
- vfp_d13,
- vfp_d14,
- vfp_d15,
- vfp_d16,
- vfp_d17,
- vfp_d18,
- vfp_d19,
- vfp_d20,
- vfp_d21,
- vfp_d22,
- vfp_d23,
- vfp_d24,
- vfp_d25,
- vfp_d26,
- vfp_d27,
- vfp_d28,
- vfp_d29,
- vfp_d30,
- vfp_d31
+enum {
+ vfp_v0 = 0,
+ vfp_v1,
+ vfp_v2,
+ vfp_v3,
+ vfp_v4,
+ vfp_v5,
+ vfp_v6,
+ vfp_v7,
+ vfp_v8,
+ vfp_v9,
+ vfp_v10,
+ vfp_v11,
+ vfp_v12,
+ vfp_v13,
+ vfp_v14,
+ vfp_v15,
+ vfp_v16,
+ vfp_v17,
+ vfp_v18,
+ vfp_v19,
+ vfp_v20,
+ vfp_v21,
+ vfp_v22,
+ vfp_v23,
+ vfp_v24,
+ vfp_v25,
+ vfp_v26,
+ vfp_v27,
+ vfp_v28,
+ vfp_v29,
+ vfp_v30,
+ vfp_v31,
+ vfp_fpsr,
+ vfp_fpcr,
+
+ // lower 32 bits of the corresponding vfp_v<n> reg.
+ vfp_s0,
+ vfp_s1,
+ vfp_s2,
+ vfp_s3,
+ vfp_s4,
+ vfp_s5,
+ vfp_s6,
+ vfp_s7,
+ vfp_s8,
+ vfp_s9,
+ vfp_s10,
+ vfp_s11,
+ vfp_s12,
+ vfp_s13,
+ vfp_s14,
+ vfp_s15,
+ vfp_s16,
+ vfp_s17,
+ vfp_s18,
+ vfp_s19,
+ vfp_s20,
+ vfp_s21,
+ vfp_s22,
+ vfp_s23,
+ vfp_s24,
+ vfp_s25,
+ vfp_s26,
+ vfp_s27,
+ vfp_s28,
+ vfp_s29,
+ vfp_s30,
+ vfp_s31,
+
+ // lower 64 bits of the corresponding vfp_v<n> reg.
+ vfp_d0,
+ vfp_d1,
+ vfp_d2,
+ vfp_d3,
+ vfp_d4,
+ vfp_d5,
+ vfp_d6,
+ vfp_d7,
+ vfp_d8,
+ vfp_d9,
+ vfp_d10,
+ vfp_d11,
+ vfp_d12,
+ vfp_d13,
+ vfp_d14,
+ vfp_d15,
+ vfp_d16,
+ vfp_d17,
+ vfp_d18,
+ vfp_d19,
+ vfp_d20,
+ vfp_d21,
+ vfp_d22,
+ vfp_d23,
+ vfp_d24,
+ vfp_d25,
+ vfp_d26,
+ vfp_d27,
+ vfp_d28,
+ vfp_d29,
+ vfp_d30,
+ vfp_d31
};
-enum
-{
- exc_far = 0,
- exc_esr,
- exc_exception
-};
+enum { exc_far = 0, exc_esr, exc_exception };
-// These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" document.
+// These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)"
+// document.
-enum
-{
- dwarf_x0 = 0,
- dwarf_x1,
- dwarf_x2,
- dwarf_x3,
- dwarf_x4,
- dwarf_x5,
- dwarf_x6,
- dwarf_x7,
- dwarf_x8,
- dwarf_x9,
- dwarf_x10,
- dwarf_x11,
- dwarf_x12,
- dwarf_x13,
- dwarf_x14,
- dwarf_x15,
- dwarf_x16,
- dwarf_x17,
- dwarf_x18,
- dwarf_x19,
- dwarf_x20,
- dwarf_x21,
- dwarf_x22,
- dwarf_x23,
- dwarf_x24,
- dwarf_x25,
- dwarf_x26,
- dwarf_x27,
- dwarf_x28,
- dwarf_x29,
- dwarf_x30,
- dwarf_x31,
- dwarf_pc = 32,
- dwarf_elr_mode = 33,
- dwarf_fp = dwarf_x29,
- dwarf_lr = dwarf_x30,
- dwarf_sp = dwarf_x31,
- // 34-63 reserved
-
- // V0-V31 (128 bit vector registers)
- dwarf_v0 = 64,
- dwarf_v1,
- dwarf_v2,
- dwarf_v3,
- dwarf_v4,
- dwarf_v5,
- dwarf_v6,
- dwarf_v7,
- dwarf_v8,
- dwarf_v9,
- dwarf_v10,
- dwarf_v11,
- dwarf_v12,
- dwarf_v13,
- dwarf_v14,
- dwarf_v15,
- dwarf_v16,
- dwarf_v17,
- dwarf_v18,
- dwarf_v19,
- dwarf_v20,
- dwarf_v21,
- dwarf_v22,
- dwarf_v23,
- dwarf_v24,
- dwarf_v25,
- dwarf_v26,
- dwarf_v27,
- dwarf_v28,
- dwarf_v29,
- dwarf_v30,
- dwarf_v31
-
- // 96-127 reserved
+enum {
+ dwarf_x0 = 0,
+ dwarf_x1,
+ dwarf_x2,
+ dwarf_x3,
+ dwarf_x4,
+ dwarf_x5,
+ dwarf_x6,
+ dwarf_x7,
+ dwarf_x8,
+ dwarf_x9,
+ dwarf_x10,
+ dwarf_x11,
+ dwarf_x12,
+ dwarf_x13,
+ dwarf_x14,
+ dwarf_x15,
+ dwarf_x16,
+ dwarf_x17,
+ dwarf_x18,
+ dwarf_x19,
+ dwarf_x20,
+ dwarf_x21,
+ dwarf_x22,
+ dwarf_x23,
+ dwarf_x24,
+ dwarf_x25,
+ dwarf_x26,
+ dwarf_x27,
+ dwarf_x28,
+ dwarf_x29,
+ dwarf_x30,
+ dwarf_x31,
+ dwarf_pc = 32,
+ dwarf_elr_mode = 33,
+ dwarf_fp = dwarf_x29,
+ dwarf_lr = dwarf_x30,
+ dwarf_sp = dwarf_x31,
+ // 34-63 reserved
+
+ // V0-V31 (128 bit vector registers)
+ dwarf_v0 = 64,
+ dwarf_v1,
+ dwarf_v2,
+ dwarf_v3,
+ dwarf_v4,
+ dwarf_v5,
+ dwarf_v6,
+ dwarf_v7,
+ dwarf_v8,
+ dwarf_v9,
+ dwarf_v10,
+ dwarf_v11,
+ dwarf_v12,
+ dwarf_v13,
+ dwarf_v14,
+ dwarf_v15,
+ dwarf_v16,
+ dwarf_v17,
+ dwarf_v18,
+ dwarf_v19,
+ dwarf_v20,
+ dwarf_v21,
+ dwarf_v22,
+ dwarf_v23,
+ dwarf_v24,
+ dwarf_v25,
+ dwarf_v26,
+ dwarf_v27,
+ dwarf_v28,
+ dwarf_v29,
+ dwarf_v30,
+ dwarf_v31
+
+ // 96-127 reserved
};
-enum
-{
- debugserver_gpr_x0 = 0,
- debugserver_gpr_x1,
- debugserver_gpr_x2,
- debugserver_gpr_x3,
- debugserver_gpr_x4,
- debugserver_gpr_x5,
- debugserver_gpr_x6,
- debugserver_gpr_x7,
- debugserver_gpr_x8,
- debugserver_gpr_x9,
- debugserver_gpr_x10,
- debugserver_gpr_x11,
- debugserver_gpr_x12,
- debugserver_gpr_x13,
- debugserver_gpr_x14,
- debugserver_gpr_x15,
- debugserver_gpr_x16,
- debugserver_gpr_x17,
- debugserver_gpr_x18,
- debugserver_gpr_x19,
- debugserver_gpr_x20,
- debugserver_gpr_x21,
- debugserver_gpr_x22,
- debugserver_gpr_x23,
- debugserver_gpr_x24,
- debugserver_gpr_x25,
- debugserver_gpr_x26,
- debugserver_gpr_x27,
- debugserver_gpr_x28,
- debugserver_gpr_fp, // x29
- debugserver_gpr_lr, // x30
- debugserver_gpr_sp, // sp aka xsp
- debugserver_gpr_pc,
- debugserver_gpr_cpsr,
- debugserver_vfp_v0,
- debugserver_vfp_v1,
- debugserver_vfp_v2,
- debugserver_vfp_v3,
- debugserver_vfp_v4,
- debugserver_vfp_v5,
- debugserver_vfp_v6,
- debugserver_vfp_v7,
- debugserver_vfp_v8,
- debugserver_vfp_v9,
- debugserver_vfp_v10,
- debugserver_vfp_v11,
- debugserver_vfp_v12,
- debugserver_vfp_v13,
- debugserver_vfp_v14,
- debugserver_vfp_v15,
- debugserver_vfp_v16,
- debugserver_vfp_v17,
- debugserver_vfp_v18,
- debugserver_vfp_v19,
- debugserver_vfp_v20,
- debugserver_vfp_v21,
- debugserver_vfp_v22,
- debugserver_vfp_v23,
- debugserver_vfp_v24,
- debugserver_vfp_v25,
- debugserver_vfp_v26,
- debugserver_vfp_v27,
- debugserver_vfp_v28,
- debugserver_vfp_v29,
- debugserver_vfp_v30,
- debugserver_vfp_v31,
- debugserver_vfp_fpsr,
- debugserver_vfp_fpcr
+enum {
+ debugserver_gpr_x0 = 0,
+ debugserver_gpr_x1,
+ debugserver_gpr_x2,
+ debugserver_gpr_x3,
+ debugserver_gpr_x4,
+ debugserver_gpr_x5,
+ debugserver_gpr_x6,
+ debugserver_gpr_x7,
+ debugserver_gpr_x8,
+ debugserver_gpr_x9,
+ debugserver_gpr_x10,
+ debugserver_gpr_x11,
+ debugserver_gpr_x12,
+ debugserver_gpr_x13,
+ debugserver_gpr_x14,
+ debugserver_gpr_x15,
+ debugserver_gpr_x16,
+ debugserver_gpr_x17,
+ debugserver_gpr_x18,
+ debugserver_gpr_x19,
+ debugserver_gpr_x20,
+ debugserver_gpr_x21,
+ debugserver_gpr_x22,
+ debugserver_gpr_x23,
+ debugserver_gpr_x24,
+ debugserver_gpr_x25,
+ debugserver_gpr_x26,
+ debugserver_gpr_x27,
+ debugserver_gpr_x28,
+ debugserver_gpr_fp, // x29
+ debugserver_gpr_lr, // x30
+ debugserver_gpr_sp, // sp aka xsp
+ debugserver_gpr_pc,
+ debugserver_gpr_cpsr,
+ debugserver_vfp_v0,
+ debugserver_vfp_v1,
+ debugserver_vfp_v2,
+ debugserver_vfp_v3,
+ debugserver_vfp_v4,
+ debugserver_vfp_v5,
+ debugserver_vfp_v6,
+ debugserver_vfp_v7,
+ debugserver_vfp_v8,
+ debugserver_vfp_v9,
+ debugserver_vfp_v10,
+ debugserver_vfp_v11,
+ debugserver_vfp_v12,
+ debugserver_vfp_v13,
+ debugserver_vfp_v14,
+ debugserver_vfp_v15,
+ debugserver_vfp_v16,
+ debugserver_vfp_v17,
+ debugserver_vfp_v18,
+ debugserver_vfp_v19,
+ debugserver_vfp_v20,
+ debugserver_vfp_v21,
+ debugserver_vfp_v22,
+ debugserver_vfp_v23,
+ debugserver_vfp_v24,
+ debugserver_vfp_v25,
+ debugserver_vfp_v26,
+ debugserver_vfp_v27,
+ debugserver_vfp_v28,
+ debugserver_vfp_v29,
+ debugserver_vfp_v30,
+ debugserver_vfp_v31,
+ debugserver_vfp_fpsr,
+ debugserver_vfp_fpcr
};
-const char *g_contained_x0[] {"x0", NULL };
-const char *g_contained_x1[] {"x1", NULL };
-const char *g_contained_x2[] {"x2", NULL };
-const char *g_contained_x3[] {"x3", NULL };
-const char *g_contained_x4[] {"x4", NULL };
-const char *g_contained_x5[] {"x5", NULL };
-const char *g_contained_x6[] {"x6", NULL };
-const char *g_contained_x7[] {"x7", NULL };
-const char *g_contained_x8[] {"x8", NULL };
-const char *g_contained_x9[] {"x9", NULL };
-const char *g_contained_x10[] {"x10", NULL };
-const char *g_contained_x11[] {"x11", NULL };
-const char *g_contained_x12[] {"x12", NULL };
-const char *g_contained_x13[] {"x13", NULL };
-const char *g_contained_x14[] {"x14", NULL };
-const char *g_contained_x15[] {"x15", NULL };
-const char *g_contained_x16[] {"x16", NULL };
-const char *g_contained_x17[] {"x17", NULL };
-const char *g_contained_x18[] {"x18", NULL };
-const char *g_contained_x19[] {"x19", NULL };
-const char *g_contained_x20[] {"x20", NULL };
-const char *g_contained_x21[] {"x21", NULL };
-const char *g_contained_x22[] {"x22", NULL };
-const char *g_contained_x23[] {"x23", NULL };
-const char *g_contained_x24[] {"x24", NULL };
-const char *g_contained_x25[] {"x25", NULL };
-const char *g_contained_x26[] {"x26", NULL };
-const char *g_contained_x27[] {"x27", NULL };
-const char *g_contained_x28[] {"x28", NULL };
-
-const char *g_invalidate_x0[] {"x0", "w0", NULL };
-const char *g_invalidate_x1[] {"x1", "w1", NULL };
-const char *g_invalidate_x2[] {"x2", "w2", NULL };
-const char *g_invalidate_x3[] {"x3", "w3", NULL };
-const char *g_invalidate_x4[] {"x4", "w4", NULL };
-const char *g_invalidate_x5[] {"x5", "w5", NULL };
-const char *g_invalidate_x6[] {"x6", "w6", NULL };
-const char *g_invalidate_x7[] {"x7", "w7", NULL };
-const char *g_invalidate_x8[] {"x8", "w8", NULL };
-const char *g_invalidate_x9[] {"x9", "w9", NULL };
-const char *g_invalidate_x10[] {"x10", "w10", NULL };
-const char *g_invalidate_x11[] {"x11", "w11", NULL };
-const char *g_invalidate_x12[] {"x12", "w12", NULL };
-const char *g_invalidate_x13[] {"x13", "w13", NULL };
-const char *g_invalidate_x14[] {"x14", "w14", NULL };
-const char *g_invalidate_x15[] {"x15", "w15", NULL };
-const char *g_invalidate_x16[] {"x16", "w16", NULL };
-const char *g_invalidate_x17[] {"x17", "w17", NULL };
-const char *g_invalidate_x18[] {"x18", "w18", NULL };
-const char *g_invalidate_x19[] {"x19", "w19", NULL };
-const char *g_invalidate_x20[] {"x20", "w20", NULL };
-const char *g_invalidate_x21[] {"x21", "w21", NULL };
-const char *g_invalidate_x22[] {"x22", "w22", NULL };
-const char *g_invalidate_x23[] {"x23", "w23", NULL };
-const char *g_invalidate_x24[] {"x24", "w24", NULL };
-const char *g_invalidate_x25[] {"x25", "w25", NULL };
-const char *g_invalidate_x26[] {"x26", "w26", NULL };
-const char *g_invalidate_x27[] {"x27", "w27", NULL };
-const char *g_invalidate_x28[] {"x28", "w28", NULL };
+const char *g_contained_x0[]{"x0", NULL};
+const char *g_contained_x1[]{"x1", NULL};
+const char *g_contained_x2[]{"x2", NULL};
+const char *g_contained_x3[]{"x3", NULL};
+const char *g_contained_x4[]{"x4", NULL};
+const char *g_contained_x5[]{"x5", NULL};
+const char *g_contained_x6[]{"x6", NULL};
+const char *g_contained_x7[]{"x7", NULL};
+const char *g_contained_x8[]{"x8", NULL};
+const char *g_contained_x9[]{"x9", NULL};
+const char *g_contained_x10[]{"x10", NULL};
+const char *g_contained_x11[]{"x11", NULL};
+const char *g_contained_x12[]{"x12", NULL};
+const char *g_contained_x13[]{"x13", NULL};
+const char *g_contained_x14[]{"x14", NULL};
+const char *g_contained_x15[]{"x15", NULL};
+const char *g_contained_x16[]{"x16", NULL};
+const char *g_contained_x17[]{"x17", NULL};
+const char *g_contained_x18[]{"x18", NULL};
+const char *g_contained_x19[]{"x19", NULL};
+const char *g_contained_x20[]{"x20", NULL};
+const char *g_contained_x21[]{"x21", NULL};
+const char *g_contained_x22[]{"x22", NULL};
+const char *g_contained_x23[]{"x23", NULL};
+const char *g_contained_x24[]{"x24", NULL};
+const char *g_contained_x25[]{"x25", NULL};
+const char *g_contained_x26[]{"x26", NULL};
+const char *g_contained_x27[]{"x27", NULL};
+const char *g_contained_x28[]{"x28", NULL};
+
+const char *g_invalidate_x0[]{"x0", "w0", NULL};
+const char *g_invalidate_x1[]{"x1", "w1", NULL};
+const char *g_invalidate_x2[]{"x2", "w2", NULL};
+const char *g_invalidate_x3[]{"x3", "w3", NULL};
+const char *g_invalidate_x4[]{"x4", "w4", NULL};
+const char *g_invalidate_x5[]{"x5", "w5", NULL};
+const char *g_invalidate_x6[]{"x6", "w6", NULL};
+const char *g_invalidate_x7[]{"x7", "w7", NULL};
+const char *g_invalidate_x8[]{"x8", "w8", NULL};
+const char *g_invalidate_x9[]{"x9", "w9", NULL};
+const char *g_invalidate_x10[]{"x10", "w10", NULL};
+const char *g_invalidate_x11[]{"x11", "w11", NULL};
+const char *g_invalidate_x12[]{"x12", "w12", NULL};
+const char *g_invalidate_x13[]{"x13", "w13", NULL};
+const char *g_invalidate_x14[]{"x14", "w14", NULL};
+const char *g_invalidate_x15[]{"x15", "w15", NULL};
+const char *g_invalidate_x16[]{"x16", "w16", NULL};
+const char *g_invalidate_x17[]{"x17", "w17", NULL};
+const char *g_invalidate_x18[]{"x18", "w18", NULL};
+const char *g_invalidate_x19[]{"x19", "w19", NULL};
+const char *g_invalidate_x20[]{"x20", "w20", NULL};
+const char *g_invalidate_x21[]{"x21", "w21", NULL};
+const char *g_invalidate_x22[]{"x22", "w22", NULL};
+const char *g_invalidate_x23[]{"x23", "w23", NULL};
+const char *g_invalidate_x24[]{"x24", "w24", NULL};
+const char *g_invalidate_x25[]{"x25", "w25", NULL};
+const char *g_invalidate_x26[]{"x26", "w26", NULL};
+const char *g_invalidate_x27[]{"x27", "w27", NULL};
+const char *g_invalidate_x28[]{"x28", "w28", NULL};
-#define GPR_OFFSET_IDX(idx) (offsetof (DNBArchMachARM64::GPR, __x[idx]))
+#define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx]))
-#define GPR_OFFSET_NAME(reg) (offsetof (DNBArchMachARM64::GPR , __##reg))
+#define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg))
// These macros will auto define the register name, alt name, register size,
// register offset, encoding, format and native register. This ensures that
// the register state structures are defined correctly and have the correct
// sizes and offsets.
-#define DEFINE_GPR_IDX(idx, reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx) , dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, g_invalidate_x##idx }
-#define DEFINE_GPR_NAME(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL }
-#define DEFINE_PSEUDO_GPR_IDX(idx, reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_x##idx, g_invalidate_x##idx }
+#define DEFINE_GPR_IDX(idx, reg, alt, gen) \
+ { \
+ e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \
+ dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \
+ g_invalidate_x##idx \
+ }
+#define DEFINE_GPR_NAME(reg, alt, gen) \
+ { \
+ e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \
+ dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \
+ }
+#define DEFINE_PSEUDO_GPR_IDX(idx, reg) \
+ { \
+ e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \
+ g_contained_x##idx, g_invalidate_x##idx \
+ }
//_STRUCT_ARM_THREAD_STATE64
//{
@@ -1365,268 +1375,292 @@ const char *g_invalidate_x28[] {"x28", "
// uint32_t cpsr; /* Current program status register */
//};
-
// General purpose registers
-const DNBRegisterInfo
-DNBArchMachARM64::g_gpr_registers[] =
-{
- DEFINE_GPR_IDX ( 0, x0, "arg1", GENERIC_REGNUM_ARG1 ),
- DEFINE_GPR_IDX ( 1, x1, "arg2", GENERIC_REGNUM_ARG2 ),
- DEFINE_GPR_IDX ( 2, x2, "arg3", GENERIC_REGNUM_ARG3 ),
- DEFINE_GPR_IDX ( 3, x3, "arg4", GENERIC_REGNUM_ARG4 ),
- DEFINE_GPR_IDX ( 4, x4, "arg5", GENERIC_REGNUM_ARG5 ),
- DEFINE_GPR_IDX ( 5, x5, "arg6", GENERIC_REGNUM_ARG6 ),
- DEFINE_GPR_IDX ( 6, x6, "arg7", GENERIC_REGNUM_ARG7 ),
- DEFINE_GPR_IDX ( 7, x7, "arg8", GENERIC_REGNUM_ARG8 ),
- DEFINE_GPR_IDX ( 8, x8, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX ( 9, x9, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (10, x10, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (11, x11, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (12, x12, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (13, x13, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (14, x14, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (15, x15, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (16, x16, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (17, x17, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (18, x18, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (19, x19, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (20, x20, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (21, x21, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (22, x22, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (23, x23, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (24, x24, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (25, x25, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (26, x26, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (27, x27, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_IDX (28, x28, NULL, INVALID_NUB_REGNUM ),
- DEFINE_GPR_NAME (fp, "x29", GENERIC_REGNUM_FP),
- DEFINE_GPR_NAME (lr, "x30", GENERIC_REGNUM_RA),
- DEFINE_GPR_NAME (sp, "xsp", GENERIC_REGNUM_SP),
- DEFINE_GPR_NAME (pc, NULL, GENERIC_REGNUM_PC),
-
- // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, lr.
- // this should be specified for arm64 too even though debugserver is only used for
+const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = {
+ DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1),
+ DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2),
+ DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3),
+ DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4),
+ DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5),
+ DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6),
+ DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7),
+ DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8),
+ DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM),
+ DEFINE_GPR_NAME(fp, "x29", GENERIC_REGNUM_FP),
+ DEFINE_GPR_NAME(lr, "x30", GENERIC_REGNUM_RA),
+ DEFINE_GPR_NAME(sp, "xsp", GENERIC_REGNUM_SP),
+ DEFINE_GPR_NAME(pc, NULL, GENERIC_REGNUM_PC),
+
+ // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp,
+ // lr.
+ // this should be specified for arm64 too even though debugserver is only
+ // used for
// userland debugging.
- { e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, debugserver_gpr_cpsr, NULL, NULL },
-
- DEFINE_PSEUDO_GPR_IDX ( 0, w0),
- DEFINE_PSEUDO_GPR_IDX ( 1, w1),
- DEFINE_PSEUDO_GPR_IDX ( 2, w2),
- DEFINE_PSEUDO_GPR_IDX ( 3, w3),
- DEFINE_PSEUDO_GPR_IDX ( 4, w4),
- DEFINE_PSEUDO_GPR_IDX ( 5, w5),
- DEFINE_PSEUDO_GPR_IDX ( 6, w6),
- DEFINE_PSEUDO_GPR_IDX ( 7, w7),
- DEFINE_PSEUDO_GPR_IDX ( 8, w8),
- DEFINE_PSEUDO_GPR_IDX ( 9, w9),
- DEFINE_PSEUDO_GPR_IDX (10, w10),
- DEFINE_PSEUDO_GPR_IDX (11, w11),
- DEFINE_PSEUDO_GPR_IDX (12, w12),
- DEFINE_PSEUDO_GPR_IDX (13, w13),
- DEFINE_PSEUDO_GPR_IDX (14, w14),
- DEFINE_PSEUDO_GPR_IDX (15, w15),
- DEFINE_PSEUDO_GPR_IDX (16, w16),
- DEFINE_PSEUDO_GPR_IDX (17, w17),
- DEFINE_PSEUDO_GPR_IDX (18, w18),
- DEFINE_PSEUDO_GPR_IDX (19, w19),
- DEFINE_PSEUDO_GPR_IDX (20, w20),
- DEFINE_PSEUDO_GPR_IDX (21, w21),
- DEFINE_PSEUDO_GPR_IDX (22, w22),
- DEFINE_PSEUDO_GPR_IDX (23, w23),
- DEFINE_PSEUDO_GPR_IDX (24, w24),
- DEFINE_PSEUDO_GPR_IDX (25, w25),
- DEFINE_PSEUDO_GPR_IDX (26, w26),
- DEFINE_PSEUDO_GPR_IDX (27, w27),
- DEFINE_PSEUDO_GPR_IDX (28, w28)
-};
-
-const char *g_contained_v0[] {"v0", NULL };
-const char *g_contained_v1[] {"v1", NULL };
-const char *g_contained_v2[] {"v2", NULL };
-const char *g_contained_v3[] {"v3", NULL };
-const char *g_contained_v4[] {"v4", NULL };
-const char *g_contained_v5[] {"v5", NULL };
-const char *g_contained_v6[] {"v6", NULL };
-const char *g_contained_v7[] {"v7", NULL };
-const char *g_contained_v8[] {"v8", NULL };
-const char *g_contained_v9[] {"v9", NULL };
-const char *g_contained_v10[] {"v10", NULL };
-const char *g_contained_v11[] {"v11", NULL };
-const char *g_contained_v12[] {"v12", NULL };
-const char *g_contained_v13[] {"v13", NULL };
-const char *g_contained_v14[] {"v14", NULL };
-const char *g_contained_v15[] {"v15", NULL };
-const char *g_contained_v16[] {"v16", NULL };
-const char *g_contained_v17[] {"v17", NULL };
-const char *g_contained_v18[] {"v18", NULL };
-const char *g_contained_v19[] {"v19", NULL };
-const char *g_contained_v20[] {"v20", NULL };
-const char *g_contained_v21[] {"v21", NULL };
-const char *g_contained_v22[] {"v22", NULL };
-const char *g_contained_v23[] {"v23", NULL };
-const char *g_contained_v24[] {"v24", NULL };
-const char *g_contained_v25[] {"v25", NULL };
-const char *g_contained_v26[] {"v26", NULL };
-const char *g_contained_v27[] {"v27", NULL };
-const char *g_contained_v28[] {"v28", NULL };
-const char *g_contained_v29[] {"v29", NULL };
-const char *g_contained_v30[] {"v30", NULL };
-const char *g_contained_v31[] {"v31", NULL };
-
-const char *g_invalidate_v0[] {"v0", "d0", "s0", NULL };
-const char *g_invalidate_v1[] {"v1", "d1", "s1", NULL };
-const char *g_invalidate_v2[] {"v2", "d2", "s2", NULL };
-const char *g_invalidate_v3[] {"v3", "d3", "s3", NULL };
-const char *g_invalidate_v4[] {"v4", "d4", "s4", NULL };
-const char *g_invalidate_v5[] {"v5", "d5", "s5", NULL };
-const char *g_invalidate_v6[] {"v6", "d6", "s6", NULL };
-const char *g_invalidate_v7[] {"v7", "d7", "s7", NULL };
-const char *g_invalidate_v8[] {"v8", "d8", "s8", NULL };
-const char *g_invalidate_v9[] {"v9", "d9", "s9", NULL };
-const char *g_invalidate_v10[] {"v10", "d10", "s10", NULL };
-const char *g_invalidate_v11[] {"v11", "d11", "s11", NULL };
-const char *g_invalidate_v12[] {"v12", "d12", "s12", NULL };
-const char *g_invalidate_v13[] {"v13", "d13", "s13", NULL };
-const char *g_invalidate_v14[] {"v14", "d14", "s14", NULL };
-const char *g_invalidate_v15[] {"v15", "d15", "s15", NULL };
-const char *g_invalidate_v16[] {"v16", "d16", "s16", NULL };
-const char *g_invalidate_v17[] {"v17", "d17", "s17", NULL };
-const char *g_invalidate_v18[] {"v18", "d18", "s18", NULL };
-const char *g_invalidate_v19[] {"v19", "d19", "s19", NULL };
-const char *g_invalidate_v20[] {"v20", "d20", "s20", NULL };
-const char *g_invalidate_v21[] {"v21", "d21", "s21", NULL };
-const char *g_invalidate_v22[] {"v22", "d22", "s22", NULL };
-const char *g_invalidate_v23[] {"v23", "d23", "s23", NULL };
-const char *g_invalidate_v24[] {"v24", "d24", "s24", NULL };
-const char *g_invalidate_v25[] {"v25", "d25", "s25", NULL };
-const char *g_invalidate_v26[] {"v26", "d26", "s26", NULL };
-const char *g_invalidate_v27[] {"v27", "d27", "s27", NULL };
-const char *g_invalidate_v28[] {"v28", "d28", "s28", NULL };
-const char *g_invalidate_v29[] {"v29", "d29", "s29", NULL };
-const char *g_invalidate_v30[] {"v30", "d30", "s30", NULL };
-const char *g_invalidate_v31[] {"v31", "d31", "s31", NULL };
-
-#if defined (__arm64__) || defined (__aarch64__)
-#define VFP_V_OFFSET_IDX(idx) (offsetof (DNBArchMachARM64::FPU, __v) + (idx * 16) + offsetof (DNBArchMachARM64::Context, vfp))
+ {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4,
+ GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM,
+ debugserver_gpr_cpsr, NULL, NULL},
+
+ DEFINE_PSEUDO_GPR_IDX(0, w0),
+ DEFINE_PSEUDO_GPR_IDX(1, w1),
+ DEFINE_PSEUDO_GPR_IDX(2, w2),
+ DEFINE_PSEUDO_GPR_IDX(3, w3),
+ DEFINE_PSEUDO_GPR_IDX(4, w4),
+ DEFINE_PSEUDO_GPR_IDX(5, w5),
+ DEFINE_PSEUDO_GPR_IDX(6, w6),
+ DEFINE_PSEUDO_GPR_IDX(7, w7),
+ DEFINE_PSEUDO_GPR_IDX(8, w8),
+ DEFINE_PSEUDO_GPR_IDX(9, w9),
+ DEFINE_PSEUDO_GPR_IDX(10, w10),
+ DEFINE_PSEUDO_GPR_IDX(11, w11),
+ DEFINE_PSEUDO_GPR_IDX(12, w12),
+ DEFINE_PSEUDO_GPR_IDX(13, w13),
+ DEFINE_PSEUDO_GPR_IDX(14, w14),
+ DEFINE_PSEUDO_GPR_IDX(15, w15),
+ DEFINE_PSEUDO_GPR_IDX(16, w16),
+ DEFINE_PSEUDO_GPR_IDX(17, w17),
+ DEFINE_PSEUDO_GPR_IDX(18, w18),
+ DEFINE_PSEUDO_GPR_IDX(19, w19),
+ DEFINE_PSEUDO_GPR_IDX(20, w20),
+ DEFINE_PSEUDO_GPR_IDX(21, w21),
+ DEFINE_PSEUDO_GPR_IDX(22, w22),
+ DEFINE_PSEUDO_GPR_IDX(23, w23),
+ DEFINE_PSEUDO_GPR_IDX(24, w24),
+ DEFINE_PSEUDO_GPR_IDX(25, w25),
+ DEFINE_PSEUDO_GPR_IDX(26, w26),
+ DEFINE_PSEUDO_GPR_IDX(27, w27),
+ DEFINE_PSEUDO_GPR_IDX(28, w28)};
+
+const char *g_contained_v0[]{"v0", NULL};
+const char *g_contained_v1[]{"v1", NULL};
+const char *g_contained_v2[]{"v2", NULL};
+const char *g_contained_v3[]{"v3", NULL};
+const char *g_contained_v4[]{"v4", NULL};
+const char *g_contained_v5[]{"v5", NULL};
+const char *g_contained_v6[]{"v6", NULL};
+const char *g_contained_v7[]{"v7", NULL};
+const char *g_contained_v8[]{"v8", NULL};
+const char *g_contained_v9[]{"v9", NULL};
+const char *g_contained_v10[]{"v10", NULL};
+const char *g_contained_v11[]{"v11", NULL};
+const char *g_contained_v12[]{"v12", NULL};
+const char *g_contained_v13[]{"v13", NULL};
+const char *g_contained_v14[]{"v14", NULL};
+const char *g_contained_v15[]{"v15", NULL};
+const char *g_contained_v16[]{"v16", NULL};
+const char *g_contained_v17[]{"v17", NULL};
+const char *g_contained_v18[]{"v18", NULL};
+const char *g_contained_v19[]{"v19", NULL};
+const char *g_contained_v20[]{"v20", NULL};
+const char *g_contained_v21[]{"v21", NULL};
+const char *g_contained_v22[]{"v22", NULL};
+const char *g_contained_v23[]{"v23", NULL};
+const char *g_contained_v24[]{"v24", NULL};
+const char *g_contained_v25[]{"v25", NULL};
+const char *g_contained_v26[]{"v26", NULL};
+const char *g_contained_v27[]{"v27", NULL};
+const char *g_contained_v28[]{"v28", NULL};
+const char *g_contained_v29[]{"v29", NULL};
+const char *g_contained_v30[]{"v30", NULL};
+const char *g_contained_v31[]{"v31", NULL};
+
+const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL};
+const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL};
+const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL};
+const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL};
+const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL};
+const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL};
+const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL};
+const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL};
+const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL};
+const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL};
+const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL};
+const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL};
+const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL};
+const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL};
+const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL};
+const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL};
+const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL};
+const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL};
+const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL};
+const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL};
+const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL};
+const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL};
+const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL};
+const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL};
+const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL};
+const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL};
+const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL};
+const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL};
+const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL};
+const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL};
+const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL};
+const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL};
+
+#if defined(__arm64__) || defined(__aarch64__)
+#define VFP_V_OFFSET_IDX(idx) \
+ (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \
+ offsetof(DNBArchMachARM64::Context, vfp))
#else
-#define VFP_V_OFFSET_IDX(idx) (offsetof (DNBArchMachARM64::FPU, opaque) + (idx * 16) + offsetof (DNBArchMachARM64::Context, vfp))
+#define VFP_V_OFFSET_IDX(idx) \
+ (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \
+ offsetof(DNBArchMachARM64::Context, vfp))
#endif
-#define VFP_OFFSET_NAME(reg) (offsetof (DNBArchMachARM64::FPU, reg) + offsetof (DNBArchMachARM64::Context, vfp))
-#define EXC_OFFSET(reg) (offsetof (DNBArchMachARM64::EXC, reg) + offsetof (DNBArchMachARM64::Context, exc))
+#define VFP_OFFSET_NAME(reg) \
+ (offsetof(DNBArchMachARM64::FPU, reg) + \
+ offsetof(DNBArchMachARM64::Context, vfp))
+#define EXC_OFFSET(reg) \
+ (offsetof(DNBArchMachARM64::EXC, reg) + \
+ offsetof(DNBArchMachARM64::Context, exc))
//#define FLOAT_FORMAT Float
-#define DEFINE_VFP_V_IDX(idx) { e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx }
-#define DEFINE_PSEUDO_VFP_S_IDX(idx) { e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx }
-#define DEFINE_PSEUDO_VFP_D_IDX(idx) { e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx }
+#define DEFINE_VFP_V_IDX(idx) \
+ { \
+ e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \
+ VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \
+ INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \
+ }
+#define DEFINE_PSEUDO_VFP_S_IDX(idx) \
+ { \
+ e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \
+ INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \
+ }
+#define DEFINE_PSEUDO_VFP_D_IDX(idx) \
+ { \
+ e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \
+ INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \
+ }
// Floating point registers
-const DNBRegisterInfo
-DNBArchMachARM64::g_vfp_registers[] =
-{
- DEFINE_VFP_V_IDX ( 0),
- DEFINE_VFP_V_IDX ( 1),
- DEFINE_VFP_V_IDX ( 2),
- DEFINE_VFP_V_IDX ( 3),
- DEFINE_VFP_V_IDX ( 4),
- DEFINE_VFP_V_IDX ( 5),
- DEFINE_VFP_V_IDX ( 6),
- DEFINE_VFP_V_IDX ( 7),
- DEFINE_VFP_V_IDX ( 8),
- DEFINE_VFP_V_IDX ( 9),
- DEFINE_VFP_V_IDX (10),
- DEFINE_VFP_V_IDX (11),
- DEFINE_VFP_V_IDX (12),
- DEFINE_VFP_V_IDX (13),
- DEFINE_VFP_V_IDX (14),
- DEFINE_VFP_V_IDX (15),
- DEFINE_VFP_V_IDX (16),
- DEFINE_VFP_V_IDX (17),
- DEFINE_VFP_V_IDX (18),
- DEFINE_VFP_V_IDX (19),
- DEFINE_VFP_V_IDX (20),
- DEFINE_VFP_V_IDX (21),
- DEFINE_VFP_V_IDX (22),
- DEFINE_VFP_V_IDX (23),
- DEFINE_VFP_V_IDX (24),
- DEFINE_VFP_V_IDX (25),
- DEFINE_VFP_V_IDX (26),
- DEFINE_VFP_V_IDX (27),
- DEFINE_VFP_V_IDX (28),
- DEFINE_VFP_V_IDX (29),
- DEFINE_VFP_V_IDX (30),
- DEFINE_VFP_V_IDX (31),
- { e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, VFP_V_OFFSET_IDX (32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
- { e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, VFP_V_OFFSET_IDX (32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-
- DEFINE_PSEUDO_VFP_S_IDX (0),
- DEFINE_PSEUDO_VFP_S_IDX (1),
- DEFINE_PSEUDO_VFP_S_IDX (2),
- DEFINE_PSEUDO_VFP_S_IDX (3),
- DEFINE_PSEUDO_VFP_S_IDX (4),
- DEFINE_PSEUDO_VFP_S_IDX (5),
- DEFINE_PSEUDO_VFP_S_IDX (6),
- DEFINE_PSEUDO_VFP_S_IDX (7),
- DEFINE_PSEUDO_VFP_S_IDX (8),
- DEFINE_PSEUDO_VFP_S_IDX (9),
- DEFINE_PSEUDO_VFP_S_IDX (10),
- DEFINE_PSEUDO_VFP_S_IDX (11),
- DEFINE_PSEUDO_VFP_S_IDX (12),
- DEFINE_PSEUDO_VFP_S_IDX (13),
- DEFINE_PSEUDO_VFP_S_IDX (14),
- DEFINE_PSEUDO_VFP_S_IDX (15),
- DEFINE_PSEUDO_VFP_S_IDX (16),
- DEFINE_PSEUDO_VFP_S_IDX (17),
- DEFINE_PSEUDO_VFP_S_IDX (18),
- DEFINE_PSEUDO_VFP_S_IDX (19),
- DEFINE_PSEUDO_VFP_S_IDX (20),
- DEFINE_PSEUDO_VFP_S_IDX (21),
- DEFINE_PSEUDO_VFP_S_IDX (22),
- DEFINE_PSEUDO_VFP_S_IDX (23),
- DEFINE_PSEUDO_VFP_S_IDX (24),
- DEFINE_PSEUDO_VFP_S_IDX (25),
- DEFINE_PSEUDO_VFP_S_IDX (26),
- DEFINE_PSEUDO_VFP_S_IDX (27),
- DEFINE_PSEUDO_VFP_S_IDX (28),
- DEFINE_PSEUDO_VFP_S_IDX (29),
- DEFINE_PSEUDO_VFP_S_IDX (30),
- DEFINE_PSEUDO_VFP_S_IDX (31),
-
- DEFINE_PSEUDO_VFP_D_IDX (0),
- DEFINE_PSEUDO_VFP_D_IDX (1),
- DEFINE_PSEUDO_VFP_D_IDX (2),
- DEFINE_PSEUDO_VFP_D_IDX (3),
- DEFINE_PSEUDO_VFP_D_IDX (4),
- DEFINE_PSEUDO_VFP_D_IDX (5),
- DEFINE_PSEUDO_VFP_D_IDX (6),
- DEFINE_PSEUDO_VFP_D_IDX (7),
- DEFINE_PSEUDO_VFP_D_IDX (8),
- DEFINE_PSEUDO_VFP_D_IDX (9),
- DEFINE_PSEUDO_VFP_D_IDX (10),
- DEFINE_PSEUDO_VFP_D_IDX (11),
- DEFINE_PSEUDO_VFP_D_IDX (12),
- DEFINE_PSEUDO_VFP_D_IDX (13),
- DEFINE_PSEUDO_VFP_D_IDX (14),
- DEFINE_PSEUDO_VFP_D_IDX (15),
- DEFINE_PSEUDO_VFP_D_IDX (16),
- DEFINE_PSEUDO_VFP_D_IDX (17),
- DEFINE_PSEUDO_VFP_D_IDX (18),
- DEFINE_PSEUDO_VFP_D_IDX (19),
- DEFINE_PSEUDO_VFP_D_IDX (20),
- DEFINE_PSEUDO_VFP_D_IDX (21),
- DEFINE_PSEUDO_VFP_D_IDX (22),
- DEFINE_PSEUDO_VFP_D_IDX (23),
- DEFINE_PSEUDO_VFP_D_IDX (24),
- DEFINE_PSEUDO_VFP_D_IDX (25),
- DEFINE_PSEUDO_VFP_D_IDX (26),
- DEFINE_PSEUDO_VFP_D_IDX (27),
- DEFINE_PSEUDO_VFP_D_IDX (28),
- DEFINE_PSEUDO_VFP_D_IDX (29),
- DEFINE_PSEUDO_VFP_D_IDX (30),
- DEFINE_PSEUDO_VFP_D_IDX (31)
+const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = {
+ DEFINE_VFP_V_IDX(0),
+ DEFINE_VFP_V_IDX(1),
+ DEFINE_VFP_V_IDX(2),
+ DEFINE_VFP_V_IDX(3),
+ DEFINE_VFP_V_IDX(4),
+ DEFINE_VFP_V_IDX(5),
+ DEFINE_VFP_V_IDX(6),
+ DEFINE_VFP_V_IDX(7),
+ DEFINE_VFP_V_IDX(8),
+ DEFINE_VFP_V_IDX(9),
+ DEFINE_VFP_V_IDX(10),
+ DEFINE_VFP_V_IDX(11),
+ DEFINE_VFP_V_IDX(12),
+ DEFINE_VFP_V_IDX(13),
+ DEFINE_VFP_V_IDX(14),
+ DEFINE_VFP_V_IDX(15),
+ DEFINE_VFP_V_IDX(16),
+ DEFINE_VFP_V_IDX(17),
+ DEFINE_VFP_V_IDX(18),
+ DEFINE_VFP_V_IDX(19),
+ DEFINE_VFP_V_IDX(20),
+ DEFINE_VFP_V_IDX(21),
+ DEFINE_VFP_V_IDX(22),
+ DEFINE_VFP_V_IDX(23),
+ DEFINE_VFP_V_IDX(24),
+ DEFINE_VFP_V_IDX(25),
+ DEFINE_VFP_V_IDX(26),
+ DEFINE_VFP_V_IDX(27),
+ DEFINE_VFP_V_IDX(28),
+ DEFINE_VFP_V_IDX(29),
+ DEFINE_VFP_V_IDX(30),
+ DEFINE_VFP_V_IDX(31),
+ {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4,
+ VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4,
+ VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+
+ DEFINE_PSEUDO_VFP_S_IDX(0),
+ DEFINE_PSEUDO_VFP_S_IDX(1),
+ DEFINE_PSEUDO_VFP_S_IDX(2),
+ DEFINE_PSEUDO_VFP_S_IDX(3),
+ DEFINE_PSEUDO_VFP_S_IDX(4),
+ DEFINE_PSEUDO_VFP_S_IDX(5),
+ DEFINE_PSEUDO_VFP_S_IDX(6),
+ DEFINE_PSEUDO_VFP_S_IDX(7),
+ DEFINE_PSEUDO_VFP_S_IDX(8),
+ DEFINE_PSEUDO_VFP_S_IDX(9),
+ DEFINE_PSEUDO_VFP_S_IDX(10),
+ DEFINE_PSEUDO_VFP_S_IDX(11),
+ DEFINE_PSEUDO_VFP_S_IDX(12),
+ DEFINE_PSEUDO_VFP_S_IDX(13),
+ DEFINE_PSEUDO_VFP_S_IDX(14),
+ DEFINE_PSEUDO_VFP_S_IDX(15),
+ DEFINE_PSEUDO_VFP_S_IDX(16),
+ DEFINE_PSEUDO_VFP_S_IDX(17),
+ DEFINE_PSEUDO_VFP_S_IDX(18),
+ DEFINE_PSEUDO_VFP_S_IDX(19),
+ DEFINE_PSEUDO_VFP_S_IDX(20),
+ DEFINE_PSEUDO_VFP_S_IDX(21),
+ DEFINE_PSEUDO_VFP_S_IDX(22),
+ DEFINE_PSEUDO_VFP_S_IDX(23),
+ DEFINE_PSEUDO_VFP_S_IDX(24),
+ DEFINE_PSEUDO_VFP_S_IDX(25),
+ DEFINE_PSEUDO_VFP_S_IDX(26),
+ DEFINE_PSEUDO_VFP_S_IDX(27),
+ DEFINE_PSEUDO_VFP_S_IDX(28),
+ DEFINE_PSEUDO_VFP_S_IDX(29),
+ DEFINE_PSEUDO_VFP_S_IDX(30),
+ DEFINE_PSEUDO_VFP_S_IDX(31),
+
+ DEFINE_PSEUDO_VFP_D_IDX(0),
+ DEFINE_PSEUDO_VFP_D_IDX(1),
+ DEFINE_PSEUDO_VFP_D_IDX(2),
+ DEFINE_PSEUDO_VFP_D_IDX(3),
+ DEFINE_PSEUDO_VFP_D_IDX(4),
+ DEFINE_PSEUDO_VFP_D_IDX(5),
+ DEFINE_PSEUDO_VFP_D_IDX(6),
+ DEFINE_PSEUDO_VFP_D_IDX(7),
+ DEFINE_PSEUDO_VFP_D_IDX(8),
+ DEFINE_PSEUDO_VFP_D_IDX(9),
+ DEFINE_PSEUDO_VFP_D_IDX(10),
+ DEFINE_PSEUDO_VFP_D_IDX(11),
+ DEFINE_PSEUDO_VFP_D_IDX(12),
+ DEFINE_PSEUDO_VFP_D_IDX(13),
+ DEFINE_PSEUDO_VFP_D_IDX(14),
+ DEFINE_PSEUDO_VFP_D_IDX(15),
+ DEFINE_PSEUDO_VFP_D_IDX(16),
+ DEFINE_PSEUDO_VFP_D_IDX(17),
+ DEFINE_PSEUDO_VFP_D_IDX(18),
+ DEFINE_PSEUDO_VFP_D_IDX(19),
+ DEFINE_PSEUDO_VFP_D_IDX(20),
+ DEFINE_PSEUDO_VFP_D_IDX(21),
+ DEFINE_PSEUDO_VFP_D_IDX(22),
+ DEFINE_PSEUDO_VFP_D_IDX(23),
+ DEFINE_PSEUDO_VFP_D_IDX(24),
+ DEFINE_PSEUDO_VFP_D_IDX(25),
+ DEFINE_PSEUDO_VFP_D_IDX(26),
+ DEFINE_PSEUDO_VFP_D_IDX(27),
+ DEFINE_PSEUDO_VFP_D_IDX(28),
+ DEFINE_PSEUDO_VFP_D_IDX(29),
+ DEFINE_PSEUDO_VFP_D_IDX(30),
+ DEFINE_PSEUDO_VFP_D_IDX(31)
};
-
//_STRUCT_ARM_EXCEPTION_STATE64
//{
// uint64_t far; /* Virtual Fault Address */
@@ -1635,461 +1669,436 @@ DNBArchMachARM64::g_vfp_registers[] =
//};
// Exception registers
-const DNBRegisterInfo
-DNBArchMachARM64::g_exc_registers[] =
-{
- { e_regSetEXC, exc_far , "far" , NULL, Uint, Hex, 8, EXC_OFFSET(__far) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
- { e_regSetEXC, exc_esr , "esr" , NULL, Uint, Hex, 4, EXC_OFFSET(__esr) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
- { e_regSetEXC, exc_exception , "exception" , NULL, Uint, Hex, 4, EXC_OFFSET(__exception) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL }
-};
+const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = {
+ {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4,
+ EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}};
// Number of registers in each register set
-const size_t DNBArchMachARM64::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchMachARM64::k_num_vfp_registers = sizeof(g_vfp_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchMachARM64::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchMachARM64::k_num_all_registers = k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers;
+const size_t DNBArchMachARM64::k_num_gpr_registers =
+ sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchMachARM64::k_num_vfp_registers =
+ sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchMachARM64::k_num_exc_registers =
+ sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchMachARM64::k_num_all_registers =
+ k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers;
//----------------------------------------------------------------------
// Register set definitions. The first definitions at register set index
// of zero is for all registers, followed by other registers sets. The
// register information for the all register set need not be filled in.
//----------------------------------------------------------------------
-const DNBRegisterSetInfo
-DNBArchMachARM64::g_reg_sets[] =
-{
- { "ARM64 Registers", NULL, k_num_all_registers },
- { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers },
- { "Floating Point Registers", g_vfp_registers, k_num_vfp_registers },
- { "Exception State Registers", g_exc_registers, k_num_exc_registers }
-};
+const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = {
+ {"ARM64 Registers", NULL, k_num_all_registers},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
// Total number of register sets for this architecture
-const size_t DNBArchMachARM64::k_num_register_sets = sizeof(g_reg_sets)/sizeof(DNBRegisterSetInfo);
-
+const size_t DNBArchMachARM64::k_num_register_sets =
+ sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo);
const DNBRegisterSetInfo *
-DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets)
-{
- *num_reg_sets = k_num_register_sets;
- return g_reg_sets;
-}
-
-bool
-DNBArchMachARM64::FixGenericRegisterNumber (uint32_t &set, uint32_t ®)
-{
- if (set == REGISTER_SET_GENERIC)
- {
- switch (reg)
- {
- case GENERIC_REGNUM_PC: // Program Counter
- set = e_regSetGPR;
- reg = gpr_pc;
- break;
-
- case GENERIC_REGNUM_SP: // Stack Pointer
- set = e_regSetGPR;
- reg = gpr_sp;
- break;
-
- case GENERIC_REGNUM_FP: // Frame Pointer
- set = e_regSetGPR;
- reg = gpr_fp;
- break;
-
- case GENERIC_REGNUM_RA: // Return Address
- set = e_regSetGPR;
- reg = gpr_lr;
- break;
-
- case GENERIC_REGNUM_FLAGS: // Processor flags register
- set = e_regSetGPR;
- reg = gpr_cpsr;
- break;
-
- case GENERIC_REGNUM_ARG1:
- case GENERIC_REGNUM_ARG2:
- case GENERIC_REGNUM_ARG3:
- case GENERIC_REGNUM_ARG4:
- case GENERIC_REGNUM_ARG5:
- case GENERIC_REGNUM_ARG6:
- set = e_regSetGPR;
- reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1;
- break;
-
- default:
- return false;
- }
- }
- return true;
-}
-bool
-DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value)
-{
- if (!FixGenericRegisterNumber (set, reg))
- return false;
-
- if (GetRegisterState(set, false) != KERN_SUCCESS)
- return false;
-
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- value->info = *regInfo;
- switch (set)
- {
- case e_regSetGPR:
- if (reg <= gpr_pc)
- {
- value->value.uint64 = m_state.context.gpr.__x[reg];
- return true;
- }
- else if (reg == gpr_cpsr)
- {
- value->value.uint32 = m_state.context.gpr.__cpsr;
- return true;
- }
- break;
-
- case e_regSetVFP:
-
- if (reg >= vfp_v0 && reg <= vfp_v31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 16);
+DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
+ *num_reg_sets = k_num_register_sets;
+ return g_reg_sets;
+}
+
+bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) {
+ if (set == REGISTER_SET_GENERIC) {
+ switch (reg) {
+ case GENERIC_REGNUM_PC: // Program Counter
+ set = e_regSetGPR;
+ reg = gpr_pc;
+ break;
+
+ case GENERIC_REGNUM_SP: // Stack Pointer
+ set = e_regSetGPR;
+ reg = gpr_sp;
+ break;
+
+ case GENERIC_REGNUM_FP: // Frame Pointer
+ set = e_regSetGPR;
+ reg = gpr_fp;
+ break;
+
+ case GENERIC_REGNUM_RA: // Return Address
+ set = e_regSetGPR;
+ reg = gpr_lr;
+ break;
+
+ case GENERIC_REGNUM_FLAGS: // Processor flags register
+ set = e_regSetGPR;
+ reg = gpr_cpsr;
+ break;
+
+ case GENERIC_REGNUM_ARG1:
+ case GENERIC_REGNUM_ARG2:
+ case GENERIC_REGNUM_ARG3:
+ case GENERIC_REGNUM_ARG4:
+ case GENERIC_REGNUM_ARG5:
+ case GENERIC_REGNUM_ARG6:
+ set = e_regSetGPR;
+ reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1;
+ break;
+
+ default:
+ return false;
+ }
+ }
+ return true;
+}
+bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value) {
+ if (!FixGenericRegisterNumber(set, reg))
+ return false;
+
+ if (GetRegisterState(set, false) != KERN_SUCCESS)
+ return false;
+
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ value->info = *regInfo;
+ switch (set) {
+ case e_regSetGPR:
+ if (reg <= gpr_pc) {
+ value->value.uint64 = m_state.context.gpr.__x[reg];
+ return true;
+ } else if (reg == gpr_cpsr) {
+ value->value.uint32 = m_state.context.gpr.__cpsr;
+ return true;
+ }
+ break;
+
+ case e_regSetVFP:
+
+ if (reg >= vfp_v0 && reg <= vfp_v31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0],
+ 16);
#else
- memcpy (&value->value.v_uint8, ((uint8_t *) &m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 16);
+ memcpy(&value->value.v_uint8,
+ ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16),
+ 16);
#endif
- return true;
- }
- else if (reg == vfp_fpsr)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&value->value.uint32, &m_state.context.vfp.__fpsr, 4);
+ return true;
+ } else if (reg == vfp_fpsr) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4);
#else
- memcpy (&value->value.uint32, ((uint8_t *) &m_state.context.vfp.opaque) + (32 * 16) + 0, 4);
+ memcpy(&value->value.uint32,
+ ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4);
#endif
- return true;
- }
- else if (reg == vfp_fpcr)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&value->value.uint32, &m_state.context.vfp.__fpcr, 4);
+ return true;
+ } else if (reg == vfp_fpcr) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4);
#else
- memcpy (&value->value.uint32, ((uint8_t *) &m_state.context.vfp.opaque) + (32 * 16) + 4, 4);
+ memcpy(&value->value.uint32,
+ ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4);
#endif
- return true;
- }
- else if (reg >= vfp_s0 && reg <= vfp_s31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 4);
+ return true;
+ } else if (reg >= vfp_s0 && reg <= vfp_s31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0],
+ 4);
#else
- memcpy (&value->value.v_uint8, ((uint8_t *) &m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 4);
+ memcpy(&value->value.v_uint8,
+ ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16),
+ 4);
#endif
- return true;
- }
- else if (reg >= vfp_d0 && reg <= vfp_d31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 8);
+ return true;
+ } else if (reg >= vfp_d0 && reg <= vfp_d31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0],
+ 8);
#else
- memcpy (&value->value.v_uint8, ((uint8_t *) &m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 8);
+ memcpy(&value->value.v_uint8,
+ ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16),
+ 8);
#endif
- return true;
- }
- break;
-
- case e_regSetEXC:
- if (reg == exc_far)
- {
- value->value.uint64 = m_state.context.exc.__far;
- return true;
- }
- else if (reg == exc_esr)
- {
- value->value.uint32 = m_state.context.exc.__esr;
- return true;
- }
- else if (reg == exc_exception)
- {
- value->value.uint32 = m_state.context.exc.__exception;
- return true;
- }
- break;
- }
- }
+ return true;
+ }
+ break;
+
+ case e_regSetEXC:
+ if (reg == exc_far) {
+ value->value.uint64 = m_state.context.exc.__far;
+ return true;
+ } else if (reg == exc_esr) {
+ value->value.uint32 = m_state.context.exc.__esr;
+ return true;
+ } else if (reg == exc_exception) {
+ value->value.uint32 = m_state.context.exc.__exception;
+ return true;
+ }
+ break;
+ }
+ }
+ return false;
+}
+
+bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value) {
+ if (!FixGenericRegisterNumber(set, reg))
return false;
-}
-bool
-DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, const DNBRegisterValue *value)
-{
- if (!FixGenericRegisterNumber (set, reg))
- return false;
-
- if (GetRegisterState(set, false) != KERN_SUCCESS)
- return false;
-
- bool success = false;
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- switch (set)
- {
- case e_regSetGPR:
- if (reg <= gpr_pc)
- {
- m_state.context.gpr.__x[reg] = value->value.uint64;
- success = true;
- }
- else if (reg == gpr_cpsr)
- {
- m_state.context.gpr.__cpsr = value->value.uint32;
- success = true;
- }
- break;
-
- case e_regSetVFP:
- if (reg >= vfp_v0 && reg <= vfp_v31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 16);
+ if (GetRegisterState(set, false) != KERN_SUCCESS)
+ return false;
+
+ bool success = false;
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ switch (set) {
+ case e_regSetGPR:
+ if (reg <= gpr_pc) {
+ m_state.context.gpr.__x[reg] = value->value.uint64;
+ success = true;
+ } else if (reg == gpr_cpsr) {
+ m_state.context.gpr.__cpsr = value->value.uint32;
+ success = true;
+ }
+ break;
+
+ case e_regSetVFP:
+ if (reg >= vfp_v0 && reg <= vfp_v31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8,
+ 16);
#else
- memcpy (((uint8_t *) &m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), &value->value.v_uint8, 16);
+ memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16),
+ &value->value.v_uint8, 16);
#endif
- success = true;
- }
- else if (reg == vfp_fpsr)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&m_state.context.vfp.__fpsr, &value->value.uint32, 4);
+ success = true;
+ } else if (reg == vfp_fpsr) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4);
#else
- memcpy (((uint8_t *) &m_state.context.vfp.opaque) + (32 * 16) + 0, &value->value.uint32, 4);
+ memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0,
+ &value->value.uint32, 4);
#endif
- success = true;
- }
- else if (reg == vfp_fpcr)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&m_state.context.vfp.__fpcr, &value->value.uint32, 4);
+ success = true;
+ } else if (reg == vfp_fpcr) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4);
#else
- memcpy (((uint8_t *) m_state.context.vfp.opaque) + (32 * 16) + 4, &value->value.uint32, 4);
+ memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4,
+ &value->value.uint32, 4);
#endif
- success = true;
- }
- else if (reg >= vfp_s0 && reg <= vfp_s31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 4);
+ success = true;
+ } else if (reg >= vfp_s0 && reg <= vfp_s31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8,
+ 4);
#else
- memcpy (((uint8_t *) &m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), &value->value.v_uint8, 4);
+ memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16),
+ &value->value.v_uint8, 4);
#endif
- success = true;
- }
- else if (reg >= vfp_d0 && reg <= vfp_d31)
- {
-#if defined (__arm64__) || defined (__aarch64__)
- memcpy (&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 8);
+ success = true;
+ } else if (reg >= vfp_d0 && reg <= vfp_d31) {
+#if defined(__arm64__) || defined(__aarch64__)
+ memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8,
+ 8);
#else
- memcpy (((uint8_t *) &m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), &value->value.v_uint8, 8);
+ memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16),
+ &value->value.v_uint8, 8);
#endif
- success = true;
- }
- break;
-
- case e_regSetEXC:
- if (reg == exc_far)
- {
- m_state.context.exc.__far = value->value.uint64;
- success = true;
- }
- else if (reg == exc_esr)
- {
- m_state.context.exc.__esr = value->value.uint32;
- success = true;
- }
- else if (reg == exc_exception)
- {
- m_state.context.exc.__exception = value->value.uint32;
- success = true;
- }
- break;
- }
-
- }
- if (success)
- return SetRegisterState(set) == KERN_SUCCESS;
- return false;
-}
-
-kern_return_t
-DNBArchMachARM64::GetRegisterState(int set, bool force)
-{
- switch (set)
- {
- case e_regSetALL: return GetGPRState(force) |
- GetVFPState(force) |
- GetEXCState(force) |
- GetDBGState(force);
- case e_regSetGPR: return GetGPRState(force);
- case e_regSetVFP: return GetVFPState(force);
- case e_regSetEXC: return GetEXCState(force);
- case e_regSetDBG: return GetDBGState(force);
- default: break;
- }
- return KERN_INVALID_ARGUMENT;
-}
-
-kern_return_t
-DNBArchMachARM64::SetRegisterState(int set)
-{
- // Make sure we have a valid context to set.
- kern_return_t err = GetRegisterState(set, false);
- if (err != KERN_SUCCESS)
- return err;
-
- switch (set)
- {
- case e_regSetALL: return SetGPRState() |
- SetVFPState() |
- SetEXCState() |
- SetDBGState(false);
- case e_regSetGPR: return SetGPRState();
- case e_regSetVFP: return SetVFPState();
- case e_regSetEXC: return SetEXCState();
- case e_regSetDBG: return SetDBGState(false);
- default: break;
- }
- return KERN_INVALID_ARGUMENT;
-}
-
-bool
-DNBArchMachARM64::RegisterSetStateIsValid (int set) const
-{
- return m_state.RegsAreValid(set);
-}
-
-
-nub_size_t
-DNBArchMachARM64::GetRegisterContext (void *buf, nub_size_t buf_len)
-{
- nub_size_t size = sizeof (m_state.context.gpr) +
- sizeof (m_state.context.vfp) +
- sizeof (m_state.context.exc);
-
- if (buf && buf_len)
- {
- if (size > buf_len)
- size = buf_len;
-
- bool force = false;
- if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
- return 0;
-
- // Copy each struct individually to avoid any padding that might be between the structs in m_state.context
- uint8_t *p = (uint8_t *)buf;
- ::memcpy (p, &m_state.context.gpr, sizeof(m_state.context.gpr));
- p += sizeof(m_state.context.gpr);
- ::memcpy (p, &m_state.context.vfp, sizeof(m_state.context.vfp));
- p += sizeof(m_state.context.vfp);
- ::memcpy (p, &m_state.context.exc, sizeof(m_state.context.exc));
- p += sizeof(m_state.context.exc);
-
- size_t bytes_written = p - (uint8_t *)buf;
- UNUSED_IF_ASSERT_DISABLED(bytes_written);
- assert (bytes_written == size);
- }
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size);
- // Return the size of the register context even if NULL was passed in
- return size;
-}
-
-nub_size_t
-DNBArchMachARM64::SetRegisterContext (const void *buf, nub_size_t buf_len)
-{
- nub_size_t size = sizeof (m_state.context.gpr) +
- sizeof (m_state.context.vfp) +
- sizeof (m_state.context.exc);
-
- if (buf == NULL || buf_len == 0)
- size = 0;
-
- if (size)
- {
- if (size > buf_len)
- size = buf_len;
-
- // Copy each struct individually to avoid any padding that might be between the structs in m_state.context
- uint8_t *p = (uint8_t *)buf;
- ::memcpy (&m_state.context.gpr, p, sizeof(m_state.context.gpr));
- p += sizeof(m_state.context.gpr);
- ::memcpy (&m_state.context.vfp, p, sizeof(m_state.context.vfp));
- p += sizeof(m_state.context.vfp);
- ::memcpy (&m_state.context.exc, p, sizeof(m_state.context.exc));
- p += sizeof(m_state.context.exc);
-
- size_t bytes_written = p - (uint8_t *)buf;
- UNUSED_IF_ASSERT_DISABLED(bytes_written);
- assert (bytes_written == size);
- SetGPRState();
- SetVFPState();
- SetEXCState();
- }
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size);
- return size;
-}
-
-uint32_t
-DNBArchMachARM64::SaveRegisterState ()
-{
- kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
- DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
-
- // Always re-read the registers because above we call thread_abort_safely();
- bool force = true;
-
- if ((kret = GetGPRState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () error: GPR regs failed to read: %u ", kret);
- }
- else if ((kret = GetVFPState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () error: %s regs failed to read: %u", "VFP", kret);
- }
- else
- {
- const uint32_t save_id = GetNextRegisterStateSaveID ();
- m_saved_register_states[save_id] = m_state.context;
- return save_id;
- }
- return UINT32_MAX;
-}
-
-bool
-DNBArchMachARM64::RestoreRegisterState (uint32_t save_id)
-{
- SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
- if (pos != m_saved_register_states.end())
- {
- m_state.context.gpr = pos->second.gpr;
- m_state.context.vfp = pos->second.vfp;
- kern_return_t kret;
- bool success = true;
- if ((kret = SetGPRState()) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState (save_id = %u) error: GPR regs failed to write: %u", save_id, kret);
- success = false;
- }
- else if ((kret = SetVFPState()) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState (save_id = %u) error: %s regs failed to write: %u", save_id, "VFP", kret);
- success = false;
- }
- m_saved_register_states.erase(pos);
- return success;
+ success = true;
+ }
+ break;
+
+ case e_regSetEXC:
+ if (reg == exc_far) {
+ m_state.context.exc.__far = value->value.uint64;
+ success = true;
+ } else if (reg == exc_esr) {
+ m_state.context.exc.__esr = value->value.uint32;
+ success = true;
+ } else if (reg == exc_exception) {
+ m_state.context.exc.__exception = value->value.uint32;
+ success = true;
+ }
+ break;
+ }
+ }
+ if (success)
+ return SetRegisterState(set) == KERN_SUCCESS;
+ return false;
+}
+
+kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) {
+ switch (set) {
+ case e_regSetALL:
+ return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) |
+ GetDBGState(force);
+ case e_regSetGPR:
+ return GetGPRState(force);
+ case e_regSetVFP:
+ return GetVFPState(force);
+ case e_regSetEXC:
+ return GetEXCState(force);
+ case e_regSetDBG:
+ return GetDBGState(force);
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
+}
+
+kern_return_t DNBArchMachARM64::SetRegisterState(int set) {
+ // Make sure we have a valid context to set.
+ kern_return_t err = GetRegisterState(set, false);
+ if (err != KERN_SUCCESS)
+ return err;
+
+ switch (set) {
+ case e_regSetALL:
+ return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false);
+ case e_regSetGPR:
+ return SetGPRState();
+ case e_regSetVFP:
+ return SetVFPState();
+ case e_regSetEXC:
+ return SetEXCState();
+ case e_regSetDBG:
+ return SetDBGState(false);
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
+}
+
+bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const {
+ return m_state.RegsAreValid(set);
+}
+
+nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) {
+ nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
+ sizeof(m_state.context.exc);
+
+ if (buf && buf_len) {
+ if (size > buf_len)
+ size = buf_len;
+
+ bool force = false;
+ if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
+ return 0;
+
+ // Copy each struct individually to avoid any padding that might be between
+ // the structs in m_state.context
+ uint8_t *p = (uint8_t *)buf;
+ ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr));
+ p += sizeof(m_state.context.gpr);
+ ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp));
+ p += sizeof(m_state.context.vfp);
+ ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc));
+ p += sizeof(m_state.context.exc);
+
+ size_t bytes_written = p - (uint8_t *)buf;
+ UNUSED_IF_ASSERT_DISABLED(bytes_written);
+ assert(bytes_written == size);
+ }
+ DNBLogThreadedIf(
+ LOG_THREAD,
+ "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf,
+ buf_len, size);
+ // Return the size of the register context even if NULL was passed in
+ return size;
+}
+
+nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf,
+ nub_size_t buf_len) {
+ nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
+ sizeof(m_state.context.exc);
+
+ if (buf == NULL || buf_len == 0)
+ size = 0;
+
+ if (size) {
+ if (size > buf_len)
+ size = buf_len;
+
+ // Copy each struct individually to avoid any padding that might be between
+ // the structs in m_state.context
+ uint8_t *p = (uint8_t *)buf;
+ ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr));
+ p += sizeof(m_state.context.gpr);
+ ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp));
+ p += sizeof(m_state.context.vfp);
+ ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc));
+ p += sizeof(m_state.context.exc);
+
+ size_t bytes_written = p - (uint8_t *)buf;
+ UNUSED_IF_ASSERT_DISABLED(bytes_written);
+ assert(bytes_written == size);
+ SetGPRState();
+ SetVFPState();
+ SetEXCState();
+ }
+ DNBLogThreadedIf(
+ LOG_THREAD,
+ "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf,
+ buf_len, size);
+ return size;
+}
+
+uint32_t DNBArchMachARM64::SaveRegisterState() {
+ kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
+ DNBLogThreadedIf(
+ LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
+ "(SetGPRState() for stop_count = %u)",
+ m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
+
+ // Always re-read the registers because above we call thread_abort_safely();
+ bool force = true;
+
+ if ((kret = GetGPRState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () "
+ "error: GPR regs failed to read: %u ",
+ kret);
+ } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () "
+ "error: %s regs failed to read: %u",
+ "VFP", kret);
+ } else {
+ const uint32_t save_id = GetNextRegisterStateSaveID();
+ m_saved_register_states[save_id] = m_state.context;
+ return save_id;
+ }
+ return UINT32_MAX;
+}
+
+bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) {
+ SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
+ if (pos != m_saved_register_states.end()) {
+ m_state.context.gpr = pos->second.gpr;
+ m_state.context.vfp = pos->second.vfp;
+ kern_return_t kret;
+ bool success = true;
+ if ((kret = SetGPRState()) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState "
+ "(save_id = %u) error: GPR regs failed to "
+ "write: %u",
+ save_id, kret);
+ success = false;
+ } else if ((kret = SetVFPState()) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState "
+ "(save_id = %u) error: %s regs failed to "
+ "write: %u",
+ save_id, "VFP", kret);
+ success = false;
}
- return false;
+ m_saved_register_states.erase(pos);
+ return success;
+ }
+ return false;
}
-
-#endif // #if defined (ARM_THREAD_STATE64_COUNT)
-#endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
+#endif // #if defined (ARM_THREAD_STATE64_COUNT)
+#endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
Modified: lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.h Tue Sep 6 15:57:50 2016
@@ -7,266 +7,243 @@
//
//===----------------------------------------------------------------------===//
-
#ifndef __DNBArchImplARM64_h__
#define __DNBArchImplARM64_h__
-#if defined (__arm__) || defined (__arm64__) || defined (__aarch64__)
+#if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
-#include <map>
#include <mach/thread_status.h>
+#include <map>
-#if defined (ARM_THREAD_STATE64_COUNT)
+#if defined(ARM_THREAD_STATE64_COUNT)
#include "DNBArch.h"
class MachThread;
-class DNBArchMachARM64 : public DNBArchProtocol
-{
+class DNBArchMachARM64 : public DNBArchProtocol {
public:
- enum { kMaxNumThumbITBreakpoints = 4 };
+ enum { kMaxNumThumbITBreakpoints = 4 };
- DNBArchMachARM64(MachThread *thread) :
- m_thread(thread),
- m_state(),
- m_disabled_watchpoints(),
- m_watchpoint_hw_index(-1),
- m_watchpoint_did_occur(false),
+ DNBArchMachARM64(MachThread *thread)
+ : m_thread(thread), m_state(), m_disabled_watchpoints(),
+ m_watchpoint_hw_index(-1), m_watchpoint_did_occur(false),
m_watchpoint_resume_single_step_enabled(false),
- m_saved_register_states()
- {
- m_disabled_watchpoints.resize (16);
- memset(&m_dbg_save, 0, sizeof(m_dbg_save));
- }
-
- virtual ~DNBArchMachARM64()
- {
- }
-
- static void Initialize();
- static const DNBRegisterSetInfo *
- GetRegisterSetInfo(nub_size_t *num_reg_sets);
-
- virtual bool GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value);
- virtual bool SetRegisterValue(uint32_t set, uint32_t reg, const DNBRegisterValue *value);
- virtual nub_size_t GetRegisterContext (void *buf, nub_size_t buf_len);
- virtual nub_size_t SetRegisterContext (const void *buf, nub_size_t buf_len);
- virtual uint32_t SaveRegisterState ();
- virtual bool RestoreRegisterState (uint32_t save_id);
-
- virtual kern_return_t GetRegisterState (int set, bool force);
- virtual kern_return_t SetRegisterState (int set);
- virtual bool RegisterSetStateIsValid (int set) const;
-
- virtual uint64_t GetPC(uint64_t failValue); // Get program counter
- virtual kern_return_t SetPC(uint64_t value);
- virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
- virtual void ThreadWillResume();
- virtual bool ThreadDidStop();
- virtual bool NotifyException(MachException::Data& exc);
-
- static DNBArchProtocol *Create (MachThread *thread);
- static const uint8_t * SoftwareBreakpointOpcode (nub_size_t byte_size);
- static uint32_t GetCPUType();
-
- virtual uint32_t NumSupportedHardwareWatchpoints();
- virtual uint32_t EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task);
- virtual bool DisableHardwareWatchpoint (uint32_t hw_break_index, bool also_set_on_task);
- virtual bool DisableHardwareWatchpoint_helper (uint32_t hw_break_index, bool also_set_on_task);
+ m_saved_register_states() {
+ m_disabled_watchpoints.resize(16);
+ memset(&m_dbg_save, 0, sizeof(m_dbg_save));
+ }
+
+ virtual ~DNBArchMachARM64() {}
+
+ static void Initialize();
+ static const DNBRegisterSetInfo *GetRegisterSetInfo(nub_size_t *num_reg_sets);
+
+ virtual bool GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value);
+ virtual bool SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value);
+ virtual nub_size_t GetRegisterContext(void *buf, nub_size_t buf_len);
+ virtual nub_size_t SetRegisterContext(const void *buf, nub_size_t buf_len);
+ virtual uint32_t SaveRegisterState();
+ virtual bool RestoreRegisterState(uint32_t save_id);
+
+ virtual kern_return_t GetRegisterState(int set, bool force);
+ virtual kern_return_t SetRegisterState(int set);
+ virtual bool RegisterSetStateIsValid(int set) const;
+
+ virtual uint64_t GetPC(uint64_t failValue); // Get program counter
+ virtual kern_return_t SetPC(uint64_t value);
+ virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
+ virtual void ThreadWillResume();
+ virtual bool ThreadDidStop();
+ virtual bool NotifyException(MachException::Data &exc);
+
+ static DNBArchProtocol *Create(MachThread *thread);
+ static const uint8_t *SoftwareBreakpointOpcode(nub_size_t byte_size);
+ static uint32_t GetCPUType();
+
+ virtual uint32_t NumSupportedHardwareWatchpoints();
+ virtual uint32_t EnableHardwareWatchpoint(nub_addr_t addr, nub_size_t size,
+ bool read, bool write,
+ bool also_set_on_task);
+ virtual bool DisableHardwareWatchpoint(uint32_t hw_break_index,
+ bool also_set_on_task);
+ virtual bool DisableHardwareWatchpoint_helper(uint32_t hw_break_index,
+ bool also_set_on_task);
protected:
+ kern_return_t EnableHardwareSingleStep(bool enable);
+ static bool FixGenericRegisterNumber(uint32_t &set, uint32_t ®);
+ typedef enum RegisterSetTag {
+ e_regSetALL = REGISTER_SET_ALL,
+ e_regSetGPR, // ARM_THREAD_STATE64,
+ e_regSetVFP, // ARM_NEON_STATE64,
+ e_regSetEXC, // ARM_EXCEPTION_STATE64,
+ e_regSetDBG, // ARM_DEBUG_STATE64,
+ kNumRegisterSets
+ } RegisterSet;
+
+ enum {
+ e_regSetGPRCount = ARM_THREAD_STATE64_COUNT,
+ e_regSetVFPCount = ARM_NEON_STATE64_COUNT,
+ e_regSetEXCCount = ARM_EXCEPTION_STATE64_COUNT,
+ e_regSetDBGCount = ARM_DEBUG_STATE64_COUNT,
+ };
+
+ enum { Read = 0, Write = 1, kNumErrors = 2 };
+
+ typedef arm_thread_state64_t GPR;
+ typedef arm_neon_state64_t FPU;
+ typedef arm_exception_state64_t EXC;
+
+ static const DNBRegisterInfo g_gpr_registers[];
+ static const DNBRegisterInfo g_vfp_registers[];
+ static const DNBRegisterInfo g_exc_registers[];
+ static const DNBRegisterSetInfo g_reg_sets[];
+
+ static const size_t k_num_gpr_registers;
+ static const size_t k_num_vfp_registers;
+ static const size_t k_num_exc_registers;
+ static const size_t k_num_all_registers;
+ static const size_t k_num_register_sets;
+
+ struct Context {
+ GPR gpr;
+ FPU vfp;
+ EXC exc;
+ };
+
+ struct State {
+ Context context;
+ arm_debug_state64_t dbg;
+ kern_return_t gpr_errs[2]; // Read/Write errors
+ kern_return_t vfp_errs[2]; // Read/Write errors
+ kern_return_t exc_errs[2]; // Read/Write errors
+ kern_return_t dbg_errs[2]; // Read/Write errors
+ State() {
+ uint32_t i;
+ for (i = 0; i < kNumErrors; i++) {
+ gpr_errs[i] = -1;
+ vfp_errs[i] = -1;
+ exc_errs[i] = -1;
+ dbg_errs[i] = -1;
+ }
+ }
+ void InvalidateRegisterSetState(int set) { SetError(set, Read, -1); }
- kern_return_t EnableHardwareSingleStep (bool enable);
- static bool FixGenericRegisterNumber (uint32_t &set, uint32_t ®);
+ void InvalidateAllRegisterStates() { SetError(e_regSetALL, Read, -1); }
- typedef enum RegisterSetTag
- {
- e_regSetALL = REGISTER_SET_ALL,
- e_regSetGPR, // ARM_THREAD_STATE64,
- e_regSetVFP, // ARM_NEON_STATE64,
- e_regSetEXC, // ARM_EXCEPTION_STATE64,
- e_regSetDBG, // ARM_DEBUG_STATE64,
- kNumRegisterSets
- } RegisterSet;
-
- enum
- {
- e_regSetGPRCount = ARM_THREAD_STATE64_COUNT,
- e_regSetVFPCount = ARM_NEON_STATE64_COUNT,
- e_regSetEXCCount = ARM_EXCEPTION_STATE64_COUNT,
- e_regSetDBGCount = ARM_DEBUG_STATE64_COUNT,
- };
-
- enum
- {
- Read = 0,
- Write = 1,
- kNumErrors = 2
- };
-
- typedef arm_thread_state64_t GPR;
- typedef arm_neon_state64_t FPU;
- typedef arm_exception_state64_t EXC;
-
- static const DNBRegisterInfo g_gpr_registers[];
- static const DNBRegisterInfo g_vfp_registers[];
- static const DNBRegisterInfo g_exc_registers[];
- static const DNBRegisterSetInfo g_reg_sets[];
-
- static const size_t k_num_gpr_registers;
- static const size_t k_num_vfp_registers;
- static const size_t k_num_exc_registers;
- static const size_t k_num_all_registers;
- static const size_t k_num_register_sets;
-
- struct Context
- {
- GPR gpr;
- FPU vfp;
- EXC exc;
- };
-
- struct State
- {
- Context context;
- arm_debug_state64_t dbg;
- kern_return_t gpr_errs[2]; // Read/Write errors
- kern_return_t vfp_errs[2]; // Read/Write errors
- kern_return_t exc_errs[2]; // Read/Write errors
- kern_return_t dbg_errs[2]; // Read/Write errors
- State()
- {
- uint32_t i;
- for (i=0; i<kNumErrors; i++)
- {
- gpr_errs[i] = -1;
- vfp_errs[i] = -1;
- exc_errs[i] = -1;
- dbg_errs[i] = -1;
- }
- }
- void InvalidateRegisterSetState(int set)
- {
- SetError (set, Read, -1);
+ kern_return_t GetError(int set, uint32_t err_idx) const {
+ if (err_idx < kNumErrors) {
+ switch (set) {
+ // When getting all errors, just OR all values together to see if
+ // we got any kind of error.
+ case e_regSetALL:
+ return gpr_errs[err_idx] | vfp_errs[err_idx] | exc_errs[err_idx] |
+ dbg_errs[err_idx];
+ case e_regSetGPR:
+ return gpr_errs[err_idx];
+ case e_regSetVFP:
+ return vfp_errs[err_idx];
+ case e_regSetEXC:
+ return exc_errs[err_idx];
+ // case e_regSetDBG: return dbg_errs[err_idx];
+ default:
+ break;
}
-
- void
- InvalidateAllRegisterStates()
- {
- SetError (e_regSetALL, Read, -1);
- }
-
- kern_return_t GetError (int set, uint32_t err_idx) const
- {
- if (err_idx < kNumErrors)
- {
- switch (set)
- {
- // When getting all errors, just OR all values together to see if
- // we got any kind of error.
- case e_regSetALL: return gpr_errs[err_idx] |
- vfp_errs[err_idx] |
- exc_errs[err_idx] |
- dbg_errs[err_idx] ;
- case e_regSetGPR: return gpr_errs[err_idx];
- case e_regSetVFP: return vfp_errs[err_idx];
- case e_regSetEXC: return exc_errs[err_idx];
- //case e_regSetDBG: return dbg_errs[err_idx];
- default: break;
- }
- }
- return -1;
- }
- bool SetError (int set, uint32_t err_idx, kern_return_t err)
- {
- if (err_idx < kNumErrors)
- {
- switch (set)
- {
- case e_regSetALL:
- gpr_errs[err_idx] = err;
- vfp_errs[err_idx] = err;
- dbg_errs[err_idx] = err;
- exc_errs[err_idx] = err;
- return true;
-
- case e_regSetGPR:
- gpr_errs[err_idx] = err;
- return true;
-
- case e_regSetVFP:
- vfp_errs[err_idx] = err;
- return true;
-
- case e_regSetEXC:
- exc_errs[err_idx] = err;
- return true;
-
-// case e_regSetDBG:
-// dbg_errs[err_idx] = err;
-// return true;
- default: break;
- }
- }
- return false;
- }
- bool RegsAreValid (int set) const
- {
- return GetError(set, Read) == KERN_SUCCESS;
+ }
+ return -1;
+ }
+ bool SetError(int set, uint32_t err_idx, kern_return_t err) {
+ if (err_idx < kNumErrors) {
+ switch (set) {
+ case e_regSetALL:
+ gpr_errs[err_idx] = err;
+ vfp_errs[err_idx] = err;
+ dbg_errs[err_idx] = err;
+ exc_errs[err_idx] = err;
+ return true;
+
+ case e_regSetGPR:
+ gpr_errs[err_idx] = err;
+ return true;
+
+ case e_regSetVFP:
+ vfp_errs[err_idx] = err;
+ return true;
+
+ case e_regSetEXC:
+ exc_errs[err_idx] = err;
+ return true;
+
+ // case e_regSetDBG:
+ // dbg_errs[err_idx] = err;
+ // return true;
+ default:
+ break;
}
- };
+ }
+ return false;
+ }
+ bool RegsAreValid(int set) const {
+ return GetError(set, Read) == KERN_SUCCESS;
+ }
+ };
- kern_return_t GetGPRState (bool force);
- kern_return_t GetVFPState (bool force);
- kern_return_t GetEXCState (bool force);
- kern_return_t GetDBGState (bool force);
-
- kern_return_t SetGPRState ();
- kern_return_t SetVFPState ();
- kern_return_t SetEXCState ();
- kern_return_t SetDBGState (bool also_set_on_task);
-
- // Helper functions for watchpoint implementaions.
-
- typedef arm_debug_state64_t DBG;
-
- void ClearWatchpointOccurred();
- bool HasWatchpointOccurred();
- bool IsWatchpointEnabled(const DBG &debug_state, uint32_t hw_index);
- nub_addr_t GetWatchpointAddressByIndex (uint32_t hw_index);
- nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
- virtual bool ReenableHardwareWatchpoint (uint32_t hw_break_index);
- virtual bool ReenableHardwareWatchpoint_helper (uint32_t hw_break_index);
- virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
-
-
- class disabled_watchpoint {
- public:
- disabled_watchpoint () { addr = 0; control = 0; }
- nub_addr_t addr;
- uint32_t control;
- };
+ kern_return_t GetGPRState(bool force);
+ kern_return_t GetVFPState(bool force);
+ kern_return_t GetEXCState(bool force);
+ kern_return_t GetDBGState(bool force);
+
+ kern_return_t SetGPRState();
+ kern_return_t SetVFPState();
+ kern_return_t SetEXCState();
+ kern_return_t SetDBGState(bool also_set_on_task);
+
+ // Helper functions for watchpoint implementaions.
+
+ typedef arm_debug_state64_t DBG;
+
+ void ClearWatchpointOccurred();
+ bool HasWatchpointOccurred();
+ bool IsWatchpointEnabled(const DBG &debug_state, uint32_t hw_index);
+ nub_addr_t GetWatchpointAddressByIndex(uint32_t hw_index);
+ nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
+ virtual bool ReenableHardwareWatchpoint(uint32_t hw_break_index);
+ virtual bool ReenableHardwareWatchpoint_helper(uint32_t hw_break_index);
+ virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
+
+ class disabled_watchpoint {
+ public:
+ disabled_watchpoint() {
+ addr = 0;
+ control = 0;
+ }
+ nub_addr_t addr;
+ uint32_t control;
+ };
protected:
- MachThread * m_thread;
- State m_state;
- arm_debug_state64_t m_dbg_save;
-
- // arm64 doesn't keep the disabled watchpoint values in the debug register context like armv7;
- // we need to save them aside when we disable them temporarily.
- std::vector<disabled_watchpoint> m_disabled_watchpoints;
-
- // The following member variables should be updated atomically.
- int32_t m_watchpoint_hw_index;
- bool m_watchpoint_did_occur;
- bool m_watchpoint_resume_single_step_enabled;
-
- typedef std::map<uint32_t, Context> SaveRegisterStates;
- SaveRegisterStates m_saved_register_states;
+ MachThread *m_thread;
+ State m_state;
+ arm_debug_state64_t m_dbg_save;
+
+ // arm64 doesn't keep the disabled watchpoint values in the debug register
+ // context like armv7;
+ // we need to save them aside when we disable them temporarily.
+ std::vector<disabled_watchpoint> m_disabled_watchpoints;
+
+ // The following member variables should be updated atomically.
+ int32_t m_watchpoint_hw_index;
+ bool m_watchpoint_did_occur;
+ bool m_watchpoint_resume_single_step_enabled;
+
+ typedef std::map<uint32_t, Context> SaveRegisterStates;
+ SaveRegisterStates m_saved_register_states;
};
-#endif // #if defined (ARM_THREAD_STATE64_COUNT)
-#endif // #if defined (__arm__)
-#endif // #ifndef __DNBArchImplARM64_h__
+#endif // #if defined (ARM_THREAD_STATE64_COUNT)
+#endif // #if defined (__arm__)
+#endif // #ifndef __DNBArchImplARM64_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp Tue Sep 6 15:57:50 2016
@@ -11,51 +11,43 @@
//
//===----------------------------------------------------------------------===//
-#if defined (__i386__) || defined (__x86_64__)
+#if defined(__i386__) || defined(__x86_64__)
#include <sys/cdefs.h>
-#include "MacOSX/i386/DNBArchImplI386.h"
#include "DNBLog.h"
-#include "MachThread.h"
+#include "MacOSX/i386/DNBArchImplI386.h"
#include "MachProcess.h"
+#include "MachThread.h"
extern "C" bool CPUHasAVX(); // Defined over in DNBArchImplX86_64.cpp
-#if defined (LLDB_DEBUGSERVER_RELEASE) || defined (LLDB_DEBUGSERVER_DEBUG)
-enum debugState {
- debugStateUnknown,
- debugStateOff,
- debugStateOn
-};
+#if defined(LLDB_DEBUGSERVER_RELEASE) || defined(LLDB_DEBUGSERVER_DEBUG)
+enum debugState { debugStateUnknown, debugStateOff, debugStateOn };
static debugState sFPUDebugState = debugStateUnknown;
static debugState sAVXForceState = debugStateUnknown;
-static bool DebugFPURegs ()
-{
- if (sFPUDebugState == debugStateUnknown)
- {
- if (getenv("DNB_DEBUG_FPU_REGS"))
- sFPUDebugState = debugStateOn;
- else
- sFPUDebugState = debugStateOff;
- }
-
- return (sFPUDebugState == debugStateOn);
+static bool DebugFPURegs() {
+ if (sFPUDebugState == debugStateUnknown) {
+ if (getenv("DNB_DEBUG_FPU_REGS"))
+ sFPUDebugState = debugStateOn;
+ else
+ sFPUDebugState = debugStateOff;
+ }
+
+ return (sFPUDebugState == debugStateOn);
}
-static bool ForceAVXRegs ()
-{
- if (sFPUDebugState == debugStateUnknown)
- {
- if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS"))
- sAVXForceState = debugStateOn;
- else
- sAVXForceState = debugStateOff;
- }
-
- return (sAVXForceState == debugStateOn);
+static bool ForceAVXRegs() {
+ if (sFPUDebugState == debugStateUnknown) {
+ if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS"))
+ sAVXForceState = debugStateOn;
+ else
+ sAVXForceState = debugStateOff;
+ }
+
+ return (sAVXForceState == debugStateOn);
}
#define DEBUG_FPU_REGS (DebugFPURegs())
@@ -65,1837 +57,2314 @@ static bool ForceAVXRegs ()
#define FORCE_AVX_REGS (0)
#endif
-enum
-{
- gpr_eax = 0,
- gpr_ebx = 1,
- gpr_ecx = 2,
- gpr_edx = 3,
- gpr_edi = 4,
- gpr_esi = 5,
- gpr_ebp = 6,
- gpr_esp = 7,
- gpr_ss = 8,
- gpr_eflags = 9,
- gpr_eip = 10,
- gpr_cs = 11,
- gpr_ds = 12,
- gpr_es = 13,
- gpr_fs = 14,
- gpr_gs = 15,
- gpr_ax ,
- gpr_bx ,
- gpr_cx ,
- gpr_dx ,
- gpr_di ,
- gpr_si ,
- gpr_bp ,
- gpr_sp ,
- gpr_ah ,
- gpr_bh ,
- gpr_ch ,
- gpr_dh ,
- gpr_al ,
- gpr_bl ,
- gpr_cl ,
- gpr_dl ,
- gpr_dil,
- gpr_sil,
- gpr_bpl,
- gpr_spl,
- k_num_gpr_regs
+enum {
+ gpr_eax = 0,
+ gpr_ebx = 1,
+ gpr_ecx = 2,
+ gpr_edx = 3,
+ gpr_edi = 4,
+ gpr_esi = 5,
+ gpr_ebp = 6,
+ gpr_esp = 7,
+ gpr_ss = 8,
+ gpr_eflags = 9,
+ gpr_eip = 10,
+ gpr_cs = 11,
+ gpr_ds = 12,
+ gpr_es = 13,
+ gpr_fs = 14,
+ gpr_gs = 15,
+ gpr_ax,
+ gpr_bx,
+ gpr_cx,
+ gpr_dx,
+ gpr_di,
+ gpr_si,
+ gpr_bp,
+ gpr_sp,
+ gpr_ah,
+ gpr_bh,
+ gpr_ch,
+ gpr_dh,
+ gpr_al,
+ gpr_bl,
+ gpr_cl,
+ gpr_dl,
+ gpr_dil,
+ gpr_sil,
+ gpr_bpl,
+ gpr_spl,
+ k_num_gpr_regs
};
enum {
- fpu_fcw,
- fpu_fsw,
- fpu_ftw,
- fpu_fop,
- fpu_ip,
- fpu_cs,
- fpu_dp,
- fpu_ds,
- fpu_mxcsr,
- fpu_mxcsrmask,
- fpu_stmm0,
- fpu_stmm1,
- fpu_stmm2,
- fpu_stmm3,
- fpu_stmm4,
- fpu_stmm5,
- fpu_stmm6,
- fpu_stmm7,
- fpu_xmm0,
- fpu_xmm1,
- fpu_xmm2,
- fpu_xmm3,
- fpu_xmm4,
- fpu_xmm5,
- fpu_xmm6,
- fpu_xmm7,
- fpu_ymm0,
- fpu_ymm1,
- fpu_ymm2,
- fpu_ymm3,
- fpu_ymm4,
- fpu_ymm5,
- fpu_ymm6,
- fpu_ymm7,
- k_num_fpu_regs,
-
- // Aliases
- fpu_fctrl = fpu_fcw,
- fpu_fstat = fpu_fsw,
- fpu_ftag = fpu_ftw,
- fpu_fiseg = fpu_cs,
- fpu_fioff = fpu_ip,
- fpu_foseg = fpu_ds,
- fpu_fooff = fpu_dp
+ fpu_fcw,
+ fpu_fsw,
+ fpu_ftw,
+ fpu_fop,
+ fpu_ip,
+ fpu_cs,
+ fpu_dp,
+ fpu_ds,
+ fpu_mxcsr,
+ fpu_mxcsrmask,
+ fpu_stmm0,
+ fpu_stmm1,
+ fpu_stmm2,
+ fpu_stmm3,
+ fpu_stmm4,
+ fpu_stmm5,
+ fpu_stmm6,
+ fpu_stmm7,
+ fpu_xmm0,
+ fpu_xmm1,
+ fpu_xmm2,
+ fpu_xmm3,
+ fpu_xmm4,
+ fpu_xmm5,
+ fpu_xmm6,
+ fpu_xmm7,
+ fpu_ymm0,
+ fpu_ymm1,
+ fpu_ymm2,
+ fpu_ymm3,
+ fpu_ymm4,
+ fpu_ymm5,
+ fpu_ymm6,
+ fpu_ymm7,
+ k_num_fpu_regs,
+
+ // Aliases
+ fpu_fctrl = fpu_fcw,
+ fpu_fstat = fpu_fsw,
+ fpu_ftag = fpu_ftw,
+ fpu_fiseg = fpu_cs,
+ fpu_fioff = fpu_ip,
+ fpu_foseg = fpu_ds,
+ fpu_fooff = fpu_dp
};
enum {
- exc_trapno,
- exc_err,
- exc_faultvaddr,
- k_num_exc_regs,
+ exc_trapno,
+ exc_err,
+ exc_faultvaddr,
+ k_num_exc_regs,
};
-
-enum
-{
- ehframe_eax = 0,
- ehframe_ecx,
- ehframe_edx,
- ehframe_ebx,
-
- // On i386 Darwin the eh_frame register numbers for ebp and esp are reversed from DWARF.
- // It's due to an ancient compiler bug in the output of the eh_frame.
- // Specifically, on i386 darwin eh_frame, 4 is ebp, 5 is esp.
- // On i386 darwin debug_frame (and debug_info), 4 is esp, 5 is ebp.
- ehframe_ebp,
- ehframe_esp,
- ehframe_esi,
- ehframe_edi,
- ehframe_eip,
- ehframe_eflags
+enum {
+ ehframe_eax = 0,
+ ehframe_ecx,
+ ehframe_edx,
+ ehframe_ebx,
+
+ // On i386 Darwin the eh_frame register numbers for ebp and esp are reversed
+ // from DWARF.
+ // It's due to an ancient compiler bug in the output of the eh_frame.
+ // Specifically, on i386 darwin eh_frame, 4 is ebp, 5 is esp.
+ // On i386 darwin debug_frame (and debug_info), 4 is esp, 5 is ebp.
+ ehframe_ebp,
+ ehframe_esp,
+ ehframe_esi,
+ ehframe_edi,
+ ehframe_eip,
+ ehframe_eflags
};
-enum
-{
- dwarf_eax = 0,
- dwarf_ecx,
- dwarf_edx,
- dwarf_ebx,
- dwarf_esp,
- dwarf_ebp,
- dwarf_esi,
- dwarf_edi,
- dwarf_eip,
- dwarf_eflags,
- dwarf_stmm0 = 11,
- dwarf_stmm1,
- dwarf_stmm2,
- dwarf_stmm3,
- dwarf_stmm4,
- dwarf_stmm5,
- dwarf_stmm6,
- dwarf_stmm7,
- dwarf_xmm0 = 21,
- dwarf_xmm1,
- dwarf_xmm2,
- dwarf_xmm3,
- dwarf_xmm4,
- dwarf_xmm5,
- dwarf_xmm6,
- dwarf_xmm7,
- dwarf_ymm0 = dwarf_xmm0,
- dwarf_ymm1 = dwarf_xmm1,
- dwarf_ymm2 = dwarf_xmm2,
- dwarf_ymm3 = dwarf_xmm3,
- dwarf_ymm4 = dwarf_xmm4,
- dwarf_ymm5 = dwarf_xmm5,
- dwarf_ymm6 = dwarf_xmm6,
- dwarf_ymm7 = dwarf_xmm7,
+enum {
+ dwarf_eax = 0,
+ dwarf_ecx,
+ dwarf_edx,
+ dwarf_ebx,
+ dwarf_esp,
+ dwarf_ebp,
+ dwarf_esi,
+ dwarf_edi,
+ dwarf_eip,
+ dwarf_eflags,
+ dwarf_stmm0 = 11,
+ dwarf_stmm1,
+ dwarf_stmm2,
+ dwarf_stmm3,
+ dwarf_stmm4,
+ dwarf_stmm5,
+ dwarf_stmm6,
+ dwarf_stmm7,
+ dwarf_xmm0 = 21,
+ dwarf_xmm1,
+ dwarf_xmm2,
+ dwarf_xmm3,
+ dwarf_xmm4,
+ dwarf_xmm5,
+ dwarf_xmm6,
+ dwarf_xmm7,
+ dwarf_ymm0 = dwarf_xmm0,
+ dwarf_ymm1 = dwarf_xmm1,
+ dwarf_ymm2 = dwarf_xmm2,
+ dwarf_ymm3 = dwarf_xmm3,
+ dwarf_ymm4 = dwarf_xmm4,
+ dwarf_ymm5 = dwarf_xmm5,
+ dwarf_ymm6 = dwarf_xmm6,
+ dwarf_ymm7 = dwarf_xmm7,
};
-enum
-{
- debugserver_eax = 0,
- debugserver_ecx = 1,
- debugserver_edx = 2,
- debugserver_ebx = 3,
- debugserver_esp = 4,
- debugserver_ebp = 5,
- debugserver_esi = 6,
- debugserver_edi = 7,
- debugserver_eip = 8,
- debugserver_eflags = 9,
- debugserver_cs = 10,
- debugserver_ss = 11,
- debugserver_ds = 12,
- debugserver_es = 13,
- debugserver_fs = 14,
- debugserver_gs = 15,
- debugserver_stmm0 = 16,
- debugserver_stmm1 = 17,
- debugserver_stmm2 = 18,
- debugserver_stmm3 = 19,
- debugserver_stmm4 = 20,
- debugserver_stmm5 = 21,
- debugserver_stmm6 = 22,
- debugserver_stmm7 = 23,
- debugserver_fctrl = 24, debugserver_fcw = debugserver_fctrl,
- debugserver_fstat = 25, debugserver_fsw = debugserver_fstat,
- debugserver_ftag = 26, debugserver_ftw = debugserver_ftag,
- debugserver_fiseg = 27, debugserver_fpu_cs = debugserver_fiseg,
- debugserver_fioff = 28, debugserver_ip = debugserver_fioff,
- debugserver_foseg = 29, debugserver_fpu_ds = debugserver_foseg,
- debugserver_fooff = 30, debugserver_dp = debugserver_fooff,
- debugserver_fop = 31,
- debugserver_xmm0 = 32,
- debugserver_xmm1 = 33,
- debugserver_xmm2 = 34,
- debugserver_xmm3 = 35,
- debugserver_xmm4 = 36,
- debugserver_xmm5 = 37,
- debugserver_xmm6 = 38,
- debugserver_xmm7 = 39,
- debugserver_mxcsr = 40,
- debugserver_mm0 = 41,
- debugserver_mm1 = 42,
- debugserver_mm2 = 43,
- debugserver_mm3 = 44,
- debugserver_mm4 = 45,
- debugserver_mm5 = 46,
- debugserver_mm6 = 47,
- debugserver_mm7 = 48,
- debugserver_ymm0 = debugserver_xmm0,
- debugserver_ymm1 = debugserver_xmm1,
- debugserver_ymm2 = debugserver_xmm2,
- debugserver_ymm3 = debugserver_xmm3,
- debugserver_ymm4 = debugserver_xmm4,
- debugserver_ymm5 = debugserver_xmm5,
- debugserver_ymm6 = debugserver_xmm6,
- debugserver_ymm7 = debugserver_xmm7
+enum {
+ debugserver_eax = 0,
+ debugserver_ecx = 1,
+ debugserver_edx = 2,
+ debugserver_ebx = 3,
+ debugserver_esp = 4,
+ debugserver_ebp = 5,
+ debugserver_esi = 6,
+ debugserver_edi = 7,
+ debugserver_eip = 8,
+ debugserver_eflags = 9,
+ debugserver_cs = 10,
+ debugserver_ss = 11,
+ debugserver_ds = 12,
+ debugserver_es = 13,
+ debugserver_fs = 14,
+ debugserver_gs = 15,
+ debugserver_stmm0 = 16,
+ debugserver_stmm1 = 17,
+ debugserver_stmm2 = 18,
+ debugserver_stmm3 = 19,
+ debugserver_stmm4 = 20,
+ debugserver_stmm5 = 21,
+ debugserver_stmm6 = 22,
+ debugserver_stmm7 = 23,
+ debugserver_fctrl = 24,
+ debugserver_fcw = debugserver_fctrl,
+ debugserver_fstat = 25,
+ debugserver_fsw = debugserver_fstat,
+ debugserver_ftag = 26,
+ debugserver_ftw = debugserver_ftag,
+ debugserver_fiseg = 27,
+ debugserver_fpu_cs = debugserver_fiseg,
+ debugserver_fioff = 28,
+ debugserver_ip = debugserver_fioff,
+ debugserver_foseg = 29,
+ debugserver_fpu_ds = debugserver_foseg,
+ debugserver_fooff = 30,
+ debugserver_dp = debugserver_fooff,
+ debugserver_fop = 31,
+ debugserver_xmm0 = 32,
+ debugserver_xmm1 = 33,
+ debugserver_xmm2 = 34,
+ debugserver_xmm3 = 35,
+ debugserver_xmm4 = 36,
+ debugserver_xmm5 = 37,
+ debugserver_xmm6 = 38,
+ debugserver_xmm7 = 39,
+ debugserver_mxcsr = 40,
+ debugserver_mm0 = 41,
+ debugserver_mm1 = 42,
+ debugserver_mm2 = 43,
+ debugserver_mm3 = 44,
+ debugserver_mm4 = 45,
+ debugserver_mm5 = 46,
+ debugserver_mm6 = 47,
+ debugserver_mm7 = 48,
+ debugserver_ymm0 = debugserver_xmm0,
+ debugserver_ymm1 = debugserver_xmm1,
+ debugserver_ymm2 = debugserver_xmm2,
+ debugserver_ymm3 = debugserver_xmm3,
+ debugserver_ymm4 = debugserver_xmm4,
+ debugserver_ymm5 = debugserver_xmm5,
+ debugserver_ymm6 = debugserver_xmm6,
+ debugserver_ymm7 = debugserver_xmm7
};
-uint64_t
-DNBArchImplI386::GetPC(uint64_t failValue)
-{
- // Get program counter
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.context.gpr.__eip;
- return failValue;
-}
-
-kern_return_t
-DNBArchImplI386::SetPC(uint64_t value)
-{
- // Get program counter
- kern_return_t err = GetGPRState(false);
- if (err == KERN_SUCCESS)
- {
- m_state.context.gpr.__eip = static_cast<uint32_t>(value);
- err = SetGPRState();
- }
- return err == KERN_SUCCESS;
-}
-
-uint64_t
-DNBArchImplI386::GetSP(uint64_t failValue)
-{
- // Get stack pointer
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.context.gpr.__esp;
- return failValue;
+uint64_t DNBArchImplI386::GetPC(uint64_t failValue) {
+ // Get program counter
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.context.gpr.__eip;
+ return failValue;
+}
+
+kern_return_t DNBArchImplI386::SetPC(uint64_t value) {
+ // Get program counter
+ kern_return_t err = GetGPRState(false);
+ if (err == KERN_SUCCESS) {
+ m_state.context.gpr.__eip = static_cast<uint32_t>(value);
+ err = SetGPRState();
+ }
+ return err == KERN_SUCCESS;
+}
+
+uint64_t DNBArchImplI386::GetSP(uint64_t failValue) {
+ // Get stack pointer
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.context.gpr.__esp;
+ return failValue;
}
// Uncomment the value below to verify the values in the debugger.
//#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED
//#define SET_GPR(reg) m_state.context.gpr.__##reg = gpr_##reg
-kern_return_t
-DNBArchImplI386::GetGPRState(bool force)
-{
- if (force || m_state.GetError(e_regSetGPR, Read))
- {
+kern_return_t DNBArchImplI386::GetGPRState(bool force) {
+ if (force || m_state.GetError(e_regSetGPR, Read)) {
#if DEBUG_GPR_VALUES
- SET_GPR(eax);
- SET_GPR(ebx);
- SET_GPR(ecx);
- SET_GPR(edx);
- SET_GPR(edi);
- SET_GPR(esi);
- SET_GPR(ebp);
- SET_GPR(esp);
- SET_GPR(ss);
- SET_GPR(eflags);
- SET_GPR(eip);
- SET_GPR(cs);
- SET_GPR(ds);
- SET_GPR(es);
- SET_GPR(fs);
- SET_GPR(gs);
- m_state.SetError(e_regSetGPR, Read, 0);
+ SET_GPR(eax);
+ SET_GPR(ebx);
+ SET_GPR(ecx);
+ SET_GPR(edx);
+ SET_GPR(edi);
+ SET_GPR(esi);
+ SET_GPR(ebp);
+ SET_GPR(esp);
+ SET_GPR(ss);
+ SET_GPR(eflags);
+ SET_GPR(eip);
+ SET_GPR(cs);
+ SET_GPR(ds);
+ SET_GPR(es);
+ SET_GPR(fs);
+ SET_GPR(gs);
+ m_state.SetError(e_regSetGPR, Read, 0);
#else
- mach_msg_type_number_t count = e_regSetWordSizeGPR;
- m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count));
+ mach_msg_type_number_t count = e_regSetWordSizeGPR;
+ m_state.SetError(
+ e_regSetGPR, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), __i386_THREAD_STATE,
+ (thread_state_t)&m_state.context.gpr, &count));
#endif
- }
- return m_state.GetError(e_regSetGPR, Read);
+ }
+ return m_state.GetError(e_regSetGPR, Read);
}
// Uncomment the value below to verify the values in the debugger.
//#define DEBUG_FPU_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED
-kern_return_t
-DNBArchImplI386::GetFPUState(bool force)
-{
- if (force || m_state.GetError(e_regSetFPU, Read))
- {
- if (DEBUG_FPU_REGS)
- {
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- m_state.context.fpu.avx.__fpu_reserved[0] = -1;
- m_state.context.fpu.avx.__fpu_reserved[1] = -1;
- *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
- *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
- m_state.context.fpu.avx.__fpu_ftw = 1;
- m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
- m_state.context.fpu.avx.__fpu_fop = 2;
- m_state.context.fpu.avx.__fpu_ip = 3;
- m_state.context.fpu.avx.__fpu_cs = 4;
- m_state.context.fpu.avx.__fpu_rsrv2 = 5;
- m_state.context.fpu.avx.__fpu_dp = 6;
- m_state.context.fpu.avx.__fpu_ds = 7;
- m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
- m_state.context.fpu.avx.__fpu_mxcsr = 8;
- m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
- int i;
- for (i=0; i<16; ++i)
- {
- if (i<10)
- {
- m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
- m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
- m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
- m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
- m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
- m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
- m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
- m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
- }
- else
- {
- m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
- }
-
- m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
- m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
- m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
- m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
- m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
- m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
- m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
- m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
- }
- for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
- m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
- m_state.context.fpu.avx.__fpu_reserved1 = -1;
- for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
- m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
-
- for (i = 0; i < 16; ++i)
- {
- m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
- m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
- m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
- m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
- m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
- m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
- m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
- m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
- }
- }
- else
- {
- m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
- m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
- *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
- *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
- m_state.context.fpu.no_avx.__fpu_ftw = 1;
- m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
- m_state.context.fpu.no_avx.__fpu_fop = 2;
- m_state.context.fpu.no_avx.__fpu_ip = 3;
- m_state.context.fpu.no_avx.__fpu_cs = 4;
- m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
- m_state.context.fpu.no_avx.__fpu_dp = 6;
- m_state.context.fpu.no_avx.__fpu_ds = 7;
- m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
- m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
- m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
- int i;
- for (i=0; i<16; ++i)
- {
- if (i<10)
- {
- m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
- m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
- m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
- m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
- m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
- m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
- m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
- m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
- }
- else
- {
- m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
- }
-
- m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
- m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
- m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
- m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
- m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
- m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
- m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
- m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
- }
- for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
- m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
- m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
- }
- m_state.SetError(e_regSetFPU, Read, 0);
- }
- else
- {
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- mach_msg_type_number_t count = e_regSetWordSizeAVX;
- m_state.SetError (e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count));
- DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &avx, %u (%u passed in)) => 0x%8.8x",
- m_thread->MachPortNumber(), __i386_AVX_STATE, count, e_regSetWordSizeAVX,
- m_state.GetError(e_regSetFPU, Read));
- }
- else
- {
- mach_msg_type_number_t count = e_regSetWordSizeFPU;
- m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count));
- DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, %u (%u passed in) => 0x%8.8x",
- m_thread->MachPortNumber(), __i386_FLOAT_STATE, count, e_regSetWordSizeFPU,
- m_state.GetError(e_regSetFPU, Read));
- }
- }
- }
- return m_state.GetError(e_regSetFPU, Read);
-}
-
-kern_return_t
-DNBArchImplI386::GetEXCState(bool force)
-{
- if (force || m_state.GetError(e_regSetEXC, Read))
- {
- mach_msg_type_number_t count = e_regSetWordSizeEXC;
- m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count));
- }
- return m_state.GetError(e_regSetEXC, Read);
-}
-
-kern_return_t
-DNBArchImplI386::SetGPRState()
-{
- kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
- DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
-
-
- m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR));
- return m_state.GetError(e_regSetGPR, Write);
-}
-
-kern_return_t
-DNBArchImplI386::SetFPUState()
-{
- if (DEBUG_FPU_REGS)
- {
- m_state.SetError(e_regSetFPU, Write, 0);
- return m_state.GetError(e_regSetFPU, Write);
- }
+kern_return_t DNBArchImplI386::GetFPUState(bool force) {
+ if (force || m_state.GetError(e_regSetFPU, Read)) {
+ if (DEBUG_FPU_REGS) {
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ m_state.context.fpu.avx.__fpu_reserved[0] = -1;
+ m_state.context.fpu.avx.__fpu_reserved[1] = -1;
+ *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
+ *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
+ m_state.context.fpu.avx.__fpu_ftw = 1;
+ m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
+ m_state.context.fpu.avx.__fpu_fop = 2;
+ m_state.context.fpu.avx.__fpu_ip = 3;
+ m_state.context.fpu.avx.__fpu_cs = 4;
+ m_state.context.fpu.avx.__fpu_rsrv2 = 5;
+ m_state.context.fpu.avx.__fpu_dp = 6;
+ m_state.context.fpu.avx.__fpu_ds = 7;
+ m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
+ m_state.context.fpu.avx.__fpu_mxcsr = 8;
+ m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
+ int i;
+ for (i = 0; i < 16; ++i) {
+ if (i < 10) {
+ m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
+ m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
+ m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
+ m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
+ m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
+ m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
+ m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
+ m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
+ } else {
+ m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
+ }
+
+ m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
+ m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
+ m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
+ m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
+ m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
+ m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
+ m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
+ m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
+ }
+ for (i = 0; i < sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
+ m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
+ m_state.context.fpu.avx.__fpu_reserved1 = -1;
+ for (i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
+ m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
+
+ for (i = 0; i < 16; ++i) {
+ m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
+ m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
+ m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
+ m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
+ m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
+ m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
+ m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
+ m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
+ }
+ } else {
+ m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
+ m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
+ *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
+ *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
+ m_state.context.fpu.no_avx.__fpu_ftw = 1;
+ m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
+ m_state.context.fpu.no_avx.__fpu_fop = 2;
+ m_state.context.fpu.no_avx.__fpu_ip = 3;
+ m_state.context.fpu.no_avx.__fpu_cs = 4;
+ m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
+ m_state.context.fpu.no_avx.__fpu_dp = 6;
+ m_state.context.fpu.no_avx.__fpu_ds = 7;
+ m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
+ m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
+ m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
+ int i;
+ for (i = 0; i < 16; ++i) {
+ if (i < 10) {
+ m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
+ m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
+ m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
+ m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
+ m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
+ m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
+ m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
+ m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
+ } else {
+ m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
+ }
+
+ m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
+ m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
+ m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
+ m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
+ m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
+ m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
+ m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
+ m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
+ }
+ for (i = 0; i < sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
+ m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
+ m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
+ }
+ m_state.SetError(e_regSetFPU, Read, 0);
+ } else {
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ mach_msg_type_number_t count = e_regSetWordSizeAVX;
+ m_state.SetError(e_regSetFPU, Read,
+ ::thread_get_state(
+ m_thread->MachPortNumber(), __i386_AVX_STATE,
+ (thread_state_t)&m_state.context.fpu.avx, &count));
+ DNBLogThreadedIf(LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &avx, "
+ "%u (%u passed in)) => 0x%8.8x",
+ m_thread->MachPortNumber(), __i386_AVX_STATE, count,
+ e_regSetWordSizeAVX,
+ m_state.GetError(e_regSetFPU, Read));
+ } else {
+ mach_msg_type_number_t count = e_regSetWordSizeFPU;
+ m_state.SetError(
+ e_regSetFPU, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE,
+ (thread_state_t)&m_state.context.fpu.no_avx,
+ &count));
+ DNBLogThreadedIf(LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, "
+ "%u (%u passed in) => 0x%8.8x",
+ m_thread->MachPortNumber(), __i386_FLOAT_STATE, count,
+ e_regSetWordSizeFPU,
+ m_state.GetError(e_regSetFPU, Read));
+ }
+ }
+ }
+ return m_state.GetError(e_regSetFPU, Read);
+}
+
+kern_return_t DNBArchImplI386::GetEXCState(bool force) {
+ if (force || m_state.GetError(e_regSetEXC, Read)) {
+ mach_msg_type_number_t count = e_regSetWordSizeEXC;
+ m_state.SetError(
+ e_regSetEXC, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), __i386_EXCEPTION_STATE,
+ (thread_state_t)&m_state.context.exc, &count));
+ }
+ return m_state.GetError(e_regSetEXC, Read);
+}
+
+kern_return_t DNBArchImplI386::SetGPRState() {
+ kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
+ DNBLogThreadedIf(
+ LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
+ "(SetGPRState() for stop_count = %u)",
+ m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
+
+ m_state.SetError(e_regSetGPR, Write,
+ ::thread_set_state(m_thread->MachPortNumber(),
+ __i386_THREAD_STATE,
+ (thread_state_t)&m_state.context.gpr,
+ e_regSetWordSizeGPR));
+ return m_state.GetError(e_regSetGPR, Write);
+}
+
+kern_return_t DNBArchImplI386::SetFPUState() {
+ if (DEBUG_FPU_REGS) {
+ m_state.SetError(e_regSetFPU, Write, 0);
+ return m_state.GetError(e_regSetFPU, Write);
+ } else {
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ m_state.SetError(
+ e_regSetFPU, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), __i386_AVX_STATE,
+ (thread_state_t)&m_state.context.fpu.avx,
+ e_regSetWordSizeAVX));
else
- {
- if (CPUHasAVX() || FORCE_AVX_REGS)
- m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX));
- else
- m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPU));
- return m_state.GetError(e_regSetFPU, Write);
- }
-}
-
-kern_return_t
-DNBArchImplI386::SetEXCState()
-{
- m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC));
- return m_state.GetError(e_regSetEXC, Write);
-}
-
-kern_return_t
-DNBArchImplI386::GetDBGState(bool force)
-{
- if (force || m_state.GetError(e_regSetDBG, Read))
- {
- mach_msg_type_number_t count = e_regSetWordSizeDBG;
- m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count));
- }
- return m_state.GetError(e_regSetDBG, Read);
-}
+ m_state.SetError(
+ e_regSetFPU, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE,
+ (thread_state_t)&m_state.context.fpu.no_avx,
+ e_regSetWordSizeFPU));
+ return m_state.GetError(e_regSetFPU, Write);
+ }
+}
+
+kern_return_t DNBArchImplI386::SetEXCState() {
+ m_state.SetError(e_regSetEXC, Write,
+ ::thread_set_state(m_thread->MachPortNumber(),
+ __i386_EXCEPTION_STATE,
+ (thread_state_t)&m_state.context.exc,
+ e_regSetWordSizeEXC));
+ return m_state.GetError(e_regSetEXC, Write);
+}
+
+kern_return_t DNBArchImplI386::GetDBGState(bool force) {
+ if (force || m_state.GetError(e_regSetDBG, Read)) {
+ mach_msg_type_number_t count = e_regSetWordSizeDBG;
+ m_state.SetError(
+ e_regSetDBG, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), __i386_DEBUG_STATE,
+ (thread_state_t)&m_state.context.dbg, &count));
+ }
+ return m_state.GetError(e_regSetDBG, Read);
+}
+
+kern_return_t DNBArchImplI386::SetDBGState(bool also_set_on_task) {
+ m_state.SetError(e_regSetDBG, Write,
+ ::thread_set_state(m_thread->MachPortNumber(),
+ __i386_DEBUG_STATE,
+ (thread_state_t)&m_state.context.dbg,
+ e_regSetWordSizeDBG));
+ if (also_set_on_task) {
+ kern_return_t kret = ::task_set_state(
+ m_thread->Process()->Task().TaskPort(), __i386_DEBUG_STATE,
+ (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG);
+ if (kret != KERN_SUCCESS)
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::SetDBGState failed "
+ "to set debug control register state: "
+ "0x%8.8x.",
+ kret);
+ }
+ return m_state.GetError(e_regSetDBG, Write);
+}
+
+void DNBArchImplI386::ThreadWillResume() {
+ // Do we need to step this thread? If so, let the mach thread tell us so.
+ if (m_thread->IsStepping()) {
+ // This is the primary thread, let the arch do anything it needs
+ EnableHardwareSingleStep(true);
+ }
+
+ // Reset the debug status register, if necessary, before we resume.
+ kern_return_t kret = GetDBGState(false);
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchImplI386::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret);
+ if (kret != KERN_SUCCESS)
+ return;
-kern_return_t
-DNBArchImplI386::SetDBGState(bool also_set_on_task)
-{
- m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG));
- if (also_set_on_task)
- {
- kern_return_t kret = ::task_set_state(m_thread->Process()->Task().TaskPort(), __i386_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG);
- if (kret != KERN_SUCCESS)
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::SetDBGState failed to set debug control register state: 0x%8.8x.", kret);
+ DBG &debug_state = m_state.context.dbg;
+ bool need_reset = false;
+ uint32_t i, num = NumSupportedHardwareWatchpoints();
+ for (i = 0; i < num; ++i)
+ if (IsWatchpointHit(debug_state, i))
+ need_reset = true;
+
+ if (need_reset) {
+ ClearWatchpointHits(debug_state);
+ kret = SetDBGState(false);
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchImplI386::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret);
+ }
+}
+
+bool DNBArchImplI386::ThreadDidStop() {
+ bool success = true;
+
+ m_state.InvalidateAllRegisterStates();
+
+ // Are we stepping a single instruction?
+ if (GetGPRState(true) == KERN_SUCCESS) {
+ // We are single stepping, was this the primary thread?
+ if (m_thread->IsStepping()) {
+ // This was the primary thread, we need to clear the trace
+ // bit if so.
+ success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
+ } else {
+ // The MachThread will automatically restore the suspend count
+ // in ThreadDidStop(), so we don't need to do anything here if
+ // we weren't the primary thread the last time
+ }
+ }
+ return success;
+}
+
+bool DNBArchImplI386::NotifyException(MachException::Data &exc) {
+ switch (exc.exc_type) {
+ case EXC_BAD_ACCESS:
+ break;
+ case EXC_BAD_INSTRUCTION:
+ break;
+ case EXC_ARITHMETIC:
+ break;
+ case EXC_EMULATION:
+ break;
+ case EXC_SOFTWARE:
+ break;
+ case EXC_BREAKPOINT:
+ if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) {
+ // exc_code = EXC_I386_BPT
+ //
+ nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS);
+ if (pc != INVALID_NUB_ADDRESS && pc > 0) {
+ pc -= 1;
+ // Check for a breakpoint at one byte prior to the current PC value
+ // since the PC will be just past the trap.
+
+ DNBBreakpoint *bp =
+ m_thread->Process()->Breakpoints().FindByAddress(pc);
+ if (bp) {
+ // Backup the PC for i386 since the trap was taken and the PC
+ // is at the address following the single byte trap instruction.
+ if (m_state.context.gpr.__eip > 0) {
+ m_state.context.gpr.__eip = static_cast<uint32_t>(pc);
+ // Write the new PC back out
+ SetGPRState();
+ }
+ }
+ return true;
+ }
+ } else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1) {
+ // exc_code = EXC_I386_SGL
+ //
+ // Check whether this corresponds to a watchpoint hit event.
+ // If yes, set the exc_sub_code to the data break address.
+ nub_addr_t addr = 0;
+ uint32_t hw_index = GetHardwareWatchpointHit(addr);
+ if (hw_index != INVALID_NUB_HW_INDEX) {
+ exc.exc_data[1] = addr;
+ // Piggyback the hw_index in the exc.data.
+ exc.exc_data.push_back(hw_index);
+ }
+
+ return true;
+ }
+ break;
+ case EXC_SYSCALL:
+ break;
+ case EXC_MACH_SYSCALL:
+ break;
+ case EXC_RPC_ALERT:
+ break;
+ }
+ return false;
+}
+
+uint32_t DNBArchImplI386::NumSupportedHardwareWatchpoints() {
+ // Available debug address registers: dr0, dr1, dr2, dr3.
+ return 4;
+}
+
+static uint32_t size_and_rw_bits(nub_size_t size, bool read, bool write) {
+ uint32_t rw;
+ if (read) {
+ rw = 0x3; // READ or READ/WRITE
+ } else if (write) {
+ rw = 0x1; // WRITE
+ } else {
+ assert(0 && "read and write cannot both be false");
+ }
+
+ switch (size) {
+ case 1:
+ return rw;
+ case 2:
+ return (0x1 << 2) | rw;
+ case 4:
+ return (0x3 << 2) | rw;
+ case 8:
+ return (0x2 << 2) | rw;
+ }
+ assert(0 && "invalid size, must be one of 1, 2, 4, or 8");
+ return 0;
+}
+
+void DNBArchImplI386::SetWatchpoint(DBG &debug_state, uint32_t hw_index,
+ nub_addr_t addr, nub_size_t size, bool read,
+ bool write) {
+ // Set both dr7 (debug control register) and dri (debug address register).
+
+ // dr7{7-0} encodes the local/gloabl enable bits:
+ // global enable --. .-- local enable
+ // | |
+ // v v
+ // dr0 -> bits{1-0}
+ // dr1 -> bits{3-2}
+ // dr2 -> bits{5-4}
+ // dr3 -> bits{7-6}
+ //
+ // dr7{31-16} encodes the rw/len bits:
+ // b_x+3, b_x+2, b_x+1, b_x
+ // where bits{x+1, x} => rw
+ // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io
+ // read-or-write (unused)
+ // and bits{x+3, x+2} => len
+ // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte
+ //
+ // dr0 -> bits{19-16}
+ // dr1 -> bits{23-20}
+ // dr2 -> bits{27-24}
+ // dr3 -> bits{31-28}
+ debug_state.__dr7 |=
+ (1 << (2 * hw_index) |
+ size_and_rw_bits(size, read, write) << (16 + 4 * hw_index));
+ uint32_t addr_32 = addr & 0xffffffff;
+ switch (hw_index) {
+ case 0:
+ debug_state.__dr0 = addr_32;
+ break;
+ case 1:
+ debug_state.__dr1 = addr_32;
+ break;
+ case 2:
+ debug_state.__dr2 = addr_32;
+ break;
+ case 3:
+ debug_state.__dr3 = addr_32;
+ break;
+ default:
+ assert(0 &&
+ "invalid hardware register index, must be one of 0, 1, 2, or 3");
+ }
+ return;
+}
+
+void DNBArchImplI386::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) {
+ debug_state.__dr7 &= ~(3 << (2 * hw_index));
+ switch (hw_index) {
+ case 0:
+ debug_state.__dr0 = 0;
+ break;
+ case 1:
+ debug_state.__dr1 = 0;
+ break;
+ case 2:
+ debug_state.__dr2 = 0;
+ break;
+ case 3:
+ debug_state.__dr3 = 0;
+ break;
+ default:
+ assert(0 &&
+ "invalid hardware register index, must be one of 0, 1, 2, or 3");
+ }
+ return;
+}
+
+bool DNBArchImplI386::IsWatchpointVacant(const DBG &debug_state,
+ uint32_t hw_index) {
+ // Check dr7 (debug control register) for local/global enable bits:
+ // global enable --. .-- local enable
+ // | |
+ // v v
+ // dr0 -> bits{1-0}
+ // dr1 -> bits{3-2}
+ // dr2 -> bits{5-4}
+ // dr3 -> bits{7-6}
+ return (debug_state.__dr7 & (3 << (2 * hw_index))) == 0;
+}
+
+// Resets local copy of debug status register to wait for the next debug
+// exception.
+void DNBArchImplI386::ClearWatchpointHits(DBG &debug_state) {
+ // See also IsWatchpointHit().
+ debug_state.__dr6 = 0;
+ return;
+}
+
+bool DNBArchImplI386::IsWatchpointHit(const DBG &debug_state,
+ uint32_t hw_index) {
+ // Check dr6 (debug status register) whether a watchpoint hits:
+ // is watchpoint hit?
+ // |
+ // v
+ // dr0 -> bits{0}
+ // dr1 -> bits{1}
+ // dr2 -> bits{2}
+ // dr3 -> bits{3}
+ return (debug_state.__dr6 & (1 << hw_index));
+}
+
+nub_addr_t DNBArchImplI386::GetWatchAddress(const DBG &debug_state,
+ uint32_t hw_index) {
+ switch (hw_index) {
+ case 0:
+ return debug_state.__dr0;
+ case 1:
+ return debug_state.__dr1;
+ case 2:
+ return debug_state.__dr2;
+ case 3:
+ return debug_state.__dr3;
+ }
+ assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3");
+ return 0;
+}
+
+bool DNBArchImplI386::StartTransForHWP() {
+ if (m_2pc_trans_state != Trans_Done && m_2pc_trans_state != Trans_Rolled_Back)
+ DNBLogError("%s inconsistent state detected, expected %d or %d, got: %d",
+ __FUNCTION__, Trans_Done, Trans_Rolled_Back, m_2pc_trans_state);
+ m_2pc_dbg_checkpoint = m_state.context.dbg;
+ m_2pc_trans_state = Trans_Pending;
+ return true;
+}
+bool DNBArchImplI386::RollbackTransForHWP() {
+ m_state.context.dbg = m_2pc_dbg_checkpoint;
+ if (m_2pc_trans_state != Trans_Pending)
+ DNBLogError("%s inconsistent state detected, expected %d, got: %d",
+ __FUNCTION__, Trans_Pending, m_2pc_trans_state);
+ m_2pc_trans_state = Trans_Rolled_Back;
+ kern_return_t kret = SetDBGState(false);
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchImplI386::RollbackTransForHWP() SetDBGState() => 0x%8.8x.", kret);
- }
- return m_state.GetError(e_regSetDBG, Write);
+ if (kret == KERN_SUCCESS)
+ return true;
+ else
+ return false;
}
+bool DNBArchImplI386::FinishTransForHWP() {
+ m_2pc_trans_state = Trans_Done;
+ return true;
+}
+DNBArchImplI386::DBG DNBArchImplI386::GetDBGCheckpoint() {
+ return m_2pc_dbg_checkpoint;
+}
+
+uint32_t DNBArchImplI386::EnableHardwareWatchpoint(nub_addr_t addr,
+ nub_size_t size, bool read,
+ bool write,
+ bool also_set_on_task) {
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::EnableHardwareWatchpoint("
+ "addr = 0x%llx, size = %llu, read = %u, "
+ "write = %u)",
+ (uint64_t)addr, (uint64_t)size, read, write);
-void
-DNBArchImplI386::ThreadWillResume()
-{
- // Do we need to step this thread? If so, let the mach thread tell us so.
- if (m_thread->IsStepping())
- {
- // This is the primary thread, let the arch do anything it needs
- EnableHardwareSingleStep(true);
- }
-
- // Reset the debug status register, if necessary, before we resume.
- kern_return_t kret = GetDBGState(false);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret);
- if (kret != KERN_SUCCESS)
- return;
+ const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
- DBG &debug_state = m_state.context.dbg;
- bool need_reset = false;
- uint32_t i, num = NumSupportedHardwareWatchpoints();
- for (i = 0; i < num; ++i)
- if (IsWatchpointHit(debug_state, i))
- need_reset = true;
-
- if (need_reset)
- {
- ClearWatchpointHits(debug_state);
- kret = SetDBGState(false);
- DNBLogThreadedIf(LOG_WATCHPOINTS,"DNBArchImplI386::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret);
- }
-}
+ // Can only watch 1, 2, 4, or 8 bytes.
+ if (!(size == 1 || size == 2 || size == 4 || size == 8))
+ return INVALID_NUB_HW_INDEX;
-bool
-DNBArchImplI386::ThreadDidStop()
-{
- bool success = true;
+ // We must watch for either read or write
+ if (read == false && write == false)
+ return INVALID_NUB_HW_INDEX;
- m_state.InvalidateAllRegisterStates();
+ // Read the debug state
+ kern_return_t kret = GetDBGState(false);
- // Are we stepping a single instruction?
- if (GetGPRState(true) == KERN_SUCCESS)
- {
- // We are single stepping, was this the primary thread?
- if (m_thread->IsStepping())
- {
- // This was the primary thread, we need to clear the trace
- // bit if so.
- success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
- }
- else
- {
- // The MachThread will automatically restore the suspend count
- // in ThreadDidStop(), so we don't need to do anything here if
- // we weren't the primary thread the last time
- }
- }
- return success;
-}
-
-bool
-DNBArchImplI386::NotifyException(MachException::Data& exc)
-{
- switch (exc.exc_type)
- {
- case EXC_BAD_ACCESS:
- break;
- case EXC_BAD_INSTRUCTION:
- break;
- case EXC_ARITHMETIC:
- break;
- case EXC_EMULATION:
- break;
- case EXC_SOFTWARE:
- break;
- case EXC_BREAKPOINT:
- if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2)
- {
- // exc_code = EXC_I386_BPT
- //
- nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS);
- if (pc != INVALID_NUB_ADDRESS && pc > 0)
- {
- pc -= 1;
- // Check for a breakpoint at one byte prior to the current PC value
- // since the PC will be just past the trap.
-
- DNBBreakpoint *bp = m_thread->Process()->Breakpoints().FindByAddress(pc);
- if (bp)
- {
- // Backup the PC for i386 since the trap was taken and the PC
- // is at the address following the single byte trap instruction.
- if (m_state.context.gpr.__eip > 0)
- {
- m_state.context.gpr.__eip = static_cast<uint32_t>(pc);
- // Write the new PC back out
- SetGPRState ();
- }
- }
- return true;
- }
- }
- else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1)
- {
- // exc_code = EXC_I386_SGL
- //
- // Check whether this corresponds to a watchpoint hit event.
- // If yes, set the exc_sub_code to the data break address.
- nub_addr_t addr = 0;
- uint32_t hw_index = GetHardwareWatchpointHit(addr);
- if (hw_index != INVALID_NUB_HW_INDEX)
- {
- exc.exc_data[1] = addr;
- // Piggyback the hw_index in the exc.data.
- exc.exc_data.push_back(hw_index);
- }
+ if (kret == KERN_SUCCESS) {
+ // Check to make sure we have the needed hardware support
+ uint32_t i = 0;
- return true;
- }
- break;
- case EXC_SYSCALL:
- break;
- case EXC_MACH_SYSCALL:
- break;
- case EXC_RPC_ALERT:
+ DBG &debug_state = m_state.context.dbg;
+ for (i = 0; i < num_hw_watchpoints; ++i) {
+ if (IsWatchpointVacant(debug_state, i))
break;
}
- return false;
-}
-
-uint32_t
-DNBArchImplI386::NumSupportedHardwareWatchpoints()
-{
- // Available debug address registers: dr0, dr1, dr2, dr3.
- return 4;
-}
-static uint32_t
-size_and_rw_bits(nub_size_t size, bool read, bool write)
-{
- uint32_t rw;
- if (read) {
- rw = 0x3; // READ or READ/WRITE
- } else if (write) {
- rw = 0x1; // WRITE
+ // See if we found an available hw breakpoint slot above
+ if (i < num_hw_watchpoints) {
+ StartTransForHWP();
+
+ // Modify our local copy of the debug state, first.
+ SetWatchpoint(debug_state, i, addr, size, read, write);
+ // Now set the watch point in the inferior.
+ kret = SetDBGState(also_set_on_task);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::"
+ "EnableHardwareWatchpoint() "
+ "SetDBGState() => 0x%8.8x.",
+ kret);
+
+ if (kret == KERN_SUCCESS)
+ return i;
+ else // Revert to the previous debug state voluntarily. The transaction
+ // coordinator knows that we have failed.
+ m_state.context.dbg = GetDBGCheckpoint();
} else {
- assert(0 && "read and write cannot both be false");
- }
-
- switch (size) {
- case 1:
- return rw;
- case 2:
- return (0x1 << 2) | rw;
- case 4:
- return (0x3 << 2) | rw;
- case 8:
- return (0x2 << 2) | rw;
- }
- assert(0 && "invalid size, must be one of 1, 2, 4, or 8");
- return 0;
-}
-
-void
-DNBArchImplI386::SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write)
-{
- // Set both dr7 (debug control register) and dri (debug address register).
-
- // dr7{7-0} encodes the local/gloabl enable bits:
- // global enable --. .-- local enable
- // | |
- // v v
- // dr0 -> bits{1-0}
- // dr1 -> bits{3-2}
- // dr2 -> bits{5-4}
- // dr3 -> bits{7-6}
- //
- // dr7{31-16} encodes the rw/len bits:
- // b_x+3, b_x+2, b_x+1, b_x
- // where bits{x+1, x} => rw
- // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io read-or-write (unused)
- // and bits{x+3, x+2} => len
- // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte
- //
- // dr0 -> bits{19-16}
- // dr1 -> bits{23-20}
- // dr2 -> bits{27-24}
- // dr3 -> bits{31-28}
- debug_state.__dr7 |= (1 << (2*hw_index) |
- size_and_rw_bits(size, read, write) << (16+4*hw_index));
- uint32_t addr_32 = addr & 0xffffffff;
- switch (hw_index) {
- case 0:
- debug_state.__dr0 = addr_32; break;
- case 1:
- debug_state.__dr1 = addr_32; break;
- case 2:
- debug_state.__dr2 = addr_32; break;
- case 3:
- debug_state.__dr3 = addr_32; break;
- default:
- assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3");
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::"
+ "EnableHardwareWatchpoint(): All "
+ "hardware resources (%u) are in use.",
+ num_hw_watchpoints);
}
- return;
+ }
+ return INVALID_NUB_HW_INDEX;
}
-void
-DNBArchImplI386::ClearWatchpoint(DBG &debug_state, uint32_t hw_index)
-{
- debug_state.__dr7 &= ~(3 << (2*hw_index));
- switch (hw_index) {
- case 0:
- debug_state.__dr0 = 0; break;
- case 1:
- debug_state.__dr1 = 0; break;
- case 2:
- debug_state.__dr2 = 0; break;
- case 3:
- debug_state.__dr3 = 0; break;
- default:
- assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3");
- }
- return;
-}
+bool DNBArchImplI386::DisableHardwareWatchpoint(uint32_t hw_index,
+ bool also_set_on_task) {
+ kern_return_t kret = GetDBGState(false);
-bool
-DNBArchImplI386::IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index)
-{
- // Check dr7 (debug control register) for local/global enable bits:
- // global enable --. .-- local enable
- // | |
- // v v
- // dr0 -> bits{1-0}
- // dr1 -> bits{3-2}
- // dr2 -> bits{5-4}
- // dr3 -> bits{7-6}
- return (debug_state.__dr7 & (3 << (2*hw_index))) == 0;
-}
-
-// Resets local copy of debug status register to wait for the next debug exception.
-void
-DNBArchImplI386::ClearWatchpointHits(DBG &debug_state)
-{
- // See also IsWatchpointHit().
- debug_state.__dr6 = 0;
- return;
-}
-
-bool
-DNBArchImplI386::IsWatchpointHit(const DBG &debug_state, uint32_t hw_index)
-{
- // Check dr6 (debug status register) whether a watchpoint hits:
- // is watchpoint hit?
- // |
- // v
- // dr0 -> bits{0}
- // dr1 -> bits{1}
- // dr2 -> bits{2}
- // dr3 -> bits{3}
- return (debug_state.__dr6 & (1 << hw_index));
-}
-
-nub_addr_t
-DNBArchImplI386::GetWatchAddress(const DBG &debug_state, uint32_t hw_index)
-{
- switch (hw_index) {
- case 0:
- return debug_state.__dr0;
- case 1:
- return debug_state.__dr1;
- case 2:
- return debug_state.__dr2;
- case 3:
- return debug_state.__dr3;
- }
- assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3");
- return 0;
-}
-
-bool
-DNBArchImplI386::StartTransForHWP()
-{
- if (m_2pc_trans_state != Trans_Done && m_2pc_trans_state != Trans_Rolled_Back)
- DNBLogError ("%s inconsistent state detected, expected %d or %d, got: %d", __FUNCTION__, Trans_Done, Trans_Rolled_Back, m_2pc_trans_state);
- m_2pc_dbg_checkpoint = m_state.context.dbg;
- m_2pc_trans_state = Trans_Pending;
- return true;
-}
-bool
-DNBArchImplI386::RollbackTransForHWP()
-{
- m_state.context.dbg = m_2pc_dbg_checkpoint;
- if (m_2pc_trans_state != Trans_Pending)
- DNBLogError ("%s inconsistent state detected, expected %d, got: %d", __FUNCTION__, Trans_Pending, m_2pc_trans_state);
- m_2pc_trans_state = Trans_Rolled_Back;
- kern_return_t kret = SetDBGState(false);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::RollbackTransForHWP() SetDBGState() => 0x%8.8x.", kret);
+ const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
+ if (kret == KERN_SUCCESS) {
+ DBG &debug_state = m_state.context.dbg;
+ if (hw_index < num_hw_points &&
+ !IsWatchpointVacant(debug_state, hw_index)) {
+ StartTransForHWP();
+
+ // Modify our local copy of the debug state, first.
+ ClearWatchpoint(debug_state, hw_index);
+ // Now disable the watch point in the inferior.
+ kret = SetDBGState(also_set_on_task);
+ DNBLogThreadedIf(LOG_WATCHPOINTS,
+ "DNBArchImplI386::DisableHardwareWatchpoint( %u )",
+ hw_index);
- if (kret == KERN_SUCCESS)
+ if (kret == KERN_SUCCESS)
return true;
- else
- return false;
-}
-bool
-DNBArchImplI386::FinishTransForHWP()
-{
- m_2pc_trans_state = Trans_Done;
- return true;
-}
-DNBArchImplI386::DBG
-DNBArchImplI386::GetDBGCheckpoint()
-{
- return m_2pc_dbg_checkpoint;
-}
-
-uint32_t
-DNBArchImplI386::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task)
-{
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::EnableHardwareWatchpoint(addr = 0x%llx, size = %llu, read = %u, write = %u)", (uint64_t)addr, (uint64_t)size, read, write);
-
- const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
-
- // Can only watch 1, 2, 4, or 8 bytes.
- if (!(size == 1 || size == 2 || size == 4 || size == 8))
- return INVALID_NUB_HW_INDEX;
-
- // We must watch for either read or write
- if (read == false && write == false)
- return INVALID_NUB_HW_INDEX;
-
- // Read the debug state
- kern_return_t kret = GetDBGState(false);
-
- if (kret == KERN_SUCCESS)
- {
- // Check to make sure we have the needed hardware support
- uint32_t i = 0;
-
- DBG &debug_state = m_state.context.dbg;
- for (i = 0; i < num_hw_watchpoints; ++i)
- {
- if (IsWatchpointVacant(debug_state, i))
- break;
- }
-
- // See if we found an available hw breakpoint slot above
- if (i < num_hw_watchpoints)
- {
- StartTransForHWP();
-
- // Modify our local copy of the debug state, first.
- SetWatchpoint(debug_state, i, addr, size, read, write);
- // Now set the watch point in the inferior.
- kret = SetDBGState(also_set_on_task);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret);
-
- if (kret == KERN_SUCCESS)
- return i;
- else // Revert to the previous debug state voluntarily. The transaction coordinator knows that we have failed.
- m_state.context.dbg = GetDBGCheckpoint();
- }
- else
- {
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
- }
+ else // Revert to the previous debug state voluntarily. The transaction
+ // coordinator knows that we have failed.
+ m_state.context.dbg = GetDBGCheckpoint();
}
- return INVALID_NUB_HW_INDEX;
-}
-
-bool
-DNBArchImplI386::DisableHardwareWatchpoint (uint32_t hw_index, bool also_set_on_task)
-{
- kern_return_t kret = GetDBGState(false);
-
- const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
- if (kret == KERN_SUCCESS)
- {
- DBG &debug_state = m_state.context.dbg;
- if (hw_index < num_hw_points && !IsWatchpointVacant(debug_state, hw_index))
- {
- StartTransForHWP();
-
- // Modify our local copy of the debug state, first.
- ClearWatchpoint(debug_state, hw_index);
- // Now disable the watch point in the inferior.
- kret = SetDBGState(also_set_on_task);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::DisableHardwareWatchpoint( %u )",
- hw_index);
-
- if (kret == KERN_SUCCESS)
- return true;
- else // Revert to the previous debug state voluntarily. The transaction coordinator knows that we have failed.
- m_state.context.dbg = GetDBGCheckpoint();
- }
- }
- return false;
+ }
+ return false;
}
// Iterate through the debug status register; return the index of the first hit.
-uint32_t
-DNBArchImplI386::GetHardwareWatchpointHit(nub_addr_t &addr)
-{
- // Read the debug state
- kern_return_t kret = GetDBGState(true);
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret);
- if (kret == KERN_SUCCESS)
- {
- DBG &debug_state = m_state.context.dbg;
- uint32_t i, num = NumSupportedHardwareWatchpoints();
- for (i = 0; i < num; ++i)
- {
- if (IsWatchpointHit(debug_state, i))
- {
- addr = GetWatchAddress(debug_state, i);
- DNBLogThreadedIf(LOG_WATCHPOINTS,
- "DNBArchImplI386::GetHardwareWatchpointHit() found => %u (addr = 0x%llx).",
- i, (uint64_t)addr);
- return i;
- }
- }
+uint32_t DNBArchImplI386::GetHardwareWatchpointHit(nub_addr_t &addr) {
+ // Read the debug state
+ kern_return_t kret = GetDBGState(true);
+ DNBLogThreadedIf(
+ LOG_WATCHPOINTS,
+ "DNBArchImplI386::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.",
+ kret);
+ if (kret == KERN_SUCCESS) {
+ DBG &debug_state = m_state.context.dbg;
+ uint32_t i, num = NumSupportedHardwareWatchpoints();
+ for (i = 0; i < num; ++i) {
+ if (IsWatchpointHit(debug_state, i)) {
+ addr = GetWatchAddress(debug_state, i);
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::"
+ "GetHardwareWatchpointHit() found => "
+ "%u (addr = 0x%llx).",
+ i, (uint64_t)addr);
+ return i;
+ }
}
- return INVALID_NUB_HW_INDEX;
+ }
+ return INVALID_NUB_HW_INDEX;
}
// Set the single step bit in the processor status register.
-kern_return_t
-DNBArchImplI386::EnableHardwareSingleStep (bool enable)
-{
- if (GetGPRState(false) == KERN_SUCCESS)
- {
- const uint32_t trace_bit = 0x100u;
- if (enable)
- m_state.context.gpr.__eflags |= trace_bit;
- else
- m_state.context.gpr.__eflags &= ~trace_bit;
- return SetGPRState();
- }
- return m_state.GetError(e_regSetGPR, Read);
+kern_return_t DNBArchImplI386::EnableHardwareSingleStep(bool enable) {
+ if (GetGPRState(false) == KERN_SUCCESS) {
+ const uint32_t trace_bit = 0x100u;
+ if (enable)
+ m_state.context.gpr.__eflags |= trace_bit;
+ else
+ m_state.context.gpr.__eflags &= ~trace_bit;
+ return SetGPRState();
+ }
+ return m_state.GetError(e_regSetGPR, Read);
}
-
//----------------------------------------------------------------------
// Register information definitions
//----------------------------------------------------------------------
-#define DEFINE_GPR_PSEUDO_16(reg16,reg32) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
-#define DEFINE_GPR_PSEUDO_8H(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
-#define DEFINE_GPR_PSEUDO_8L(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
-
-
-#define GPR_OFFSET(reg) (offsetof (DNBArchImplI386::GPR, __##reg))
-#define FPU_OFFSET(reg) (offsetof (DNBArchImplI386::FPU, __fpu_##reg) + offsetof (DNBArchImplI386::Context, fpu.no_avx))
-#define AVX_OFFSET(reg) (offsetof (DNBArchImplI386::AVX, __fpu_##reg) + offsetof (DNBArchImplI386::Context, fpu.avx))
-#define EXC_OFFSET(reg) (offsetof (DNBArchImplI386::EXC, __##reg) + offsetof (DNBArchImplI386::Context, exc))
-
-#define GPR_SIZE(reg) (sizeof(((DNBArchImplI386::GPR *)NULL)->__##reg))
-#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg))
-#define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__mmst_reg))
-#define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__xmm_reg))
-#define FPU_SIZE_YMM(reg) (32)
-#define EXC_SIZE(reg) (sizeof(((DNBArchImplI386::EXC *)NULL)->__##reg))
+#define DEFINE_GPR_PSEUDO_16(reg16, reg32) \
+ { \
+ e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \
+ INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 \
+ }
+#define DEFINE_GPR_PSEUDO_8H(reg8, reg32) \
+ { \
+ e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 1, INVALID_NUB_REGNUM, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \
+ g_contained_##reg32, g_invalidate_##reg32 \
+ }
+#define DEFINE_GPR_PSEUDO_8L(reg8, reg32) \
+ { \
+ e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 0, INVALID_NUB_REGNUM, \
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \
+ g_contained_##reg32, g_invalidate_##reg32 \
+ }
+
+#define GPR_OFFSET(reg) (offsetof(DNBArchImplI386::GPR, __##reg))
+#define FPU_OFFSET(reg) \
+ (offsetof(DNBArchImplI386::FPU, __fpu_##reg) + \
+ offsetof(DNBArchImplI386::Context, fpu.no_avx))
+#define AVX_OFFSET(reg) \
+ (offsetof(DNBArchImplI386::AVX, __fpu_##reg) + \
+ offsetof(DNBArchImplI386::Context, fpu.avx))
+#define EXC_OFFSET(reg) \
+ (offsetof(DNBArchImplI386::EXC, __##reg) + \
+ offsetof(DNBArchImplI386::Context, exc))
+
+#define GPR_SIZE(reg) (sizeof(((DNBArchImplI386::GPR *)NULL)->__##reg))
+#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg))
+#define FPU_SIZE_MMST(reg) \
+ (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__mmst_reg))
+#define FPU_SIZE_XMM(reg) \
+ (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__xmm_reg))
+#define FPU_SIZE_YMM(reg) (32)
+#define EXC_SIZE(reg) (sizeof(((DNBArchImplI386::EXC *)NULL)->__##reg))
-// This does not accurately identify the location of ymm0...7 in
+// This does not accurately identify the location of ymm0...7 in
// Context.fpu.avx. That is because there is a bunch of padding
// in Context.fpu.avx that we don't need. Offset macros lay out
// the register state that Debugserver transmits to the debugger
// -- not to interpret the thread_get_state info.
-#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n))
+#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n))
// These macros will auto define the register name, alt name, register size,
// register offset, encoding, format and native register. This ensures that
// the register state structures are defined correctly and have the correct
// sizes and offsets.
-const char * g_contained_eax[] = { "eax", NULL };
-const char * g_contained_ebx[] = { "ebx", NULL };
-const char * g_contained_ecx[] = { "ecx", NULL };
-const char * g_contained_edx[] = { "edx", NULL };
-const char * g_contained_edi[] = { "edi", NULL };
-const char * g_contained_esi[] = { "esi", NULL };
-const char * g_contained_ebp[] = { "ebp", NULL };
-const char * g_contained_esp[] = { "esp", NULL };
-
-const char * g_invalidate_eax[] = { "eax", "ax", "ah", "al", NULL };
-const char * g_invalidate_ebx[] = { "ebx", "bx", "bh", "bl", NULL };
-const char * g_invalidate_ecx[] = { "ecx", "cx", "ch", "cl", NULL };
-const char * g_invalidate_edx[] = { "edx", "dx", "dh", "dl", NULL };
-const char * g_invalidate_edi[] = { "edi", "di", "dil", NULL };
-const char * g_invalidate_esi[] = { "esi", "si", "sil", NULL };
-const char * g_invalidate_ebp[] = { "ebp", "bp", "bpl", NULL };
-const char * g_invalidate_esp[] = { "esp", "sp", "spl", NULL };
+const char *g_contained_eax[] = {"eax", NULL};
+const char *g_contained_ebx[] = {"ebx", NULL};
+const char *g_contained_ecx[] = {"ecx", NULL};
+const char *g_contained_edx[] = {"edx", NULL};
+const char *g_contained_edi[] = {"edi", NULL};
+const char *g_contained_esi[] = {"esi", NULL};
+const char *g_contained_ebp[] = {"ebp", NULL};
+const char *g_contained_esp[] = {"esp", NULL};
+
+const char *g_invalidate_eax[] = {"eax", "ax", "ah", "al", NULL};
+const char *g_invalidate_ebx[] = {"ebx", "bx", "bh", "bl", NULL};
+const char *g_invalidate_ecx[] = {"ecx", "cx", "ch", "cl", NULL};
+const char *g_invalidate_edx[] = {"edx", "dx", "dh", "dl", NULL};
+const char *g_invalidate_edi[] = {"edi", "di", "dil", NULL};
+const char *g_invalidate_esi[] = {"esi", "si", "sil", NULL};
+const char *g_invalidate_ebp[] = {"ebp", "bp", "bpl", NULL};
+const char *g_invalidate_esp[] = {"esp", "sp", "spl", NULL};
// General purpose registers for 64 bit
-const DNBRegisterInfo
-DNBArchImplI386::g_gpr_registers[] =
-{
-{ e_regSetGPR, gpr_eax, "eax" , NULL , Uint, Hex, GPR_SIZE(eax), GPR_OFFSET(eax) , ehframe_eax , dwarf_eax , INVALID_NUB_REGNUM , debugserver_eax , NULL, g_invalidate_eax },
-{ e_regSetGPR, gpr_ebx, "ebx" , NULL , Uint, Hex, GPR_SIZE(ebx), GPR_OFFSET(ebx) , ehframe_ebx , dwarf_ebx , INVALID_NUB_REGNUM , debugserver_ebx , NULL, g_invalidate_ebx },
-{ e_regSetGPR, gpr_ecx, "ecx" , NULL , Uint, Hex, GPR_SIZE(ecx), GPR_OFFSET(ecx) , ehframe_ecx , dwarf_ecx , INVALID_NUB_REGNUM , debugserver_ecx , NULL, g_invalidate_ecx },
-{ e_regSetGPR, gpr_edx, "edx" , NULL , Uint, Hex, GPR_SIZE(edx), GPR_OFFSET(edx) , ehframe_edx , dwarf_edx , INVALID_NUB_REGNUM , debugserver_edx , NULL, g_invalidate_edx },
-{ e_regSetGPR, gpr_edi, "edi" , NULL , Uint, Hex, GPR_SIZE(edi), GPR_OFFSET(edi) , ehframe_edi , dwarf_edi , INVALID_NUB_REGNUM , debugserver_edi , NULL, g_invalidate_edi },
-{ e_regSetGPR, gpr_esi, "esi" , NULL , Uint, Hex, GPR_SIZE(esi), GPR_OFFSET(esi) , ehframe_esi , dwarf_esi , INVALID_NUB_REGNUM , debugserver_esi , NULL, g_invalidate_esi },
-{ e_regSetGPR, gpr_ebp, "ebp" , "fp" , Uint, Hex, GPR_SIZE(ebp), GPR_OFFSET(ebp) , ehframe_ebp , dwarf_ebp , GENERIC_REGNUM_FP , debugserver_ebp , NULL, g_invalidate_ebp },
-{ e_regSetGPR, gpr_esp, "esp" , "sp" , Uint, Hex, GPR_SIZE(esp), GPR_OFFSET(esp) , ehframe_esp , dwarf_esp , GENERIC_REGNUM_SP , debugserver_esp , NULL, g_invalidate_esp },
-{ e_regSetGPR, gpr_ss, "ss" , NULL , Uint, Hex, GPR_SIZE(ss), GPR_OFFSET(ss) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM , debugserver_ss , NULL, NULL},
-{ e_regSetGPR, gpr_eflags, "eflags", "flags" , Uint, Hex, GPR_SIZE(eflags), GPR_OFFSET(eflags) , ehframe_eflags , dwarf_eflags , GENERIC_REGNUM_FLAGS , debugserver_eflags, NULL, NULL},
-{ e_regSetGPR, gpr_eip, "eip" , "pc" , Uint, Hex, GPR_SIZE(eip), GPR_OFFSET(eip) , ehframe_eip , dwarf_eip , GENERIC_REGNUM_PC , debugserver_eip , NULL, NULL},
-{ e_regSetGPR, gpr_cs, "cs" , NULL , Uint, Hex, GPR_SIZE(cs), GPR_OFFSET(cs) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM , debugserver_cs , NULL, NULL},
-{ e_regSetGPR, gpr_ds, "ds" , NULL , Uint, Hex, GPR_SIZE(ds), GPR_OFFSET(ds) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM , debugserver_ds , NULL, NULL},
-{ e_regSetGPR, gpr_es, "es" , NULL , Uint, Hex, GPR_SIZE(es), GPR_OFFSET(es) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM , debugserver_es , NULL, NULL},
-{ e_regSetGPR, gpr_fs, "fs" , NULL , Uint, Hex, GPR_SIZE(fs), GPR_OFFSET(fs) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM , debugserver_fs , NULL, NULL},
-{ e_regSetGPR, gpr_gs, "gs" , NULL , Uint, Hex, GPR_SIZE(gs), GPR_OFFSET(gs) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM , debugserver_gs , NULL, NULL},
-DEFINE_GPR_PSEUDO_16 (ax , eax),
-DEFINE_GPR_PSEUDO_16 (bx , ebx),
-DEFINE_GPR_PSEUDO_16 (cx , ecx),
-DEFINE_GPR_PSEUDO_16 (dx , edx),
-DEFINE_GPR_PSEUDO_16 (di , edi),
-DEFINE_GPR_PSEUDO_16 (si , esi),
-DEFINE_GPR_PSEUDO_16 (bp , ebp),
-DEFINE_GPR_PSEUDO_16 (sp , esp),
-DEFINE_GPR_PSEUDO_8H (ah , eax),
-DEFINE_GPR_PSEUDO_8H (bh , ebx),
-DEFINE_GPR_PSEUDO_8H (ch , ecx),
-DEFINE_GPR_PSEUDO_8H (dh , edx),
-DEFINE_GPR_PSEUDO_8L (al , eax),
-DEFINE_GPR_PSEUDO_8L (bl , ebx),
-DEFINE_GPR_PSEUDO_8L (cl , ecx),
-DEFINE_GPR_PSEUDO_8L (dl , edx),
-DEFINE_GPR_PSEUDO_8L (dil, edi),
-DEFINE_GPR_PSEUDO_8L (sil, esi),
-DEFINE_GPR_PSEUDO_8L (bpl, ebp),
-DEFINE_GPR_PSEUDO_8L (spl, esp)
-};
+const DNBRegisterInfo DNBArchImplI386::g_gpr_registers[] = {
+ {e_regSetGPR, gpr_eax, "eax", NULL, Uint, Hex, GPR_SIZE(eax),
+ GPR_OFFSET(eax), ehframe_eax, dwarf_eax, INVALID_NUB_REGNUM,
+ debugserver_eax, NULL, g_invalidate_eax},
+ {e_regSetGPR, gpr_ebx, "ebx", NULL, Uint, Hex, GPR_SIZE(ebx),
+ GPR_OFFSET(ebx), ehframe_ebx, dwarf_ebx, INVALID_NUB_REGNUM,
+ debugserver_ebx, NULL, g_invalidate_ebx},
+ {e_regSetGPR, gpr_ecx, "ecx", NULL, Uint, Hex, GPR_SIZE(ecx),
+ GPR_OFFSET(ecx), ehframe_ecx, dwarf_ecx, INVALID_NUB_REGNUM,
+ debugserver_ecx, NULL, g_invalidate_ecx},
+ {e_regSetGPR, gpr_edx, "edx", NULL, Uint, Hex, GPR_SIZE(edx),
+ GPR_OFFSET(edx), ehframe_edx, dwarf_edx, INVALID_NUB_REGNUM,
+ debugserver_edx, NULL, g_invalidate_edx},
+ {e_regSetGPR, gpr_edi, "edi", NULL, Uint, Hex, GPR_SIZE(edi),
+ GPR_OFFSET(edi), ehframe_edi, dwarf_edi, INVALID_NUB_REGNUM,
+ debugserver_edi, NULL, g_invalidate_edi},
+ {e_regSetGPR, gpr_esi, "esi", NULL, Uint, Hex, GPR_SIZE(esi),
+ GPR_OFFSET(esi), ehframe_esi, dwarf_esi, INVALID_NUB_REGNUM,
+ debugserver_esi, NULL, g_invalidate_esi},
+ {e_regSetGPR, gpr_ebp, "ebp", "fp", Uint, Hex, GPR_SIZE(ebp),
+ GPR_OFFSET(ebp), ehframe_ebp, dwarf_ebp, GENERIC_REGNUM_FP,
+ debugserver_ebp, NULL, g_invalidate_ebp},
+ {e_regSetGPR, gpr_esp, "esp", "sp", Uint, Hex, GPR_SIZE(esp),
+ GPR_OFFSET(esp), ehframe_esp, dwarf_esp, GENERIC_REGNUM_SP,
+ debugserver_esp, NULL, g_invalidate_esp},
+ {e_regSetGPR, gpr_ss, "ss", NULL, Uint, Hex, GPR_SIZE(ss), GPR_OFFSET(ss),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, debugserver_ss,
+ NULL, NULL},
+ {e_regSetGPR, gpr_eflags, "eflags", "flags", Uint, Hex, GPR_SIZE(eflags),
+ GPR_OFFSET(eflags), ehframe_eflags, dwarf_eflags, GENERIC_REGNUM_FLAGS,
+ debugserver_eflags, NULL, NULL},
+ {e_regSetGPR, gpr_eip, "eip", "pc", Uint, Hex, GPR_SIZE(eip),
+ GPR_OFFSET(eip), ehframe_eip, dwarf_eip, GENERIC_REGNUM_PC,
+ debugserver_eip, NULL, NULL},
+ {e_regSetGPR, gpr_cs, "cs", NULL, Uint, Hex, GPR_SIZE(cs), GPR_OFFSET(cs),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, debugserver_cs,
+ NULL, NULL},
+ {e_regSetGPR, gpr_ds, "ds", NULL, Uint, Hex, GPR_SIZE(ds), GPR_OFFSET(ds),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, debugserver_ds,
+ NULL, NULL},
+ {e_regSetGPR, gpr_es, "es", NULL, Uint, Hex, GPR_SIZE(es), GPR_OFFSET(es),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, debugserver_es,
+ NULL, NULL},
+ {e_regSetGPR, gpr_fs, "fs", NULL, Uint, Hex, GPR_SIZE(fs), GPR_OFFSET(fs),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, debugserver_fs,
+ NULL, NULL},
+ {e_regSetGPR, gpr_gs, "gs", NULL, Uint, Hex, GPR_SIZE(gs), GPR_OFFSET(gs),
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, debugserver_gs,
+ NULL, NULL},
+ DEFINE_GPR_PSEUDO_16(ax, eax),
+ DEFINE_GPR_PSEUDO_16(bx, ebx),
+ DEFINE_GPR_PSEUDO_16(cx, ecx),
+ DEFINE_GPR_PSEUDO_16(dx, edx),
+ DEFINE_GPR_PSEUDO_16(di, edi),
+ DEFINE_GPR_PSEUDO_16(si, esi),
+ DEFINE_GPR_PSEUDO_16(bp, ebp),
+ DEFINE_GPR_PSEUDO_16(sp, esp),
+ DEFINE_GPR_PSEUDO_8H(ah, eax),
+ DEFINE_GPR_PSEUDO_8H(bh, ebx),
+ DEFINE_GPR_PSEUDO_8H(ch, ecx),
+ DEFINE_GPR_PSEUDO_8H(dh, edx),
+ DEFINE_GPR_PSEUDO_8L(al, eax),
+ DEFINE_GPR_PSEUDO_8L(bl, ebx),
+ DEFINE_GPR_PSEUDO_8L(cl, ecx),
+ DEFINE_GPR_PSEUDO_8L(dl, edx),
+ DEFINE_GPR_PSEUDO_8L(dil, edi),
+ DEFINE_GPR_PSEUDO_8L(sil, esi),
+ DEFINE_GPR_PSEUDO_8L(bpl, ebp),
+ DEFINE_GPR_PSEUDO_8L(spl, esp)};
+
+const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_no_avx[] = {
+ {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
+ FPU_OFFSET(fcw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
+ FPU_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+ FPU_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
+ FPU_OFFSET(fop), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
+ FPU_OFFSET(ip), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
+ FPU_OFFSET(cs), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
+ FPU_OFFSET(dp), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
+ FPU_OFFSET(ds), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
+ FPU_OFFSET(mxcsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
+ FPU_SIZE_UINT(mxcsrmask), FPU_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+
+ {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
+ INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
+ {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
+ INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
+ {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
+ INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
+ {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
+ INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
+ {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
+ INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
+ {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
+ INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
+ {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
+ INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
+ {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
+ INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
+
+ {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm0), FPU_OFFSET(xmm0), INVALID_NUB_REGNUM, dwarf_xmm0,
+ INVALID_NUB_REGNUM, debugserver_xmm0, NULL, NULL},
+ {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm1), FPU_OFFSET(xmm1), INVALID_NUB_REGNUM, dwarf_xmm1,
+ INVALID_NUB_REGNUM, debugserver_xmm1, NULL, NULL},
+ {e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm2), FPU_OFFSET(xmm2), INVALID_NUB_REGNUM, dwarf_xmm2,
+ INVALID_NUB_REGNUM, debugserver_xmm2, NULL, NULL},
+ {e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm3), FPU_OFFSET(xmm3), INVALID_NUB_REGNUM, dwarf_xmm3,
+ INVALID_NUB_REGNUM, debugserver_xmm3, NULL, NULL},
+ {e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm4), FPU_OFFSET(xmm4), INVALID_NUB_REGNUM, dwarf_xmm4,
+ INVALID_NUB_REGNUM, debugserver_xmm4, NULL, NULL},
+ {e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm5), FPU_OFFSET(xmm5), INVALID_NUB_REGNUM, dwarf_xmm5,
+ INVALID_NUB_REGNUM, debugserver_xmm5, NULL, NULL},
+ {e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm6), FPU_OFFSET(xmm6), INVALID_NUB_REGNUM, dwarf_xmm6,
+ INVALID_NUB_REGNUM, debugserver_xmm6, NULL, NULL},
+ {e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm7), FPU_OFFSET(xmm7), INVALID_NUB_REGNUM, dwarf_xmm7,
+ INVALID_NUB_REGNUM, debugserver_xmm7, NULL, NULL}};
+
+static const char *g_contained_ymm0[] = {"ymm0", NULL};
+static const char *g_contained_ymm1[] = {"ymm1", NULL};
+static const char *g_contained_ymm2[] = {"ymm2", NULL};
+static const char *g_contained_ymm3[] = {"ymm3", NULL};
+static const char *g_contained_ymm4[] = {"ymm4", NULL};
+static const char *g_contained_ymm5[] = {"ymm5", NULL};
+static const char *g_contained_ymm6[] = {"ymm6", NULL};
+static const char *g_contained_ymm7[] = {"ymm7", NULL};
+
+const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx[] = {
+ {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
+ AVX_OFFSET(fcw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
+ AVX_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+ AVX_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
+ AVX_OFFSET(fop), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
+ AVX_OFFSET(ip), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
+ AVX_OFFSET(cs), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
+ AVX_OFFSET(dp), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
+ AVX_OFFSET(ds), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
+ AVX_OFFSET(mxcsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
+ FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+
+ {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
+ INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
+ {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
+ INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
+ {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
+ INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
+ {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
+ INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
+ {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
+ INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
+ {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
+ INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
+ {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
+ INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
+ {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
+ INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
+
+ {e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm0), AVX_OFFSET_YMM(0), INVALID_NUB_REGNUM, dwarf_ymm0,
+ INVALID_NUB_REGNUM, debugserver_ymm0, NULL, NULL},
+ {e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm1), AVX_OFFSET_YMM(1), INVALID_NUB_REGNUM, dwarf_ymm1,
+ INVALID_NUB_REGNUM, debugserver_ymm1, NULL, NULL},
+ {e_regSetFPU, fpu_ymm2, "ymm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm2), AVX_OFFSET_YMM(2), INVALID_NUB_REGNUM, dwarf_ymm2,
+ INVALID_NUB_REGNUM, debugserver_ymm2, NULL, NULL},
+ {e_regSetFPU, fpu_ymm3, "ymm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm3), AVX_OFFSET_YMM(3), INVALID_NUB_REGNUM, dwarf_ymm3,
+ INVALID_NUB_REGNUM, debugserver_ymm3, NULL, NULL},
+ {e_regSetFPU, fpu_ymm4, "ymm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm4), AVX_OFFSET_YMM(4), INVALID_NUB_REGNUM, dwarf_ymm4,
+ INVALID_NUB_REGNUM, debugserver_ymm4, NULL, NULL},
+ {e_regSetFPU, fpu_ymm5, "ymm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm5), AVX_OFFSET_YMM(5), INVALID_NUB_REGNUM, dwarf_ymm5,
+ INVALID_NUB_REGNUM, debugserver_ymm5, NULL, NULL},
+ {e_regSetFPU, fpu_ymm6, "ymm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm6), AVX_OFFSET_YMM(6), INVALID_NUB_REGNUM, dwarf_ymm6,
+ INVALID_NUB_REGNUM, debugserver_ymm6, NULL, NULL},
+ {e_regSetFPU, fpu_ymm7, "ymm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_YMM(ymm7), AVX_OFFSET_YMM(7), INVALID_NUB_REGNUM, dwarf_ymm7,
+ INVALID_NUB_REGNUM, debugserver_ymm7, NULL, NULL},
+
+ {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm0), 0, INVALID_NUB_REGNUM, dwarf_xmm0, INVALID_NUB_REGNUM,
+ debugserver_xmm0, g_contained_ymm0, NULL},
+ {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm1), 0, INVALID_NUB_REGNUM, dwarf_xmm1, INVALID_NUB_REGNUM,
+ debugserver_xmm1, g_contained_ymm1, NULL},
+ {e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm2), 0, INVALID_NUB_REGNUM, dwarf_xmm2, INVALID_NUB_REGNUM,
+ debugserver_xmm2, g_contained_ymm2, NULL},
+ {e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm3), 0, INVALID_NUB_REGNUM, dwarf_xmm3, INVALID_NUB_REGNUM,
+ debugserver_xmm3, g_contained_ymm3, NULL},
+ {e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm4), 0, INVALID_NUB_REGNUM, dwarf_xmm4, INVALID_NUB_REGNUM,
+ debugserver_xmm4, g_contained_ymm4, NULL},
+ {e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm5), 0, INVALID_NUB_REGNUM, dwarf_xmm5, INVALID_NUB_REGNUM,
+ debugserver_xmm5, g_contained_ymm5, NULL},
+ {e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm6), 0, INVALID_NUB_REGNUM, dwarf_xmm6, INVALID_NUB_REGNUM,
+ debugserver_xmm6, g_contained_ymm6, NULL},
+ {e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8,
+ FPU_SIZE_XMM(xmm7), 0, INVALID_NUB_REGNUM, dwarf_xmm7, INVALID_NUB_REGNUM,
+ debugserver_xmm7, g_contained_ymm7, NULL},
-
-const DNBRegisterInfo
-DNBArchImplI386::g_fpu_registers_no_avx[] =
-{
-{ e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-
-{ e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0, INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL },
-{ e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1, INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL },
-{ e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2, INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL },
-{ e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3, INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL },
-{ e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4, INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL },
-{ e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5, INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL },
-{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6, INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL },
-{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7, INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL },
-
-{ e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0), FPU_OFFSET(xmm0), INVALID_NUB_REGNUM, dwarf_xmm0, INVALID_NUB_REGNUM, debugserver_xmm0, NULL, NULL },
-{ e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1), FPU_OFFSET(xmm1), INVALID_NUB_REGNUM, dwarf_xmm1, INVALID_NUB_REGNUM, debugserver_xmm1, NULL, NULL },
-{ e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2), FPU_OFFSET(xmm2), INVALID_NUB_REGNUM, dwarf_xmm2, INVALID_NUB_REGNUM, debugserver_xmm2, NULL, NULL },
-{ e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3), FPU_OFFSET(xmm3), INVALID_NUB_REGNUM, dwarf_xmm3, INVALID_NUB_REGNUM, debugserver_xmm3, NULL, NULL },
-{ e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4), FPU_OFFSET(xmm4), INVALID_NUB_REGNUM, dwarf_xmm4, INVALID_NUB_REGNUM, debugserver_xmm4, NULL, NULL },
-{ e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5), FPU_OFFSET(xmm5), INVALID_NUB_REGNUM, dwarf_xmm5, INVALID_NUB_REGNUM, debugserver_xmm5, NULL, NULL },
-{ e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6), FPU_OFFSET(xmm6), INVALID_NUB_REGNUM, dwarf_xmm6, INVALID_NUB_REGNUM, debugserver_xmm6, NULL, NULL },
-{ e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7), FPU_OFFSET(xmm7), INVALID_NUB_REGNUM, dwarf_xmm7, INVALID_NUB_REGNUM, debugserver_xmm7, NULL, NULL }
};
-
-static const char *g_contained_ymm0 [] = { "ymm0", NULL };
-static const char *g_contained_ymm1 [] = { "ymm1", NULL };
-static const char *g_contained_ymm2 [] = { "ymm2", NULL };
-static const char *g_contained_ymm3 [] = { "ymm3", NULL };
-static const char *g_contained_ymm4 [] = { "ymm4", NULL };
-static const char *g_contained_ymm5 [] = { "ymm5", NULL };
-static const char *g_contained_ymm6 [] = { "ymm6", NULL };
-static const char *g_contained_ymm7 [] = { "ymm7", NULL };
-
-
-const DNBRegisterInfo
-DNBArchImplI386::g_fpu_registers_avx[] =
-{
-{ e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-
-{ e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0, INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL },
-{ e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1, INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL },
-{ e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2, INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL },
-{ e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3, INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL },
-{ e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4, INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL },
-{ e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5, INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL },
-{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6, INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL },
-{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7, INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL },
-
-{ e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0), AVX_OFFSET_YMM(0), INVALID_NUB_REGNUM, dwarf_ymm0, INVALID_NUB_REGNUM, debugserver_ymm0, NULL, NULL },
-{ e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1), AVX_OFFSET_YMM(1), INVALID_NUB_REGNUM, dwarf_ymm1, INVALID_NUB_REGNUM, debugserver_ymm1, NULL, NULL },
-{ e_regSetFPU, fpu_ymm2, "ymm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2), AVX_OFFSET_YMM(2), INVALID_NUB_REGNUM, dwarf_ymm2, INVALID_NUB_REGNUM, debugserver_ymm2, NULL, NULL },
-{ e_regSetFPU, fpu_ymm3, "ymm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3), AVX_OFFSET_YMM(3), INVALID_NUB_REGNUM, dwarf_ymm3, INVALID_NUB_REGNUM, debugserver_ymm3, NULL, NULL },
-{ e_regSetFPU, fpu_ymm4, "ymm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4), AVX_OFFSET_YMM(4), INVALID_NUB_REGNUM, dwarf_ymm4, INVALID_NUB_REGNUM, debugserver_ymm4, NULL, NULL },
-{ e_regSetFPU, fpu_ymm5, "ymm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5), AVX_OFFSET_YMM(5), INVALID_NUB_REGNUM, dwarf_ymm5, INVALID_NUB_REGNUM, debugserver_ymm5, NULL, NULL },
-{ e_regSetFPU, fpu_ymm6, "ymm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6), AVX_OFFSET_YMM(6), INVALID_NUB_REGNUM, dwarf_ymm6, INVALID_NUB_REGNUM, debugserver_ymm6, NULL, NULL },
-{ e_regSetFPU, fpu_ymm7, "ymm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7), AVX_OFFSET_YMM(7), INVALID_NUB_REGNUM, dwarf_ymm7, INVALID_NUB_REGNUM, debugserver_ymm7, NULL, NULL },
-
-{ e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0), 0, INVALID_NUB_REGNUM, dwarf_xmm0, INVALID_NUB_REGNUM, debugserver_xmm0, g_contained_ymm0, NULL },
-{ e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1), 0, INVALID_NUB_REGNUM, dwarf_xmm1, INVALID_NUB_REGNUM, debugserver_xmm1, g_contained_ymm1, NULL },
-{ e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2), 0, INVALID_NUB_REGNUM, dwarf_xmm2, INVALID_NUB_REGNUM, debugserver_xmm2, g_contained_ymm2, NULL },
-{ e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3), 0, INVALID_NUB_REGNUM, dwarf_xmm3, INVALID_NUB_REGNUM, debugserver_xmm3, g_contained_ymm3, NULL },
-{ e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4), 0, INVALID_NUB_REGNUM, dwarf_xmm4, INVALID_NUB_REGNUM, debugserver_xmm4, g_contained_ymm4, NULL },
-{ e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5), 0, INVALID_NUB_REGNUM, dwarf_xmm5, INVALID_NUB_REGNUM, debugserver_xmm5, g_contained_ymm5, NULL },
-{ e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6), 0, INVALID_NUB_REGNUM, dwarf_xmm6, INVALID_NUB_REGNUM, debugserver_xmm6, g_contained_ymm6, NULL },
-{ e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7), 0, INVALID_NUB_REGNUM, dwarf_xmm7, INVALID_NUB_REGNUM, debugserver_xmm7, g_contained_ymm7, NULL },
-
-};
-
-const DNBRegisterInfo
-DNBArchImplI386::g_exc_registers[] =
-{
-{ e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL },
-{ e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL }
-};
+const DNBRegisterInfo DNBArchImplI386::g_exc_registers[] = {
+ {e_regSetEXC, exc_trapno, "trapno", NULL, Uint, Hex, EXC_SIZE(trapno),
+ EXC_OFFSET(trapno), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetEXC, exc_err, "err", NULL, Uint, Hex, EXC_SIZE(err),
+ EXC_OFFSET(err), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
+ {e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex,
+ EXC_SIZE(faultvaddr), EXC_OFFSET(faultvaddr), INVALID_NUB_REGNUM,
+ INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}};
// Number of registers in each register set
-const size_t DNBArchImplI386::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchImplI386::k_num_fpu_registers_no_avx = sizeof(g_fpu_registers_no_avx)/sizeof(DNBRegisterInfo);
-const size_t DNBArchImplI386::k_num_fpu_registers_avx = sizeof(g_fpu_registers_avx)/sizeof(DNBRegisterInfo);
-const size_t DNBArchImplI386::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo);
-const size_t DNBArchImplI386::k_num_all_registers_no_avx = k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers;
-const size_t DNBArchImplI386::k_num_all_registers_avx = k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers;
+const size_t DNBArchImplI386::k_num_gpr_registers =
+ sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchImplI386::k_num_fpu_registers_no_avx =
+ sizeof(g_fpu_registers_no_avx) / sizeof(DNBRegisterInfo);
+const size_t DNBArchImplI386::k_num_fpu_registers_avx =
+ sizeof(g_fpu_registers_avx) / sizeof(DNBRegisterInfo);
+const size_t DNBArchImplI386::k_num_exc_registers =
+ sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
+const size_t DNBArchImplI386::k_num_all_registers_no_avx =
+ k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers;
+const size_t DNBArchImplI386::k_num_all_registers_avx =
+ k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers;
//----------------------------------------------------------------------
// Register set definitions. The first definitions at register set index
// of zero is for all registers, followed by other registers sets. The
// register information for the all register set need not be filled in.
//----------------------------------------------------------------------
-const DNBRegisterSetInfo
-DNBArchImplI386::g_reg_sets_no_avx[] =
-{
- { "i386 Registers", NULL, k_num_all_registers_no_avx },
- { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers },
- { "Floating Point Registers", g_fpu_registers_no_avx, k_num_fpu_registers_no_avx },
- { "Exception State Registers", g_exc_registers, k_num_exc_registers }
-};
-
-const DNBRegisterSetInfo
-DNBArchImplI386::g_reg_sets_avx[] =
-{
- { "i386 Registers", NULL, k_num_all_registers_avx },
- { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers },
- { "Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx },
- { "Exception State Registers", g_exc_registers, k_num_exc_registers }
-};
+const DNBRegisterSetInfo DNBArchImplI386::g_reg_sets_no_avx[] = {
+ {"i386 Registers", NULL, k_num_all_registers_no_avx},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_fpu_registers_no_avx,
+ k_num_fpu_registers_no_avx},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
+
+const DNBRegisterSetInfo DNBArchImplI386::g_reg_sets_avx[] = {
+ {"i386 Registers", NULL, k_num_all_registers_avx},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
// Total number of register sets for this architecture
-const size_t DNBArchImplI386::k_num_register_sets = sizeof(g_reg_sets_no_avx)/sizeof(DNBRegisterSetInfo);
+const size_t DNBArchImplI386::k_num_register_sets =
+ sizeof(g_reg_sets_no_avx) / sizeof(DNBRegisterSetInfo);
-DNBArchProtocol *
-DNBArchImplI386::Create (MachThread *thread)
-{
- DNBArchImplI386 *obj = new DNBArchImplI386 (thread);
- return obj;
-}
-
-const uint8_t *
-DNBArchImplI386::SoftwareBreakpointOpcode (nub_size_t byte_size)
-{
- static const uint8_t g_breakpoint_opcode[] = { 0xCC };
- if (byte_size == 1)
- return g_breakpoint_opcode;
- return NULL;
+DNBArchProtocol *DNBArchImplI386::Create(MachThread *thread) {
+ DNBArchImplI386 *obj = new DNBArchImplI386(thread);
+ return obj;
}
-const DNBRegisterSetInfo *
-DNBArchImplI386::GetRegisterSetInfo(nub_size_t *num_reg_sets)
-{
- *num_reg_sets = k_num_register_sets;
- if (CPUHasAVX() || FORCE_AVX_REGS)
- return g_reg_sets_avx;
- else
- return g_reg_sets_no_avx;
+const uint8_t *DNBArchImplI386::SoftwareBreakpointOpcode(nub_size_t byte_size) {
+ static const uint8_t g_breakpoint_opcode[] = {0xCC};
+ if (byte_size == 1)
+ return g_breakpoint_opcode;
+ return NULL;
}
+const DNBRegisterSetInfo *
+DNBArchImplI386::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
+ *num_reg_sets = k_num_register_sets;
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ return g_reg_sets_avx;
+ else
+ return g_reg_sets_no_avx;
+}
+
+void DNBArchImplI386::Initialize() {
+ DNBArchPluginInfo arch_plugin_info = {
+ CPU_TYPE_I386, DNBArchImplI386::Create,
+ DNBArchImplI386::GetRegisterSetInfo,
+ DNBArchImplI386::SoftwareBreakpointOpcode};
+
+ // Register this arch plug-in with the main protocol class
+ DNBArchProtocol::RegisterArchPlugin(arch_plugin_info);
+}
+
+bool DNBArchImplI386::GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value) {
+ if (set == REGISTER_SET_GENERIC) {
+ switch (reg) {
+ case GENERIC_REGNUM_PC: // Program Counter
+ set = e_regSetGPR;
+ reg = gpr_eip;
+ break;
+
+ case GENERIC_REGNUM_SP: // Stack Pointer
+ set = e_regSetGPR;
+ reg = gpr_esp;
+ break;
+
+ case GENERIC_REGNUM_FP: // Frame Pointer
+ set = e_regSetGPR;
+ reg = gpr_ebp;
+ break;
+
+ case GENERIC_REGNUM_FLAGS: // Processor flags register
+ set = e_regSetGPR;
+ reg = gpr_eflags;
+ break;
-void
-DNBArchImplI386::Initialize()
-{
- DNBArchPluginInfo arch_plugin_info =
- {
- CPU_TYPE_I386,
- DNBArchImplI386::Create,
- DNBArchImplI386::GetRegisterSetInfo,
- DNBArchImplI386::SoftwareBreakpointOpcode
- };
-
- // Register this arch plug-in with the main protocol class
- DNBArchProtocol::RegisterArchPlugin (arch_plugin_info);
-}
-
-bool
-DNBArchImplI386::GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value)
-{
- if (set == REGISTER_SET_GENERIC)
- {
- switch (reg)
- {
- case GENERIC_REGNUM_PC: // Program Counter
- set = e_regSetGPR;
- reg = gpr_eip;
- break;
-
- case GENERIC_REGNUM_SP: // Stack Pointer
- set = e_regSetGPR;
- reg = gpr_esp;
- break;
-
- case GENERIC_REGNUM_FP: // Frame Pointer
- set = e_regSetGPR;
- reg = gpr_ebp;
- break;
-
- case GENERIC_REGNUM_FLAGS: // Processor flags register
- set = e_regSetGPR;
- reg = gpr_eflags;
- break;
-
- case GENERIC_REGNUM_RA: // Return Address
- default:
- return false;
- }
+ case GENERIC_REGNUM_RA: // Return Address
+ default:
+ return false;
}
+ }
- if (GetRegisterState(set, false) != KERN_SUCCESS)
- return false;
-
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- value->info = *regInfo;
- switch (set)
- {
- case e_regSetGPR:
- if (reg < k_num_gpr_registers)
- {
- value->value.uint32 = ((uint32_t*)(&m_state.context.gpr))[reg];
- return true;
- }
- break;
-
- case e_regSetFPU:
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- switch (reg)
- {
- case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true;
- case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true;
- case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true;
- case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true;
- case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true;
- case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true;
- case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true;
- case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true;
- case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true;
- case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true;
-
- case fpu_stmm0: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg, 10); return true;
- case fpu_stmm1: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg, 10); return true;
- case fpu_stmm2: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg, 10); return true;
- case fpu_stmm3: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg, 10); return true;
- case fpu_stmm4: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg, 10); return true;
- case fpu_stmm5: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg, 10); return true;
- case fpu_stmm6: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg, 10); return true;
- case fpu_stmm7: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg, 10); return true;
-
- case fpu_xmm0: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, 16); return true;
- case fpu_xmm1: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, 16); return true;
- case fpu_xmm2: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, 16); return true;
- case fpu_xmm3: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, 16); return true;
- case fpu_xmm4: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, 16); return true;
- case fpu_xmm5: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, 16); return true;
- case fpu_xmm6: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, 16); return true;
- case fpu_xmm7: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, 16); return true;
-
-#define MEMCPY_YMM(n) \
- memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, 16); \
- memcpy((&value->value.uint8) + 16, m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, 16);
- case fpu_ymm0: MEMCPY_YMM(0); return true;
- case fpu_ymm1: MEMCPY_YMM(1); return true;
- case fpu_ymm2: MEMCPY_YMM(2); return true;
- case fpu_ymm3: MEMCPY_YMM(3); return true;
- case fpu_ymm4: MEMCPY_YMM(4); return true;
- case fpu_ymm5: MEMCPY_YMM(5); return true;
- case fpu_ymm6: MEMCPY_YMM(6); return true;
- case fpu_ymm7: MEMCPY_YMM(7); return true;
-#undef MEMCPY_YMM
- }
- }
- else
- {
- switch (reg)
- {
- case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true;
- case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true;
- case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true;
- case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true;
- case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true;
- case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true;
- case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true;
- case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true;
- case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true;
- case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true;
-
- case fpu_stmm0: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, 10); return true;
- case fpu_stmm1: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, 10); return true;
- case fpu_stmm2: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, 10); return true;
- case fpu_stmm3: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, 10); return true;
- case fpu_stmm4: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, 10); return true;
- case fpu_stmm5: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, 10); return true;
- case fpu_stmm6: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, 10); return true;
- case fpu_stmm7: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, 10); return true;
-
- case fpu_xmm0: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16); return true;
- case fpu_xmm1: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16); return true;
- case fpu_xmm2: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16); return true;
- case fpu_xmm3: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16); return true;
- case fpu_xmm4: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16); return true;
- case fpu_xmm5: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16); return true;
- case fpu_xmm6: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16); return true;
- case fpu_xmm7: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16); return true;
- }
- }
- break;
-
- case e_regSetEXC:
- if (reg < k_num_exc_registers)
- {
- value->value.uint32 = (&m_state.context.exc.__trapno)[reg];
- return true;
- }
- break;
- }
- }
+ if (GetRegisterState(set, false) != KERN_SUCCESS)
return false;
-}
-
-
-bool
-DNBArchImplI386::SetRegisterValue(uint32_t set, uint32_t reg, const DNBRegisterValue *value)
-{
- if (set == REGISTER_SET_GENERIC)
- {
- switch (reg)
- {
- case GENERIC_REGNUM_PC: // Program Counter
- set = e_regSetGPR;
- reg = gpr_eip;
- break;
-
- case GENERIC_REGNUM_SP: // Stack Pointer
- set = e_regSetGPR;
- reg = gpr_esp;
- break;
-
- case GENERIC_REGNUM_FP: // Frame Pointer
- set = e_regSetGPR;
- reg = gpr_ebp;
- break;
-
- case GENERIC_REGNUM_FLAGS: // Processor flags register
- set = e_regSetGPR;
- reg = gpr_eflags;
- break;
-
- case GENERIC_REGNUM_RA: // Return Address
- default:
- return false;
- }
- }
- if (GetRegisterState(set, false) != KERN_SUCCESS)
- return false;
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ value->info = *regInfo;
+ switch (set) {
+ case e_regSetGPR:
+ if (reg < k_num_gpr_registers) {
+ value->value.uint32 = ((uint32_t *)(&m_state.context.gpr))[reg];
+ return true;
+ }
+ break;
- bool success = false;
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- switch (set)
- {
- case e_regSetGPR:
- if (reg < k_num_gpr_registers)
- {
- ((uint32_t*)(&m_state.context.gpr))[reg] = value->value.uint32;
- success = true;
- }
- break;
-
- case e_regSetFPU:
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- switch (reg)
- {
- case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break;
- case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break;
- case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break;
- case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break;
- case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break;
- case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break;
- case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break;
- case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break;
- case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break;
- case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
-
- case fpu_stmm0: memcpy (m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm1: memcpy (m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm2: memcpy (m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm3: memcpy (m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm4: memcpy (m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm5: memcpy (m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm6: memcpy (m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm7: memcpy (m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg, &value->value.uint8, 10); success = true; break;
-
- case fpu_xmm0: memcpy(m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm1: memcpy(m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm2: memcpy(m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm3: memcpy(m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm4: memcpy(m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm5: memcpy(m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm6: memcpy(m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm7: memcpy(m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, &value->value.uint8, 16); success = true; break;
-
-#define MEMCPY_YMM(n) \
- memcpy(m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, &value->value.uint8, 16); \
- memcpy(m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, (&value->value.uint8) + 16, 16);
- case fpu_ymm0: MEMCPY_YMM(0); return true;
- case fpu_ymm1: MEMCPY_YMM(1); return true;
- case fpu_ymm2: MEMCPY_YMM(2); return true;
- case fpu_ymm3: MEMCPY_YMM(3); return true;
- case fpu_ymm4: MEMCPY_YMM(4); return true;
- case fpu_ymm5: MEMCPY_YMM(5); return true;
- case fpu_ymm6: MEMCPY_YMM(6); return true;
- case fpu_ymm7: MEMCPY_YMM(7); return true;
+ case e_regSetFPU:
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ switch (reg) {
+ case fpu_fcw:
+ value->value.uint16 =
+ *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw));
+ return true;
+ case fpu_fsw:
+ value->value.uint16 =
+ *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw));
+ return true;
+ case fpu_ftw:
+ value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw;
+ return true;
+ case fpu_fop:
+ value->value.uint16 = m_state.context.fpu.avx.__fpu_fop;
+ return true;
+ case fpu_ip:
+ value->value.uint32 = m_state.context.fpu.avx.__fpu_ip;
+ return true;
+ case fpu_cs:
+ value->value.uint16 = m_state.context.fpu.avx.__fpu_cs;
+ return true;
+ case fpu_dp:
+ value->value.uint32 = m_state.context.fpu.avx.__fpu_dp;
+ return true;
+ case fpu_ds:
+ value->value.uint16 = m_state.context.fpu.avx.__fpu_ds;
+ return true;
+ case fpu_mxcsr:
+ value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr;
+ return true;
+ case fpu_mxcsrmask:
+ value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask;
+ return true;
+
+ case fpu_stmm0:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg, 10);
+ return true;
+ case fpu_stmm1:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg, 10);
+ return true;
+ case fpu_stmm2:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg, 10);
+ return true;
+ case fpu_stmm3:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg, 10);
+ return true;
+ case fpu_stmm4:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg, 10);
+ return true;
+ case fpu_stmm5:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg, 10);
+ return true;
+ case fpu_stmm6:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg, 10);
+ return true;
+ case fpu_stmm7:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg, 10);
+ return true;
+
+ case fpu_xmm0:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, 16);
+ return true;
+ case fpu_xmm1:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, 16);
+ return true;
+ case fpu_xmm2:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, 16);
+ return true;
+ case fpu_xmm3:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, 16);
+ return true;
+ case fpu_xmm4:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, 16);
+ return true;
+ case fpu_xmm5:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, 16);
+ return true;
+ case fpu_xmm6:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, 16);
+ return true;
+ case fpu_xmm7:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, 16);
+ return true;
+
+#define MEMCPY_YMM(n) \
+ memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, \
+ 16); \
+ memcpy((&value->value.uint8) + 16, \
+ m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, 16);
+ case fpu_ymm0:
+ MEMCPY_YMM(0);
+ return true;
+ case fpu_ymm1:
+ MEMCPY_YMM(1);
+ return true;
+ case fpu_ymm2:
+ MEMCPY_YMM(2);
+ return true;
+ case fpu_ymm3:
+ MEMCPY_YMM(3);
+ return true;
+ case fpu_ymm4:
+ MEMCPY_YMM(4);
+ return true;
+ case fpu_ymm5:
+ MEMCPY_YMM(5);
+ return true;
+ case fpu_ymm6:
+ MEMCPY_YMM(6);
+ return true;
+ case fpu_ymm7:
+ MEMCPY_YMM(7);
+ return true;
#undef MEMCPY_YMM
- }
- }
- else
- {
- switch (reg)
- {
- case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break;
- case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break;
- case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break;
- case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break;
- case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break;
- case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break;
- case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break;
- case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break;
- case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break;
- case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
-
- case fpu_stmm0: memcpy (m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm1: memcpy (m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm2: memcpy (m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm3: memcpy (m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm4: memcpy (m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm5: memcpy (m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm6: memcpy (m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, &value->value.uint8, 10); success = true; break;
- case fpu_stmm7: memcpy (m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, &value->value.uint8, 10); success = true; break;
-
- case fpu_xmm0: memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm1: memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm2: memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm3: memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm4: memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm5: memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm6: memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, &value->value.uint8, 16); success = true; break;
- case fpu_xmm7: memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, &value->value.uint8, 16); success = true; break;
- }
- }
- break;
-
- case e_regSetEXC:
- if (reg < k_num_exc_registers)
- {
- (&m_state.context.exc.__trapno)[reg] = value->value.uint32;
- success = true;
- }
- break;
- }
- }
-
- if (success)
- return SetRegisterState(set) == KERN_SUCCESS;
- return false;
-}
-
-
-uint32_t
-DNBArchImplI386::GetRegisterContextSize()
-{
- static uint32_t g_cached_size = 0;
- if (g_cached_size == 0)
- {
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- for (size_t i=0; i<k_num_fpu_registers_avx; ++i)
- {
- if (g_fpu_registers_avx[i].value_regs == NULL)
- g_cached_size += g_fpu_registers_avx[i].size;
- }
- }
- else
- {
- for (size_t i=0; i<k_num_fpu_registers_no_avx; ++i)
- {
- if (g_fpu_registers_no_avx[i].value_regs == NULL)
- g_cached_size += g_fpu_registers_no_avx[i].size;
- }
}
- DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR = %zu, FPU = %u, EXC = %zu", sizeof(GPR), g_cached_size, sizeof(EXC));
- g_cached_size += sizeof(GPR);
- g_cached_size += sizeof(EXC);
- DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR + FPU + EXC = %u", g_cached_size);
+ } else {
+ switch (reg) {
+ case fpu_fcw:
+ value->value.uint16 =
+ *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw));
+ return true;
+ case fpu_fsw:
+ value->value.uint16 =
+ *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
+ return true;
+ case fpu_ftw:
+ value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+ return true;
+ case fpu_fop:
+ value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
+ return true;
+ case fpu_ip:
+ value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip;
+ return true;
+ case fpu_cs:
+ value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs;
+ return true;
+ case fpu_dp:
+ value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp;
+ return true;
+ case fpu_ds:
+ value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds;
+ return true;
+ case fpu_mxcsr:
+ value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr;
+ return true;
+ case fpu_mxcsrmask:
+ value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask;
+ return true;
+
+ case fpu_stmm0:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, 10);
+ return true;
+ case fpu_stmm1:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, 10);
+ return true;
+ case fpu_stmm2:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, 10);
+ return true;
+ case fpu_stmm3:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, 10);
+ return true;
+ case fpu_stmm4:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, 10);
+ return true;
+ case fpu_stmm5:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, 10);
+ return true;
+ case fpu_stmm6:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, 10);
+ return true;
+ case fpu_stmm7:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, 10);
+ return true;
+
+ case fpu_xmm0:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16);
+ return true;
+ case fpu_xmm1:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16);
+ return true;
+ case fpu_xmm2:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16);
+ return true;
+ case fpu_xmm3:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16);
+ return true;
+ case fpu_xmm4:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16);
+ return true;
+ case fpu_xmm5:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16);
+ return true;
+ case fpu_xmm6:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16);
+ return true;
+ case fpu_xmm7:
+ memcpy(&value->value.uint8,
+ m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16);
+ return true;
+ }
+ }
+ break;
+
+ case e_regSetEXC:
+ if (reg < k_num_exc_registers) {
+ value->value.uint32 = (&m_state.context.exc.__trapno)[reg];
+ return true;
+ }
+ break;
}
- return g_cached_size;
+ }
+ return false;
}
+bool DNBArchImplI386::SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value) {
+ if (set == REGISTER_SET_GENERIC) {
+ switch (reg) {
+ case GENERIC_REGNUM_PC: // Program Counter
+ set = e_regSetGPR;
+ reg = gpr_eip;
+ break;
+
+ case GENERIC_REGNUM_SP: // Stack Pointer
+ set = e_regSetGPR;
+ reg = gpr_esp;
+ break;
+
+ case GENERIC_REGNUM_FP: // Frame Pointer
+ set = e_regSetGPR;
+ reg = gpr_ebp;
+ break;
+
+ case GENERIC_REGNUM_FLAGS: // Processor flags register
+ set = e_regSetGPR;
+ reg = gpr_eflags;
+ break;
-nub_size_t
-DNBArchImplI386::GetRegisterContext (void *buf, nub_size_t buf_len)
-{
- uint32_t size = GetRegisterContextSize();
-
- if (buf && buf_len)
- {
- if (size > buf_len)
- size = static_cast<uint32_t>(buf_len);
-
- bool force = false;
- kern_return_t kret;
- if ((kret = GetGPRState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to read: %u ", buf, (uint64_t)buf_len, kret);
- size = 0;
- }
- else if ((kret = GetFPUState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = %p, len = %llu) error: %s regs failed to read: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
- size = 0;
- }
- else if ((kret = GetEXCState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = %p, len = %llu) error: EXC regs failed to read: %u", buf, (uint64_t)buf_len, kret);
- size = 0;
- }
- else
- {
- uint8_t *p = (uint8_t *)buf;
- // Copy the GPR registers
- memcpy(p, &m_state.context.gpr, sizeof(GPR));
- p += sizeof(GPR);
-
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- // Walk around the gaps in the FPU regs
- memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5);
- p += 5;
- memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8);
- p += 8;
- memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6);
- p += 6;
- memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8);
- p += 8;
-
- // Work around the padding between the stmm registers as they are 16
- // byte structs with 10 bytes of the value in each
- for (size_t i=0; i<8; ++i)
- {
- memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10);
- p += 10;
- }
-
- // Interleave the XMM and YMMH registers to make the YMM registers
- for (size_t i=0; i<8; ++i)
- {
- memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16);
- p += 16;
- memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16);
- p += 16;
- }
- }
- else
- {
- // Walk around the gaps in the FPU regs
- memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
- p += 5;
- memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
- p += 8;
- memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
- p += 6;
- memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
- p += 8;
-
- // Work around the padding between the stmm registers as they are 16
- // byte structs with 10 bytes of the value in each
- for (size_t i=0; i<8; ++i)
- {
- memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
- p += 10;
- }
-
- // Copy the XMM registers in a single block
- memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 8 * 16);
- p += 8 * 16;
- }
-
- // Copy the exception registers
- memcpy(p, &m_state.context.exc, sizeof(EXC));
- p += sizeof(EXC);
-
- // make sure we end up with exactly what we think we should have
- size_t bytes_written = p - (uint8_t *)buf;
- UNUSED_IF_ASSERT_DISABLED(bytes_written);
- assert (bytes_written == size);
- }
- }
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
- // Return the size of the register context even if NULL was passed in
- return size;
-}
-
-nub_size_t
-DNBArchImplI386::SetRegisterContext (const void *buf, nub_size_t buf_len)
-{
- nub_size_t size = sizeof (m_state.context);
- if (buf == NULL || buf_len == 0)
- size = 0;
-
- if (size)
- {
- if (size > buf_len)
- size = buf_len;
-
- uint8_t *p = (uint8_t *)buf;
- // Copy the GPR registers
- memcpy(&m_state.context.gpr, p, sizeof(GPR));
- p += sizeof(GPR);
-
- if (CPUHasAVX() || FORCE_AVX_REGS)
- {
- // Walk around the gaps in the FPU regs
- memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5);
- p += 5;
- memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8);
- p += 8;
- memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6);
- p += 6;
- memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8);
- p += 8;
-
- // Work around the padding between the stmm registers as they are 16
- // byte structs with 10 bytes of the value in each
- for (size_t i=0; i<8; ++i)
- {
- memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10);
- p += 10;
- }
-
- // Interleave the XMM and YMMH registers to make the YMM registers
- for (size_t i=0; i<8; ++i)
- {
- memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16);
- p += 16;
- memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16);
- p += 16;
- }
- }
- else
- {
- // Copy fcw through mxcsrmask as there is no padding
- memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
- p += 5;
- memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
- p += 8;
- memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
- p += 6;
- memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
- p += 8;
-
- // Work around the padding between the stmm registers as they are 16
- // byte structs with 10 bytes of the value in each
- for (size_t i=0; i<8; ++i)
- {
- memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
- p += 10;
- }
-
- // Copy the XMM registers in a single block
- memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 8 * 16);
- p += 8 * 16;
- }
-
- // Copy the exception registers
- memcpy(&m_state.context.exc, p, sizeof(EXC));
- p += sizeof(EXC);
-
- // make sure we end up with exactly what we think we should have
- size_t bytes_written = p - (uint8_t *)buf;
- UNUSED_IF_ASSERT_DISABLED(bytes_written);
- assert (bytes_written == size);
- kern_return_t kret;
- if ((kret = SetGPRState()) != KERN_SUCCESS)
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to write: %u", buf, (uint64_t)buf_len, kret);
- if ((kret = SetFPUState()) != KERN_SUCCESS)
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = %p, len = %llu) error: %s regs failed to write: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
- if ((kret = SetEXCState()) != KERN_SUCCESS)
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = %p, len = %llu) error: EXP regs failed to write: %u", buf, (uint64_t)buf_len, kret);
+ case GENERIC_REGNUM_RA: // Return Address
+ default:
+ return false;
}
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
- return size;
-}
-
+ }
-uint32_t
-DNBArchImplI386::SaveRegisterState ()
-{
- kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
- DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
-
- bool force = true;
-
- if ((kret = GetGPRState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SaveRegisterState () error: GPR regs failed to read: %u ", kret);
- }
- else if ((kret = GetFPUState(force)) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SaveRegisterState () error: %s regs failed to read: %u", CPUHasAVX() ? "AVX" : "FPU", kret);
- }
- else
- {
- const uint32_t save_id = GetNextRegisterStateSaveID ();
- m_saved_register_states[save_id] = m_state.context;
- return save_id;
- }
- return 0;
-}
-bool
-DNBArchImplI386::RestoreRegisterState (uint32_t save_id)
-{
- SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
- if (pos != m_saved_register_states.end())
- {
- m_state.context.gpr = pos->second.gpr;
- m_state.context.fpu = pos->second.fpu;
- m_state.context.exc = pos->second.exc;
- m_state.SetError(e_regSetGPR, Read, 0);
- m_state.SetError(e_regSetFPU, Read, 0);
- m_state.SetError(e_regSetEXC, Read, 0);
- kern_return_t kret;
- bool success = true;
- if ((kret = SetGPRState()) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::RestoreRegisterState (save_id = %u) error: GPR regs failed to write: %u", save_id, kret);
- success = false;
- }
- else if ((kret = SetFPUState()) != KERN_SUCCESS)
- {
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::RestoreRegisterState (save_id = %u) error: %s regs failed to write: %u", save_id, CPUHasAVX() ? "AVX" : "FPU", kret);
- success = false;
- }
- m_saved_register_states.erase(pos);
- return success;
- }
+ if (GetRegisterState(set, false) != KERN_SUCCESS)
return false;
-}
-
-kern_return_t
-DNBArchImplI386::GetRegisterState(int set, bool force)
-{
- switch (set)
- {
- case e_regSetALL: return GetGPRState(force) | GetFPUState(force) | GetEXCState(force);
- case e_regSetGPR: return GetGPRState(force);
- case e_regSetFPU: return GetFPUState(force);
- case e_regSetEXC: return GetEXCState(force);
- default: break;
+ bool success = false;
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ switch (set) {
+ case e_regSetGPR:
+ if (reg < k_num_gpr_registers) {
+ ((uint32_t *)(&m_state.context.gpr))[reg] = value->value.uint32;
+ success = true;
+ }
+ break;
+
+ case e_regSetFPU:
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ switch (reg) {
+ case fpu_fcw:
+ *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) =
+ value->value.uint16;
+ success = true;
+ break;
+ case fpu_fsw:
+ *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) =
+ value->value.uint16;
+ success = true;
+ break;
+ case fpu_ftw:
+ m_state.context.fpu.avx.__fpu_ftw = value->value.uint8;
+ success = true;
+ break;
+ case fpu_fop:
+ m_state.context.fpu.avx.__fpu_fop = value->value.uint16;
+ success = true;
+ break;
+ case fpu_ip:
+ m_state.context.fpu.avx.__fpu_ip = value->value.uint32;
+ success = true;
+ break;
+ case fpu_cs:
+ m_state.context.fpu.avx.__fpu_cs = value->value.uint16;
+ success = true;
+ break;
+ case fpu_dp:
+ m_state.context.fpu.avx.__fpu_dp = value->value.uint32;
+ success = true;
+ break;
+ case fpu_ds:
+ m_state.context.fpu.avx.__fpu_ds = value->value.uint16;
+ success = true;
+ break;
+ case fpu_mxcsr:
+ m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32;
+ success = true;
+ break;
+ case fpu_mxcsrmask:
+ m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32;
+ success = true;
+ break;
+
+ case fpu_stmm0:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm1:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm2:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm3:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm4:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm5:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm6:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm7:
+ memcpy(m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+
+ case fpu_xmm0:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm1:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm2:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm3:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm4:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm5:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm6:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm7:
+ memcpy(m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+
+#define MEMCPY_YMM(n) \
+ memcpy(m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, &value->value.uint8, \
+ 16); \
+ memcpy(m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, \
+ (&value->value.uint8) + 16, 16);
+ case fpu_ymm0:
+ MEMCPY_YMM(0);
+ return true;
+ case fpu_ymm1:
+ MEMCPY_YMM(1);
+ return true;
+ case fpu_ymm2:
+ MEMCPY_YMM(2);
+ return true;
+ case fpu_ymm3:
+ MEMCPY_YMM(3);
+ return true;
+ case fpu_ymm4:
+ MEMCPY_YMM(4);
+ return true;
+ case fpu_ymm5:
+ MEMCPY_YMM(5);
+ return true;
+ case fpu_ymm6:
+ MEMCPY_YMM(6);
+ return true;
+ case fpu_ymm7:
+ MEMCPY_YMM(7);
+ return true;
+#undef MEMCPY_YMM
+ }
+ } else {
+ switch (reg) {
+ case fpu_fcw:
+ *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) =
+ value->value.uint16;
+ success = true;
+ break;
+ case fpu_fsw:
+ *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) =
+ value->value.uint16;
+ success = true;
+ break;
+ case fpu_ftw:
+ m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+ success = true;
+ break;
+ case fpu_fop:
+ m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16;
+ success = true;
+ break;
+ case fpu_ip:
+ m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32;
+ success = true;
+ break;
+ case fpu_cs:
+ m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16;
+ success = true;
+ break;
+ case fpu_dp:
+ m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32;
+ success = true;
+ break;
+ case fpu_ds:
+ m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16;
+ success = true;
+ break;
+ case fpu_mxcsr:
+ m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32;
+ success = true;
+ break;
+ case fpu_mxcsrmask:
+ m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32;
+ success = true;
+ break;
+
+ case fpu_stmm0:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm1:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm2:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm3:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm4:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm5:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm6:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+ case fpu_stmm7:
+ memcpy(m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg,
+ &value->value.uint8, 10);
+ success = true;
+ break;
+
+ case fpu_xmm0:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm1:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm2:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm3:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm4:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm5:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm6:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ case fpu_xmm7:
+ memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg,
+ &value->value.uint8, 16);
+ success = true;
+ break;
+ }
+ }
+ break;
+
+ case e_regSetEXC:
+ if (reg < k_num_exc_registers) {
+ (&m_state.context.exc.__trapno)[reg] = value->value.uint32;
+ success = true;
+ }
+ break;
+ }
+ }
+
+ if (success)
+ return SetRegisterState(set) == KERN_SUCCESS;
+ return false;
+}
+
+uint32_t DNBArchImplI386::GetRegisterContextSize() {
+ static uint32_t g_cached_size = 0;
+ if (g_cached_size == 0) {
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ for (size_t i = 0; i < k_num_fpu_registers_avx; ++i) {
+ if (g_fpu_registers_avx[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_avx[i].size;
+ }
+ } else {
+ for (size_t i = 0; i < k_num_fpu_registers_no_avx; ++i) {
+ if (g_fpu_registers_no_avx[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_no_avx[i].size;
+ }
+ }
+ DNBLogThreaded("DNBArchImplX86_64::GetRegisterContextSize() - GPR = %zu, "
+ "FPU = %u, EXC = %zu",
+ sizeof(GPR), g_cached_size, sizeof(EXC));
+ g_cached_size += sizeof(GPR);
+ g_cached_size += sizeof(EXC);
+ DNBLogThreaded(
+ "DNBArchImplX86_64::GetRegisterContextSize() - GPR + FPU + EXC = %u",
+ g_cached_size);
+ }
+ return g_cached_size;
+}
+
+nub_size_t DNBArchImplI386::GetRegisterContext(void *buf, nub_size_t buf_len) {
+ uint32_t size = GetRegisterContextSize();
+
+ if (buf && buf_len) {
+ if (size > buf_len)
+ size = static_cast<uint32_t>(buf_len);
+
+ bool force = false;
+ kern_return_t kret;
+ if ((kret = GetGPRState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = "
+ "%p, len = %llu) error: GPR regs failed to "
+ "read: %u ",
+ buf, (uint64_t)buf_len, kret);
+ size = 0;
+ } else if ((kret = GetFPUState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(
+ LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = %p, len = "
+ "%llu) error: %s regs failed to read: %u",
+ buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
+ size = 0;
+ } else if ((kret = GetEXCState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = "
+ "%p, len = %llu) error: EXC regs failed to "
+ "read: %u",
+ buf, (uint64_t)buf_len, kret);
+ size = 0;
+ } else {
+ uint8_t *p = (uint8_t *)buf;
+ // Copy the GPR registers
+ memcpy(p, &m_state.context.gpr, sizeof(GPR));
+ p += sizeof(GPR);
+
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ // Walk around the gaps in the FPU regs
+ memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5);
+ p += 5;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8);
+ p += 8;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6);
+ p += 6;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10);
+ p += 10;
+ }
+
+ // Interleave the XMM and YMMH registers to make the YMM registers
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16);
+ p += 16;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16);
+ p += 16;
+ }
+ } else {
+ // Walk around the gaps in the FPU regs
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
+ p += 5;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
+ p += 8;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
+ p += 6;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
+ p += 10;
+ }
+
+ // Copy the XMM registers in a single block
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 8 * 16);
+ p += 8 * 16;
+ }
+
+ // Copy the exception registers
+ memcpy(p, &m_state.context.exc, sizeof(EXC));
+ p += sizeof(EXC);
+
+ // make sure we end up with exactly what we think we should have
+ size_t bytes_written = p - (uint8_t *)buf;
+ UNUSED_IF_ASSERT_DISABLED(bytes_written);
+ assert(bytes_written == size);
+ }
+ }
+ DNBLogThreadedIf(
+ LOG_THREAD,
+ "DNBArchImplI386::GetRegisterContext (buf = %p, len = %llu) => %llu", buf,
+ (uint64_t)buf_len, (uint64_t)size);
+ // Return the size of the register context even if NULL was passed in
+ return size;
+}
+
+nub_size_t DNBArchImplI386::SetRegisterContext(const void *buf,
+ nub_size_t buf_len) {
+ nub_size_t size = sizeof(m_state.context);
+ if (buf == NULL || buf_len == 0)
+ size = 0;
+
+ if (size) {
+ if (size > buf_len)
+ size = buf_len;
+
+ uint8_t *p = (uint8_t *)buf;
+ // Copy the GPR registers
+ memcpy(&m_state.context.gpr, p, sizeof(GPR));
+ p += sizeof(GPR);
+
+ if (CPUHasAVX() || FORCE_AVX_REGS) {
+ // Walk around the gaps in the FPU regs
+ memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5);
+ p += 5;
+ memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8);
+ p += 8;
+ memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6);
+ p += 6;
+ memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10);
+ p += 10;
+ }
+
+ // Interleave the XMM and YMMH registers to make the YMM registers
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16);
+ p += 16;
+ memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16);
+ p += 16;
+ }
+ } else {
+ // Copy fcw through mxcsrmask as there is no padding
+ memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
+ p += 5;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
+ p += 8;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
+ p += 6;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i = 0; i < 8; ++i) {
+ memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
+ p += 10;
+ }
+
+ // Copy the XMM registers in a single block
+ memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 8 * 16);
+ p += 8 * 16;
+ }
+
+ // Copy the exception registers
+ memcpy(&m_state.context.exc, p, sizeof(EXC));
+ p += sizeof(EXC);
+
+ // make sure we end up with exactly what we think we should have
+ size_t bytes_written = p - (uint8_t *)buf;
+ UNUSED_IF_ASSERT_DISABLED(bytes_written);
+ assert(bytes_written == size);
+ kern_return_t kret;
+ if ((kret = SetGPRState()) != KERN_SUCCESS)
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = "
+ "%p, len = %llu) error: GPR regs failed to "
+ "write: %u",
+ buf, (uint64_t)buf_len, kret);
+ if ((kret = SetFPUState()) != KERN_SUCCESS)
+ DNBLogThreadedIf(
+ LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = %p, len = "
+ "%llu) error: %s regs failed to write: %u",
+ buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
+ if ((kret = SetEXCState()) != KERN_SUCCESS)
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = "
+ "%p, len = %llu) error: EXP regs failed to "
+ "write: %u",
+ buf, (uint64_t)buf_len, kret);
+ }
+ DNBLogThreadedIf(
+ LOG_THREAD,
+ "DNBArchImplI386::SetRegisterContext (buf = %p, len = %llu) => %llu", buf,
+ (uint64_t)buf_len, (uint64_t)size);
+ return size;
+}
+
+uint32_t DNBArchImplI386::SaveRegisterState() {
+ kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
+ DNBLogThreadedIf(
+ LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
+ "(SetGPRState() for stop_count = %u)",
+ m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
+
+ bool force = true;
+
+ if ((kret = GetGPRState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::SaveRegisterState () error: "
+ "GPR regs failed to read: %u ",
+ kret);
+ } else if ((kret = GetFPUState(force)) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::SaveRegisterState () error: "
+ "%s regs failed to read: %u",
+ CPUHasAVX() ? "AVX" : "FPU", kret);
+ } else {
+ const uint32_t save_id = GetNextRegisterStateSaveID();
+ m_saved_register_states[save_id] = m_state.context;
+ return save_id;
+ }
+ return 0;
+}
+bool DNBArchImplI386::RestoreRegisterState(uint32_t save_id) {
+ SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
+ if (pos != m_saved_register_states.end()) {
+ m_state.context.gpr = pos->second.gpr;
+ m_state.context.fpu = pos->second.fpu;
+ m_state.context.exc = pos->second.exc;
+ m_state.SetError(e_regSetGPR, Read, 0);
+ m_state.SetError(e_regSetFPU, Read, 0);
+ m_state.SetError(e_regSetEXC, Read, 0);
+ kern_return_t kret;
+ bool success = true;
+ if ((kret = SetGPRState()) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::RestoreRegisterState "
+ "(save_id = %u) error: GPR regs failed to "
+ "write: %u",
+ save_id, kret);
+ success = false;
+ } else if ((kret = SetFPUState()) != KERN_SUCCESS) {
+ DNBLogThreadedIf(LOG_THREAD, "DNBArchImplI386::RestoreRegisterState "
+ "(save_id = %u) error: %s regs failed to "
+ "write: %u",
+ save_id, CPUHasAVX() ? "AVX" : "FPU", kret);
+ success = false;
}
- return KERN_INVALID_ARGUMENT;
+ m_saved_register_states.erase(pos);
+ return success;
+ }
+ return false;
}
-kern_return_t
-DNBArchImplI386::SetRegisterState(int set)
-{
- // Make sure we have a valid context to set.
- if (RegisterSetStateIsValid(set))
- {
- switch (set)
- {
- case e_regSetALL: return SetGPRState() | SetFPUState() | SetEXCState();
- case e_regSetGPR: return SetGPRState();
- case e_regSetFPU: return SetFPUState();
- case e_regSetEXC: return SetEXCState();
- default: break;
- }
+kern_return_t DNBArchImplI386::GetRegisterState(int set, bool force) {
+ switch (set) {
+ case e_regSetALL:
+ return GetGPRState(force) | GetFPUState(force) | GetEXCState(force);
+ case e_regSetGPR:
+ return GetGPRState(force);
+ case e_regSetFPU:
+ return GetFPUState(force);
+ case e_regSetEXC:
+ return GetEXCState(force);
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
+}
+
+kern_return_t DNBArchImplI386::SetRegisterState(int set) {
+ // Make sure we have a valid context to set.
+ if (RegisterSetStateIsValid(set)) {
+ switch (set) {
+ case e_regSetALL:
+ return SetGPRState() | SetFPUState() | SetEXCState();
+ case e_regSetGPR:
+ return SetGPRState();
+ case e_regSetFPU:
+ return SetFPUState();
+ case e_regSetEXC:
+ return SetEXCState();
+ default:
+ break;
}
- return KERN_INVALID_ARGUMENT;
+ }
+ return KERN_INVALID_ARGUMENT;
}
-bool
-DNBArchImplI386::RegisterSetStateIsValid (int set) const
-{
- return m_state.RegsAreValid(set);
+bool DNBArchImplI386::RegisterSetStateIsValid(int set) const {
+ return m_state.RegsAreValid(set);
}
-#endif // #if defined (__i386__)
+#endif // #if defined (__i386__)
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h Tue Sep 6 15:57:50 2016
@@ -14,242 +14,219 @@
#ifndef __DNBArchImplI386_h__
#define __DNBArchImplI386_h__
-#if defined (__i386__) || defined (__x86_64__)
+#if defined(__i386__) || defined(__x86_64__)
-#include "DNBArch.h"
#include "../HasAVX.h"
+#include "DNBArch.h"
#include "MachRegisterStatesI386.h"
#include <map>
class MachThread;
-class DNBArchImplI386 : public DNBArchProtocol
-{
+class DNBArchImplI386 : public DNBArchProtocol {
public:
- DNBArchImplI386(MachThread *thread) :
- DNBArchProtocol(),
- m_thread(thread),
- m_state(),
- m_2pc_dbg_checkpoint(),
- m_2pc_trans_state(Trans_Done),
- m_saved_register_states()
- {
- }
- virtual ~DNBArchImplI386()
- {
- }
-
- static void Initialize();
-
- virtual bool GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value);
- virtual bool SetRegisterValue(uint32_t set, uint32_t reg, const DNBRegisterValue *value);
- virtual nub_size_t GetRegisterContext (void *buf, nub_size_t buf_len);
- virtual nub_size_t SetRegisterContext (const void *buf, nub_size_t buf_len);
- virtual uint32_t SaveRegisterState ();
- virtual bool RestoreRegisterState (uint32_t save_id);
-
- virtual kern_return_t GetRegisterState (int set, bool force);
- virtual kern_return_t SetRegisterState (int set);
- virtual bool RegisterSetStateIsValid (int set) const;
-
- virtual uint64_t GetPC(uint64_t failValue); // Get program counter
- virtual kern_return_t SetPC(uint64_t value);
- virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
- virtual void ThreadWillResume();
- virtual bool ThreadDidStop();
- virtual bool NotifyException(MachException::Data& exc);
-
- virtual uint32_t NumSupportedHardwareWatchpoints();
- virtual uint32_t EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task);
- virtual bool DisableHardwareWatchpoint (uint32_t hw_break_index, bool also_set_on_task);
- virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
+ DNBArchImplI386(MachThread *thread)
+ : DNBArchProtocol(), m_thread(thread), m_state(), m_2pc_dbg_checkpoint(),
+ m_2pc_trans_state(Trans_Done), m_saved_register_states() {}
+ virtual ~DNBArchImplI386() {}
+
+ static void Initialize();
+
+ virtual bool GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value);
+ virtual bool SetRegisterValue(uint32_t set, uint32_t reg,
+ const DNBRegisterValue *value);
+ virtual nub_size_t GetRegisterContext(void *buf, nub_size_t buf_len);
+ virtual nub_size_t SetRegisterContext(const void *buf, nub_size_t buf_len);
+ virtual uint32_t SaveRegisterState();
+ virtual bool RestoreRegisterState(uint32_t save_id);
+
+ virtual kern_return_t GetRegisterState(int set, bool force);
+ virtual kern_return_t SetRegisterState(int set);
+ virtual bool RegisterSetStateIsValid(int set) const;
+
+ virtual uint64_t GetPC(uint64_t failValue); // Get program counter
+ virtual kern_return_t SetPC(uint64_t value);
+ virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
+ virtual void ThreadWillResume();
+ virtual bool ThreadDidStop();
+ virtual bool NotifyException(MachException::Data &exc);
+
+ virtual uint32_t NumSupportedHardwareWatchpoints();
+ virtual uint32_t EnableHardwareWatchpoint(nub_addr_t addr, nub_size_t size,
+ bool read, bool write,
+ bool also_set_on_task);
+ virtual bool DisableHardwareWatchpoint(uint32_t hw_break_index,
+ bool also_set_on_task);
+ virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
protected:
- kern_return_t EnableHardwareSingleStep (bool enable);
+ kern_return_t EnableHardwareSingleStep(bool enable);
- typedef __i386_thread_state_t GPR;
- typedef __i386_float_state_t FPU;
- typedef __i386_exception_state_t EXC;
- typedef __i386_avx_state_t AVX;
- typedef __i386_debug_state_t DBG;
-
- static const DNBRegisterInfo g_gpr_registers[];
- static const DNBRegisterInfo g_fpu_registers_no_avx[];
- static const DNBRegisterInfo g_fpu_registers_avx[];
- static const DNBRegisterInfo g_exc_registers[];
- static const DNBRegisterSetInfo g_reg_sets_no_avx[];
- static const DNBRegisterSetInfo g_reg_sets_avx[];
- static const size_t k_num_gpr_registers;
- static const size_t k_num_fpu_registers_no_avx;
- static const size_t k_num_fpu_registers_avx;
- static const size_t k_num_exc_registers;
- static const size_t k_num_all_registers_no_avx;
- static const size_t k_num_all_registers_avx;
- static const size_t k_num_register_sets;
-
- typedef enum RegisterSetTag
- {
- e_regSetALL = REGISTER_SET_ALL,
- e_regSetGPR,
- e_regSetFPU,
- e_regSetEXC,
- e_regSetDBG,
- kNumRegisterSets
- } RegisterSet;
-
- typedef enum RegisterSetWordSizeTag
- {
- e_regSetWordSizeGPR = sizeof(GPR) / sizeof(int),
- e_regSetWordSizeFPU = sizeof(FPU) / sizeof(int),
- e_regSetWordSizeEXC = sizeof(EXC) / sizeof(int),
- e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
- e_regSetWordSizeDBG = sizeof(DBG) / sizeof(int)
- } RegisterSetWordSize;
-
- enum
- {
- Read = 0,
- Write = 1,
- kNumErrors = 2
- };
-
- struct Context
- {
- GPR gpr;
- union {
- FPU no_avx;
- AVX avx;
- } fpu;
- EXC exc;
- DBG dbg;
- };
-
- struct State
- {
- Context context;
- kern_return_t gpr_errs[2]; // Read/Write errors
- kern_return_t fpu_errs[2]; // Read/Write errors
- kern_return_t exc_errs[2]; // Read/Write errors
- kern_return_t dbg_errs[2]; // Read/Write errors
-
- State()
- {
- uint32_t i;
- for (i=0; i<kNumErrors; i++)
- {
- gpr_errs[i] = -1;
- fpu_errs[i] = -1;
- exc_errs[i] = -1;
- dbg_errs[i] = -1;
- }
- }
- void InvalidateAllRegisterStates()
- {
- SetError (e_regSetALL, Read, -1);
- }
- kern_return_t GetError (int flavor, uint32_t err_idx) const
- {
- if (err_idx < kNumErrors)
- {
- switch (flavor)
- {
- // When getting all errors, just OR all values together to see if
- // we got any kind of error.
- case e_regSetALL: return gpr_errs[err_idx] |
- fpu_errs[err_idx] |
- exc_errs[err_idx];
- case e_regSetGPR: return gpr_errs[err_idx];
- case e_regSetFPU: return fpu_errs[err_idx];
- case e_regSetEXC: return exc_errs[err_idx];
- case e_regSetDBG: return dbg_errs[err_idx];
- default: break;
- }
- }
- return -1;
- }
- bool SetError (int flavor, uint32_t err_idx, kern_return_t err)
- {
- if (err_idx < kNumErrors)
- {
- switch (flavor)
- {
- case e_regSetALL:
- gpr_errs[err_idx] =
- fpu_errs[err_idx] =
- exc_errs[err_idx] =
- dbg_errs[err_idx] = err;
- return true;
-
- case e_regSetGPR:
- gpr_errs[err_idx] = err;
- return true;
-
- case e_regSetFPU:
- fpu_errs[err_idx] = err;
- return true;
-
- case e_regSetEXC:
- exc_errs[err_idx] = err;
- return true;
-
- case e_regSetDBG:
- dbg_errs[err_idx] = err;
- return true;
-
- default: break;
- }
- }
- return false;
+ typedef __i386_thread_state_t GPR;
+ typedef __i386_float_state_t FPU;
+ typedef __i386_exception_state_t EXC;
+ typedef __i386_avx_state_t AVX;
+ typedef __i386_debug_state_t DBG;
+
+ static const DNBRegisterInfo g_gpr_registers[];
+ static const DNBRegisterInfo g_fpu_registers_no_avx[];
+ static const DNBRegisterInfo g_fpu_registers_avx[];
+ static const DNBRegisterInfo g_exc_registers[];
+ static const DNBRegisterSetInfo g_reg_sets_no_avx[];
+ static const DNBRegisterSetInfo g_reg_sets_avx[];
+ static const size_t k_num_gpr_registers;
+ static const size_t k_num_fpu_registers_no_avx;
+ static const size_t k_num_fpu_registers_avx;
+ static const size_t k_num_exc_registers;
+ static const size_t k_num_all_registers_no_avx;
+ static const size_t k_num_all_registers_avx;
+ static const size_t k_num_register_sets;
+
+ typedef enum RegisterSetTag {
+ e_regSetALL = REGISTER_SET_ALL,
+ e_regSetGPR,
+ e_regSetFPU,
+ e_regSetEXC,
+ e_regSetDBG,
+ kNumRegisterSets
+ } RegisterSet;
+
+ typedef enum RegisterSetWordSizeTag {
+ e_regSetWordSizeGPR = sizeof(GPR) / sizeof(int),
+ e_regSetWordSizeFPU = sizeof(FPU) / sizeof(int),
+ e_regSetWordSizeEXC = sizeof(EXC) / sizeof(int),
+ e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
+ e_regSetWordSizeDBG = sizeof(DBG) / sizeof(int)
+ } RegisterSetWordSize;
+
+ enum { Read = 0, Write = 1, kNumErrors = 2 };
+
+ struct Context {
+ GPR gpr;
+ union {
+ FPU no_avx;
+ AVX avx;
+ } fpu;
+ EXC exc;
+ DBG dbg;
+ };
+
+ struct State {
+ Context context;
+ kern_return_t gpr_errs[2]; // Read/Write errors
+ kern_return_t fpu_errs[2]; // Read/Write errors
+ kern_return_t exc_errs[2]; // Read/Write errors
+ kern_return_t dbg_errs[2]; // Read/Write errors
+
+ State() {
+ uint32_t i;
+ for (i = 0; i < kNumErrors; i++) {
+ gpr_errs[i] = -1;
+ fpu_errs[i] = -1;
+ exc_errs[i] = -1;
+ dbg_errs[i] = -1;
+ }
+ }
+ void InvalidateAllRegisterStates() { SetError(e_regSetALL, Read, -1); }
+ kern_return_t GetError(int flavor, uint32_t err_idx) const {
+ if (err_idx < kNumErrors) {
+ switch (flavor) {
+ // When getting all errors, just OR all values together to see if
+ // we got any kind of error.
+ case e_regSetALL:
+ return gpr_errs[err_idx] | fpu_errs[err_idx] | exc_errs[err_idx];
+ case e_regSetGPR:
+ return gpr_errs[err_idx];
+ case e_regSetFPU:
+ return fpu_errs[err_idx];
+ case e_regSetEXC:
+ return exc_errs[err_idx];
+ case e_regSetDBG:
+ return dbg_errs[err_idx];
+ default:
+ break;
}
- bool RegsAreValid (int flavor) const
- {
- return GetError(flavor, Read) == KERN_SUCCESS;
+ }
+ return -1;
+ }
+ bool SetError(int flavor, uint32_t err_idx, kern_return_t err) {
+ if (err_idx < kNumErrors) {
+ switch (flavor) {
+ case e_regSetALL:
+ gpr_errs[err_idx] = fpu_errs[err_idx] = exc_errs[err_idx] =
+ dbg_errs[err_idx] = err;
+ return true;
+
+ case e_regSetGPR:
+ gpr_errs[err_idx] = err;
+ return true;
+
+ case e_regSetFPU:
+ fpu_errs[err_idx] = err;
+ return true;
+
+ case e_regSetEXC:
+ exc_errs[err_idx] = err;
+ return true;
+
+ case e_regSetDBG:
+ dbg_errs[err_idx] = err;
+ return true;
+
+ default:
+ break;
}
- };
+ }
+ return false;
+ }
+ bool RegsAreValid(int flavor) const {
+ return GetError(flavor, Read) == KERN_SUCCESS;
+ }
+ };
- kern_return_t GetGPRState (bool force);
- kern_return_t GetFPUState (bool force);
- kern_return_t GetEXCState (bool force);
- kern_return_t GetDBGState (bool force);
-
- kern_return_t SetGPRState ();
- kern_return_t SetFPUState ();
- kern_return_t SetEXCState ();
- kern_return_t SetDBGState (bool also_set_on_task);
-
- static DNBArchProtocol *
- Create (MachThread *thread);
-
- static const uint8_t *
- SoftwareBreakpointOpcode (nub_size_t byte_size);
-
- static const DNBRegisterSetInfo *
- GetRegisterSetInfo(nub_size_t *num_reg_sets);
-
- static uint32_t
- GetRegisterContextSize();
-
- // Helper functions for watchpoint manipulations.
- static void SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write);
- static void ClearWatchpoint(DBG &debug_state, uint32_t hw_index);
- static bool IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index);
- static void ClearWatchpointHits(DBG &debug_state);
- static bool IsWatchpointHit(const DBG &debug_state, uint32_t hw_index);
- static nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
-
- virtual bool StartTransForHWP();
- virtual bool RollbackTransForHWP();
- virtual bool FinishTransForHWP();
- DBG GetDBGCheckpoint();
-
- MachThread *m_thread;
- State m_state;
- DBG m_2pc_dbg_checkpoint;
- uint32_t m_2pc_trans_state; // Is transaction of DBG state change: Pedning (0), Done (1), or Rolled Back (2)?
- typedef std::map<uint32_t, Context> SaveRegisterStates;
- SaveRegisterStates m_saved_register_states;
+ kern_return_t GetGPRState(bool force);
+ kern_return_t GetFPUState(bool force);
+ kern_return_t GetEXCState(bool force);
+ kern_return_t GetDBGState(bool force);
+
+ kern_return_t SetGPRState();
+ kern_return_t SetFPUState();
+ kern_return_t SetEXCState();
+ kern_return_t SetDBGState(bool also_set_on_task);
+
+ static DNBArchProtocol *Create(MachThread *thread);
+
+ static const uint8_t *SoftwareBreakpointOpcode(nub_size_t byte_size);
+
+ static const DNBRegisterSetInfo *GetRegisterSetInfo(nub_size_t *num_reg_sets);
+
+ static uint32_t GetRegisterContextSize();
+
+ // Helper functions for watchpoint manipulations.
+ static void SetWatchpoint(DBG &debug_state, uint32_t hw_index,
+ nub_addr_t addr, nub_size_t size, bool read,
+ bool write);
+ static void ClearWatchpoint(DBG &debug_state, uint32_t hw_index);
+ static bool IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index);
+ static void ClearWatchpointHits(DBG &debug_state);
+ static bool IsWatchpointHit(const DBG &debug_state, uint32_t hw_index);
+ static nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
+
+ virtual bool StartTransForHWP();
+ virtual bool RollbackTransForHWP();
+ virtual bool FinishTransForHWP();
+ DBG GetDBGCheckpoint();
+
+ MachThread *m_thread;
+ State m_state;
+ DBG m_2pc_dbg_checkpoint;
+ uint32_t m_2pc_trans_state; // Is transaction of DBG state change: Pedning
+ // (0), Done (1), or Rolled Back (2)?
+ typedef std::map<uint32_t, Context> SaveRegisterStates;
+ SaveRegisterStates m_saved_register_states;
};
-#endif // #if defined (__i386__) || defined (__x86_64__)
-#endif // #ifndef __DNBArchImplI386_h__
+#endif // #if defined (__i386__) || defined (__x86_64__)
+#endif // #ifndef __DNBArchImplI386_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h Tue Sep 6 15:57:50 2016
@@ -16,165 +16,163 @@
#include <inttypes.h>
-#define __i386_THREAD_STATE 1
-#define __i386_FLOAT_STATE 2
-#define __i386_EXCEPTION_STATE 3
-#define __i386_DEBUG_STATE 10
-#define __i386_AVX_STATE 16
-
-typedef struct {
- uint32_t __eax;
- uint32_t __ebx;
- uint32_t __ecx;
- uint32_t __edx;
- uint32_t __edi;
- uint32_t __esi;
- uint32_t __ebp;
- uint32_t __esp;
- uint32_t __ss;
- uint32_t __eflags;
- uint32_t __eip;
- uint32_t __cs;
- uint32_t __ds;
- uint32_t __es;
- uint32_t __fs;
- uint32_t __gs;
+#define __i386_THREAD_STATE 1
+#define __i386_FLOAT_STATE 2
+#define __i386_EXCEPTION_STATE 3
+#define __i386_DEBUG_STATE 10
+#define __i386_AVX_STATE 16
+
+typedef struct {
+ uint32_t __eax;
+ uint32_t __ebx;
+ uint32_t __ecx;
+ uint32_t __edx;
+ uint32_t __edi;
+ uint32_t __esi;
+ uint32_t __ebp;
+ uint32_t __esp;
+ uint32_t __ss;
+ uint32_t __eflags;
+ uint32_t __eip;
+ uint32_t __cs;
+ uint32_t __ds;
+ uint32_t __es;
+ uint32_t __fs;
+ uint32_t __gs;
} __i386_thread_state_t;
typedef struct {
- uint16_t __invalid : 1;
- uint16_t __denorm : 1;
- uint16_t __zdiv : 1;
- uint16_t __ovrfl : 1;
- uint16_t __undfl : 1;
- uint16_t __precis : 1;
- uint16_t __PAD1 : 2;
- uint16_t __pc : 2;
- uint16_t __rc : 2;
- uint16_t __PAD2 : 1;
- uint16_t __PAD3 : 3;
+ uint16_t __invalid : 1;
+ uint16_t __denorm : 1;
+ uint16_t __zdiv : 1;
+ uint16_t __ovrfl : 1;
+ uint16_t __undfl : 1;
+ uint16_t __precis : 1;
+ uint16_t __PAD1 : 2;
+ uint16_t __pc : 2;
+ uint16_t __rc : 2;
+ uint16_t __PAD2 : 1;
+ uint16_t __PAD3 : 3;
} __i386_fp_control_t;
typedef struct {
- uint16_t __invalid : 1;
- uint16_t __denorm : 1;
- uint16_t __zdiv : 1;
- uint16_t __ovrfl : 1;
- uint16_t __undfl : 1;
- uint16_t __precis : 1;
- uint16_t __stkflt : 1;
- uint16_t __errsumm : 1;
- uint16_t __c0 : 1;
- uint16_t __c1 : 1;
- uint16_t __c2 : 1;
- uint16_t __tos : 3;
- uint16_t __c3 : 1;
- uint16_t __busy : 1;
+ uint16_t __invalid : 1;
+ uint16_t __denorm : 1;
+ uint16_t __zdiv : 1;
+ uint16_t __ovrfl : 1;
+ uint16_t __undfl : 1;
+ uint16_t __precis : 1;
+ uint16_t __stkflt : 1;
+ uint16_t __errsumm : 1;
+ uint16_t __c0 : 1;
+ uint16_t __c1 : 1;
+ uint16_t __c2 : 1;
+ uint16_t __tos : 3;
+ uint16_t __c3 : 1;
+ uint16_t __busy : 1;
} __i386_fp_status_t;
typedef struct {
- uint8_t __mmst_reg[10];
- uint8_t __mmst_rsrv[6];
+ uint8_t __mmst_reg[10];
+ uint8_t __mmst_rsrv[6];
} __i386_mmst_reg;
-typedef struct {
- uint8_t __xmm_reg[16];
-} __i386_xmm_reg;
+typedef struct { uint8_t __xmm_reg[16]; } __i386_xmm_reg;
typedef struct {
- uint32_t __fpu_reserved[2];
- __i386_fp_control_t __fpu_fcw;
- __i386_fp_status_t __fpu_fsw;
- uint8_t __fpu_ftw;
- uint8_t __fpu_rsrv1;
- uint16_t __fpu_fop;
- uint32_t __fpu_ip;
- uint16_t __fpu_cs;
- uint16_t __fpu_rsrv2;
- uint32_t __fpu_dp;
- uint16_t __fpu_ds;
- uint16_t __fpu_rsrv3;
- uint32_t __fpu_mxcsr;
- uint32_t __fpu_mxcsrmask;
- __i386_mmst_reg __fpu_stmm0;
- __i386_mmst_reg __fpu_stmm1;
- __i386_mmst_reg __fpu_stmm2;
- __i386_mmst_reg __fpu_stmm3;
- __i386_mmst_reg __fpu_stmm4;
- __i386_mmst_reg __fpu_stmm5;
- __i386_mmst_reg __fpu_stmm6;
- __i386_mmst_reg __fpu_stmm7;
- __i386_xmm_reg __fpu_xmm0;
- __i386_xmm_reg __fpu_xmm1;
- __i386_xmm_reg __fpu_xmm2;
- __i386_xmm_reg __fpu_xmm3;
- __i386_xmm_reg __fpu_xmm4;
- __i386_xmm_reg __fpu_xmm5;
- __i386_xmm_reg __fpu_xmm6;
- __i386_xmm_reg __fpu_xmm7;
- uint8_t __fpu_rsrv4[14*16];
- uint32_t __fpu_reserved1;
+ uint32_t __fpu_reserved[2];
+ __i386_fp_control_t __fpu_fcw;
+ __i386_fp_status_t __fpu_fsw;
+ uint8_t __fpu_ftw;
+ uint8_t __fpu_rsrv1;
+ uint16_t __fpu_fop;
+ uint32_t __fpu_ip;
+ uint16_t __fpu_cs;
+ uint16_t __fpu_rsrv2;
+ uint32_t __fpu_dp;
+ uint16_t __fpu_ds;
+ uint16_t __fpu_rsrv3;
+ uint32_t __fpu_mxcsr;
+ uint32_t __fpu_mxcsrmask;
+ __i386_mmst_reg __fpu_stmm0;
+ __i386_mmst_reg __fpu_stmm1;
+ __i386_mmst_reg __fpu_stmm2;
+ __i386_mmst_reg __fpu_stmm3;
+ __i386_mmst_reg __fpu_stmm4;
+ __i386_mmst_reg __fpu_stmm5;
+ __i386_mmst_reg __fpu_stmm6;
+ __i386_mmst_reg __fpu_stmm7;
+ __i386_xmm_reg __fpu_xmm0;
+ __i386_xmm_reg __fpu_xmm1;
+ __i386_xmm_reg __fpu_xmm2;
+ __i386_xmm_reg __fpu_xmm3;
+ __i386_xmm_reg __fpu_xmm4;
+ __i386_xmm_reg __fpu_xmm5;
+ __i386_xmm_reg __fpu_xmm6;
+ __i386_xmm_reg __fpu_xmm7;
+ uint8_t __fpu_rsrv4[14 * 16];
+ uint32_t __fpu_reserved1;
} __i386_float_state_t;
typedef struct {
- uint32_t __fpu_reserved[2];
- __i386_fp_control_t __fpu_fcw;
- __i386_fp_status_t __fpu_fsw;
- uint8_t __fpu_ftw;
- uint8_t __fpu_rsrv1;
- uint16_t __fpu_fop;
- uint32_t __fpu_ip;
- uint16_t __fpu_cs;
- uint16_t __fpu_rsrv2;
- uint32_t __fpu_dp;
- uint16_t __fpu_ds;
- uint16_t __fpu_rsrv3;
- uint32_t __fpu_mxcsr;
- uint32_t __fpu_mxcsrmask;
- __i386_mmst_reg __fpu_stmm0;
- __i386_mmst_reg __fpu_stmm1;
- __i386_mmst_reg __fpu_stmm2;
- __i386_mmst_reg __fpu_stmm3;
- __i386_mmst_reg __fpu_stmm4;
- __i386_mmst_reg __fpu_stmm5;
- __i386_mmst_reg __fpu_stmm6;
- __i386_mmst_reg __fpu_stmm7;
- __i386_xmm_reg __fpu_xmm0;
- __i386_xmm_reg __fpu_xmm1;
- __i386_xmm_reg __fpu_xmm2;
- __i386_xmm_reg __fpu_xmm3;
- __i386_xmm_reg __fpu_xmm4;
- __i386_xmm_reg __fpu_xmm5;
- __i386_xmm_reg __fpu_xmm6;
- __i386_xmm_reg __fpu_xmm7;
- uint8_t __fpu_rsrv4[14*16];
- uint32_t __fpu_reserved1;
- uint8_t __avx_reserved1[64];
- __i386_xmm_reg __fpu_ymmh0;
- __i386_xmm_reg __fpu_ymmh1;
- __i386_xmm_reg __fpu_ymmh2;
- __i386_xmm_reg __fpu_ymmh3;
- __i386_xmm_reg __fpu_ymmh4;
- __i386_xmm_reg __fpu_ymmh5;
- __i386_xmm_reg __fpu_ymmh6;
- __i386_xmm_reg __fpu_ymmh7;
+ uint32_t __fpu_reserved[2];
+ __i386_fp_control_t __fpu_fcw;
+ __i386_fp_status_t __fpu_fsw;
+ uint8_t __fpu_ftw;
+ uint8_t __fpu_rsrv1;
+ uint16_t __fpu_fop;
+ uint32_t __fpu_ip;
+ uint16_t __fpu_cs;
+ uint16_t __fpu_rsrv2;
+ uint32_t __fpu_dp;
+ uint16_t __fpu_ds;
+ uint16_t __fpu_rsrv3;
+ uint32_t __fpu_mxcsr;
+ uint32_t __fpu_mxcsrmask;
+ __i386_mmst_reg __fpu_stmm0;
+ __i386_mmst_reg __fpu_stmm1;
+ __i386_mmst_reg __fpu_stmm2;
+ __i386_mmst_reg __fpu_stmm3;
+ __i386_mmst_reg __fpu_stmm4;
+ __i386_mmst_reg __fpu_stmm5;
+ __i386_mmst_reg __fpu_stmm6;
+ __i386_mmst_reg __fpu_stmm7;
+ __i386_xmm_reg __fpu_xmm0;
+ __i386_xmm_reg __fpu_xmm1;
+ __i386_xmm_reg __fpu_xmm2;
+ __i386_xmm_reg __fpu_xmm3;
+ __i386_xmm_reg __fpu_xmm4;
+ __i386_xmm_reg __fpu_xmm5;
+ __i386_xmm_reg __fpu_xmm6;
+ __i386_xmm_reg __fpu_xmm7;
+ uint8_t __fpu_rsrv4[14 * 16];
+ uint32_t __fpu_reserved1;
+ uint8_t __avx_reserved1[64];
+ __i386_xmm_reg __fpu_ymmh0;
+ __i386_xmm_reg __fpu_ymmh1;
+ __i386_xmm_reg __fpu_ymmh2;
+ __i386_xmm_reg __fpu_ymmh3;
+ __i386_xmm_reg __fpu_ymmh4;
+ __i386_xmm_reg __fpu_ymmh5;
+ __i386_xmm_reg __fpu_ymmh6;
+ __i386_xmm_reg __fpu_ymmh7;
} __i386_avx_state_t;
typedef struct {
- uint32_t __trapno;
- uint32_t __err;
- uint32_t __faultvaddr;
+ uint32_t __trapno;
+ uint32_t __err;
+ uint32_t __faultvaddr;
} __i386_exception_state_t;
typedef struct {
- uint32_t __dr0;
- uint32_t __dr1;
- uint32_t __dr2;
- uint32_t __dr3;
- uint32_t __dr4;
- uint32_t __dr5;
- uint32_t __dr6;
- uint32_t __dr7;
+ uint32_t __dr0;
+ uint32_t __dr1;
+ uint32_t __dr2;
+ uint32_t __dr3;
+ uint32_t __dr4;
+ uint32_t __dr5;
+ uint32_t __dr6;
+ uint32_t __dr7;
} __i386_debug_state_t;
#endif
Modified: lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.cpp?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.cpp Tue Sep 6 15:57:50 2016
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
+#if defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)
#if __DARWIN_UNIX03
#define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) __##reg
@@ -20,550 +20,473 @@
#endif
#include "MacOSX/ppc/DNBArchImpl.h"
-#include "MacOSX/MachThread.h"
#include "DNBBreakpoint.h"
#include "DNBLog.h"
#include "DNBRegisterInfo.h"
+#include "MacOSX/MachThread.h"
-static const uint8_t g_breakpoint_opcode[] = { 0x7F, 0xC0, 0x00, 0x08 };
-
-const uint8_t *
-DNBArchMachPPC::SoftwareBreakpointOpcode (nub_size_t size)
-{
- if (size == 4)
- return g_breakpoint_opcode;
- return NULL;
-}
-
-uint32_t
-DNBArchMachPPC::GetCPUType()
-{
- return CPU_TYPE_POWERPC;
-}
-
-uint64_t
-DNBArchMachPPC::GetPC(uint64_t failValue)
-{
- // Get program counter
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0);
- return failValue;
-}
-
-kern_return_t
-DNBArchMachPPC::SetPC(uint64_t value)
-{
- // Get program counter
- kern_return_t err = GetGPRState(false);
- if (err == KERN_SUCCESS)
- {
- m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0) = value;
- err = SetGPRState();
- }
- return err == KERN_SUCCESS;
-}
-
-uint64_t
-DNBArchMachPPC::GetSP(uint64_t failValue)
-{
- // Get stack pointer
- if (GetGPRState(false) == KERN_SUCCESS)
- return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(r1);
- return failValue;
-}
-
-kern_return_t
-DNBArchMachPPC::GetGPRState(bool force)
-{
- if (force || m_state.GetError(e_regSetGPR, Read))
- {
- mach_msg_type_number_t count = e_regSetWordSizeGPR;
- m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetGPR, (thread_state_t)&m_state.gpr, &count));
- }
- return m_state.GetError(e_regSetGPR, Read);
-}
-
-kern_return_t
-DNBArchMachPPC::GetFPRState(bool force)
-{
- if (force || m_state.GetError(e_regSetFPR, Read))
- {
- mach_msg_type_number_t count = e_regSetWordSizeFPR;
- m_state.SetError(e_regSetFPR, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetFPR, (thread_state_t)&m_state.fpr, &count));
- }
- return m_state.GetError(e_regSetFPR, Read);
-}
-
-kern_return_t
-DNBArchMachPPC::GetEXCState(bool force)
-{
- if (force || m_state.GetError(e_regSetEXC, Read))
- {
- mach_msg_type_number_t count = e_regSetWordSizeEXC;
- m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetEXC, (thread_state_t)&m_state.exc, &count));
- }
- return m_state.GetError(e_regSetEXC, Read);
-}
-
-kern_return_t
-DNBArchMachPPC::GetVECState(bool force)
-{
- if (force || m_state.GetError(e_regSetVEC, Read))
- {
- mach_msg_type_number_t count = e_regSetWordSizeVEC;
- m_state.SetError(e_regSetVEC, Read, ::thread_get_state(m_thread->MachPortNumber(), e_regSetVEC, (thread_state_t)&m_state.vec, &count));
- }
- return m_state.GetError(e_regSetVEC, Read);
-}
-
-kern_return_t
-DNBArchMachPPC::SetGPRState()
-{
- m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetGPR, (thread_state_t)&m_state.gpr, e_regSetWordSizeGPR));
- return m_state.GetError(e_regSetGPR, Write);
-}
-
-kern_return_t
-DNBArchMachPPC::SetFPRState()
-{
- m_state.SetError(e_regSetFPR, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetFPR, (thread_state_t)&m_state.fpr, e_regSetWordSizeFPR));
- return m_state.GetError(e_regSetFPR, Write);
-}
-
-kern_return_t
-DNBArchMachPPC::SetEXCState()
-{
- m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetEXC, (thread_state_t)&m_state.exc, e_regSetWordSizeEXC));
- return m_state.GetError(e_regSetEXC, Write);
-}
-
-kern_return_t
-DNBArchMachPPC::SetVECState()
-{
- m_state.SetError(e_regSetVEC, Write, ::thread_set_state(m_thread->MachPortNumber(), e_regSetVEC, (thread_state_t)&m_state.vec, e_regSetWordSizeVEC));
- return m_state.GetError(e_regSetVEC, Write);
-}
-
-bool
-DNBArchMachPPC::ThreadWillResume()
-{
- bool success = true;
-
- // Do we need to step this thread? If so, let the mach thread tell us so.
- if (m_thread->IsStepping())
- {
- // This is the primary thread, let the arch do anything it needs
- success = EnableHardwareSingleStep(true) == KERN_SUCCESS;
- }
- return success;
-}
-
-bool
-DNBArchMachPPC::ThreadDidStop()
-{
- bool success = true;
-
- m_state.InvalidateAllRegisterStates();
+static const uint8_t g_breakpoint_opcode[] = {0x7F, 0xC0, 0x00, 0x08};
- // Are we stepping a single instruction?
- if (GetGPRState(true) == KERN_SUCCESS)
- {
- // We are single stepping, was this the primary thread?
- if (m_thread->IsStepping())
- {
- // This was the primary thread, we need to clear the trace
- // bit if so.
- success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
- }
- else
- {
- // The MachThread will automatically restore the suspend count
- // in ThreadDidStop(), so we don't need to do anything here if
- // we weren't the primary thread the last time
- }
+const uint8_t *DNBArchMachPPC::SoftwareBreakpointOpcode(nub_size_t size) {
+ if (size == 4)
+ return g_breakpoint_opcode;
+ return NULL;
+}
+
+uint32_t DNBArchMachPPC::GetCPUType() { return CPU_TYPE_POWERPC; }
+
+uint64_t DNBArchMachPPC::GetPC(uint64_t failValue) {
+ // Get program counter
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0);
+ return failValue;
+}
+
+kern_return_t DNBArchMachPPC::SetPC(uint64_t value) {
+ // Get program counter
+ kern_return_t err = GetGPRState(false);
+ if (err == KERN_SUCCESS) {
+ m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0) = value;
+ err = SetGPRState();
+ }
+ return err == KERN_SUCCESS;
+}
+
+uint64_t DNBArchMachPPC::GetSP(uint64_t failValue) {
+ // Get stack pointer
+ if (GetGPRState(false) == KERN_SUCCESS)
+ return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(r1);
+ return failValue;
+}
+
+kern_return_t DNBArchMachPPC::GetGPRState(bool force) {
+ if (force || m_state.GetError(e_regSetGPR, Read)) {
+ mach_msg_type_number_t count = e_regSetWordSizeGPR;
+ m_state.SetError(e_regSetGPR, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), e_regSetGPR,
+ (thread_state_t)&m_state.gpr, &count));
+ }
+ return m_state.GetError(e_regSetGPR, Read);
+}
+
+kern_return_t DNBArchMachPPC::GetFPRState(bool force) {
+ if (force || m_state.GetError(e_regSetFPR, Read)) {
+ mach_msg_type_number_t count = e_regSetWordSizeFPR;
+ m_state.SetError(e_regSetFPR, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), e_regSetFPR,
+ (thread_state_t)&m_state.fpr, &count));
+ }
+ return m_state.GetError(e_regSetFPR, Read);
+}
+
+kern_return_t DNBArchMachPPC::GetEXCState(bool force) {
+ if (force || m_state.GetError(e_regSetEXC, Read)) {
+ mach_msg_type_number_t count = e_regSetWordSizeEXC;
+ m_state.SetError(e_regSetEXC, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), e_regSetEXC,
+ (thread_state_t)&m_state.exc, &count));
+ }
+ return m_state.GetError(e_regSetEXC, Read);
+}
+
+kern_return_t DNBArchMachPPC::GetVECState(bool force) {
+ if (force || m_state.GetError(e_regSetVEC, Read)) {
+ mach_msg_type_number_t count = e_regSetWordSizeVEC;
+ m_state.SetError(e_regSetVEC, Read,
+ ::thread_get_state(m_thread->MachPortNumber(), e_regSetVEC,
+ (thread_state_t)&m_state.vec, &count));
+ }
+ return m_state.GetError(e_regSetVEC, Read);
+}
+
+kern_return_t DNBArchMachPPC::SetGPRState() {
+ m_state.SetError(e_regSetGPR, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), e_regSetGPR,
+ (thread_state_t)&m_state.gpr,
+ e_regSetWordSizeGPR));
+ return m_state.GetError(e_regSetGPR, Write);
+}
+
+kern_return_t DNBArchMachPPC::SetFPRState() {
+ m_state.SetError(e_regSetFPR, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), e_regSetFPR,
+ (thread_state_t)&m_state.fpr,
+ e_regSetWordSizeFPR));
+ return m_state.GetError(e_regSetFPR, Write);
+}
+
+kern_return_t DNBArchMachPPC::SetEXCState() {
+ m_state.SetError(e_regSetEXC, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), e_regSetEXC,
+ (thread_state_t)&m_state.exc,
+ e_regSetWordSizeEXC));
+ return m_state.GetError(e_regSetEXC, Write);
+}
+
+kern_return_t DNBArchMachPPC::SetVECState() {
+ m_state.SetError(e_regSetVEC, Write,
+ ::thread_set_state(m_thread->MachPortNumber(), e_regSetVEC,
+ (thread_state_t)&m_state.vec,
+ e_regSetWordSizeVEC));
+ return m_state.GetError(e_regSetVEC, Write);
+}
+
+bool DNBArchMachPPC::ThreadWillResume() {
+ bool success = true;
+
+ // Do we need to step this thread? If so, let the mach thread tell us so.
+ if (m_thread->IsStepping()) {
+ // This is the primary thread, let the arch do anything it needs
+ success = EnableHardwareSingleStep(true) == KERN_SUCCESS;
+ }
+ return success;
+}
+
+bool DNBArchMachPPC::ThreadDidStop() {
+ bool success = true;
+
+ m_state.InvalidateAllRegisterStates();
+
+ // Are we stepping a single instruction?
+ if (GetGPRState(true) == KERN_SUCCESS) {
+ // We are single stepping, was this the primary thread?
+ if (m_thread->IsStepping()) {
+ // This was the primary thread, we need to clear the trace
+ // bit if so.
+ success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
+ } else {
+ // The MachThread will automatically restore the suspend count
+ // in ThreadDidStop(), so we don't need to do anything here if
+ // we weren't the primary thread the last time
}
- return success;
+ }
+ return success;
}
-
// Set the single step bit in the processor status register.
-kern_return_t
-DNBArchMachPPC::EnableHardwareSingleStep (bool enable)
-{
- DNBLogThreadedIf(LOG_STEP, "DNBArchMachPPC::EnableHardwareSingleStep( enable = %d )", enable);
- if (GetGPRState(false) == KERN_SUCCESS)
- {
- const uint32_t trace_bit = 0x400;
- if (enable)
- m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) |= trace_bit;
- else
- m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) &= ~trace_bit;
- return SetGPRState();
- }
- return m_state.GetError(e_regSetGPR, Read);
+kern_return_t DNBArchMachPPC::EnableHardwareSingleStep(bool enable) {
+ DNBLogThreadedIf(LOG_STEP,
+ "DNBArchMachPPC::EnableHardwareSingleStep( enable = %d )",
+ enable);
+ if (GetGPRState(false) == KERN_SUCCESS) {
+ const uint32_t trace_bit = 0x400;
+ if (enable)
+ m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) |= trace_bit;
+ else
+ m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) &= ~trace_bit;
+ return SetGPRState();
+ }
+ return m_state.GetError(e_regSetGPR, Read);
}
//----------------------------------------------------------------------
// Register information definitions for 32 bit PowerPC.
//----------------------------------------------------------------------
-enum gpr_regnums
-{
- e_regNumGPR_srr0,
- e_regNumGPR_srr1,
- e_regNumGPR_r0,
- e_regNumGPR_r1,
- e_regNumGPR_r2,
- e_regNumGPR_r3,
- e_regNumGPR_r4,
- e_regNumGPR_r5,
- e_regNumGPR_r6,
- e_regNumGPR_r7,
- e_regNumGPR_r8,
- e_regNumGPR_r9,
- e_regNumGPR_r10,
- e_regNumGPR_r11,
- e_regNumGPR_r12,
- e_regNumGPR_r13,
- e_regNumGPR_r14,
- e_regNumGPR_r15,
- e_regNumGPR_r16,
- e_regNumGPR_r17,
- e_regNumGPR_r18,
- e_regNumGPR_r19,
- e_regNumGPR_r20,
- e_regNumGPR_r21,
- e_regNumGPR_r22,
- e_regNumGPR_r23,
- e_regNumGPR_r24,
- e_regNumGPR_r25,
- e_regNumGPR_r26,
- e_regNumGPR_r27,
- e_regNumGPR_r28,
- e_regNumGPR_r29,
- e_regNumGPR_r30,
- e_regNumGPR_r31,
- e_regNumGPR_cr,
- e_regNumGPR_xer,
- e_regNumGPR_lr,
- e_regNumGPR_ctr,
- e_regNumGPR_mq,
- e_regNumGPR_vrsave
+enum gpr_regnums {
+ e_regNumGPR_srr0,
+ e_regNumGPR_srr1,
+ e_regNumGPR_r0,
+ e_regNumGPR_r1,
+ e_regNumGPR_r2,
+ e_regNumGPR_r3,
+ e_regNumGPR_r4,
+ e_regNumGPR_r5,
+ e_regNumGPR_r6,
+ e_regNumGPR_r7,
+ e_regNumGPR_r8,
+ e_regNumGPR_r9,
+ e_regNumGPR_r10,
+ e_regNumGPR_r11,
+ e_regNumGPR_r12,
+ e_regNumGPR_r13,
+ e_regNumGPR_r14,
+ e_regNumGPR_r15,
+ e_regNumGPR_r16,
+ e_regNumGPR_r17,
+ e_regNumGPR_r18,
+ e_regNumGPR_r19,
+ e_regNumGPR_r20,
+ e_regNumGPR_r21,
+ e_regNumGPR_r22,
+ e_regNumGPR_r23,
+ e_regNumGPR_r24,
+ e_regNumGPR_r25,
+ e_regNumGPR_r26,
+ e_regNumGPR_r27,
+ e_regNumGPR_r28,
+ e_regNumGPR_r29,
+ e_regNumGPR_r30,
+ e_regNumGPR_r31,
+ e_regNumGPR_cr,
+ e_regNumGPR_xer,
+ e_regNumGPR_lr,
+ e_regNumGPR_ctr,
+ e_regNumGPR_mq,
+ e_regNumGPR_vrsave
};
-
-
-
// General purpose registers
-static DNBRegisterInfo g_gpr_registers[] =
-{
- { "srr0" , Uint, 4, Hex },
- { "srr1" , Uint, 4, Hex },
- { "r0" , Uint, 4, Hex },
- { "r1" , Uint, 4, Hex },
- { "r2" , Uint, 4, Hex },
- { "r3" , Uint, 4, Hex },
- { "r4" , Uint, 4, Hex },
- { "r5" , Uint, 4, Hex },
- { "r6" , Uint, 4, Hex },
- { "r7" , Uint, 4, Hex },
- { "r8" , Uint, 4, Hex },
- { "r9" , Uint, 4, Hex },
- { "r10" , Uint, 4, Hex },
- { "r11" , Uint, 4, Hex },
- { "r12" , Uint, 4, Hex },
- { "r13" , Uint, 4, Hex },
- { "r14" , Uint, 4, Hex },
- { "r15" , Uint, 4, Hex },
- { "r16" , Uint, 4, Hex },
- { "r17" , Uint, 4, Hex },
- { "r18" , Uint, 4, Hex },
- { "r19" , Uint, 4, Hex },
- { "r20" , Uint, 4, Hex },
- { "r21" , Uint, 4, Hex },
- { "r22" , Uint, 4, Hex },
- { "r23" , Uint, 4, Hex },
- { "r24" , Uint, 4, Hex },
- { "r25" , Uint, 4, Hex },
- { "r26" , Uint, 4, Hex },
- { "r27" , Uint, 4, Hex },
- { "r28" , Uint, 4, Hex },
- { "r29" , Uint, 4, Hex },
- { "r30" , Uint, 4, Hex },
- { "r31" , Uint, 4, Hex },
- { "cr" , Uint, 4, Hex },
- { "xer" , Uint, 4, Hex },
- { "lr" , Uint, 4, Hex },
- { "ctr" , Uint, 4, Hex },
- { "mq" , Uint, 4, Hex },
- { "vrsave", Uint, 4, Hex },
+static DNBRegisterInfo g_gpr_registers[] = {
+ {"srr0", Uint, 4, Hex}, {"srr1", Uint, 4, Hex}, {"r0", Uint, 4, Hex},
+ {"r1", Uint, 4, Hex}, {"r2", Uint, 4, Hex}, {"r3", Uint, 4, Hex},
+ {"r4", Uint, 4, Hex}, {"r5", Uint, 4, Hex}, {"r6", Uint, 4, Hex},
+ {"r7", Uint, 4, Hex}, {"r8", Uint, 4, Hex}, {"r9", Uint, 4, Hex},
+ {"r10", Uint, 4, Hex}, {"r11", Uint, 4, Hex}, {"r12", Uint, 4, Hex},
+ {"r13", Uint, 4, Hex}, {"r14", Uint, 4, Hex}, {"r15", Uint, 4, Hex},
+ {"r16", Uint, 4, Hex}, {"r17", Uint, 4, Hex}, {"r18", Uint, 4, Hex},
+ {"r19", Uint, 4, Hex}, {"r20", Uint, 4, Hex}, {"r21", Uint, 4, Hex},
+ {"r22", Uint, 4, Hex}, {"r23", Uint, 4, Hex}, {"r24", Uint, 4, Hex},
+ {"r25", Uint, 4, Hex}, {"r26", Uint, 4, Hex}, {"r27", Uint, 4, Hex},
+ {"r28", Uint, 4, Hex}, {"r29", Uint, 4, Hex}, {"r30", Uint, 4, Hex},
+ {"r31", Uint, 4, Hex}, {"cr", Uint, 4, Hex}, {"xer", Uint, 4, Hex},
+ {"lr", Uint, 4, Hex}, {"ctr", Uint, 4, Hex}, {"mq", Uint, 4, Hex},
+ {"vrsave", Uint, 4, Hex},
};
// Floating point registers
-static DNBRegisterInfo g_fpr_registers[] =
-{
- { "fp0" , IEEE754, 8, Float },
- { "fp1" , IEEE754, 8, Float },
- { "fp2" , IEEE754, 8, Float },
- { "fp3" , IEEE754, 8, Float },
- { "fp4" , IEEE754, 8, Float },
- { "fp5" , IEEE754, 8, Float },
- { "fp6" , IEEE754, 8, Float },
- { "fp7" , IEEE754, 8, Float },
- { "fp8" , IEEE754, 8, Float },
- { "fp9" , IEEE754, 8, Float },
- { "fp10" , IEEE754, 8, Float },
- { "fp11" , IEEE754, 8, Float },
- { "fp12" , IEEE754, 8, Float },
- { "fp13" , IEEE754, 8, Float },
- { "fp14" , IEEE754, 8, Float },
- { "fp15" , IEEE754, 8, Float },
- { "fp16" , IEEE754, 8, Float },
- { "fp17" , IEEE754, 8, Float },
- { "fp18" , IEEE754, 8, Float },
- { "fp19" , IEEE754, 8, Float },
- { "fp20" , IEEE754, 8, Float },
- { "fp21" , IEEE754, 8, Float },
- { "fp22" , IEEE754, 8, Float },
- { "fp23" , IEEE754, 8, Float },
- { "fp24" , IEEE754, 8, Float },
- { "fp25" , IEEE754, 8, Float },
- { "fp26" , IEEE754, 8, Float },
- { "fp27" , IEEE754, 8, Float },
- { "fp28" , IEEE754, 8, Float },
- { "fp29" , IEEE754, 8, Float },
- { "fp30" , IEEE754, 8, Float },
- { "fp31" , IEEE754, 8, Float },
- { "fpscr" , Uint, 4, Hex }
-};
+static DNBRegisterInfo g_fpr_registers[] = {
+ {"fp0", IEEE754, 8, Float}, {"fp1", IEEE754, 8, Float},
+ {"fp2", IEEE754, 8, Float}, {"fp3", IEEE754, 8, Float},
+ {"fp4", IEEE754, 8, Float}, {"fp5", IEEE754, 8, Float},
+ {"fp6", IEEE754, 8, Float}, {"fp7", IEEE754, 8, Float},
+ {"fp8", IEEE754, 8, Float}, {"fp9", IEEE754, 8, Float},
+ {"fp10", IEEE754, 8, Float}, {"fp11", IEEE754, 8, Float},
+ {"fp12", IEEE754, 8, Float}, {"fp13", IEEE754, 8, Float},
+ {"fp14", IEEE754, 8, Float}, {"fp15", IEEE754, 8, Float},
+ {"fp16", IEEE754, 8, Float}, {"fp17", IEEE754, 8, Float},
+ {"fp18", IEEE754, 8, Float}, {"fp19", IEEE754, 8, Float},
+ {"fp20", IEEE754, 8, Float}, {"fp21", IEEE754, 8, Float},
+ {"fp22", IEEE754, 8, Float}, {"fp23", IEEE754, 8, Float},
+ {"fp24", IEEE754, 8, Float}, {"fp25", IEEE754, 8, Float},
+ {"fp26", IEEE754, 8, Float}, {"fp27", IEEE754, 8, Float},
+ {"fp28", IEEE754, 8, Float}, {"fp29", IEEE754, 8, Float},
+ {"fp30", IEEE754, 8, Float}, {"fp31", IEEE754, 8, Float},
+ {"fpscr", Uint, 4, Hex}};
// Exception registers
-static DNBRegisterInfo g_exc_registers[] =
-{
- { "dar" , Uint, 4, Hex },
- { "dsisr" , Uint, 4, Hex },
- { "exception" , Uint, 4, Hex }
-};
+static DNBRegisterInfo g_exc_registers[] = {{"dar", Uint, 4, Hex},
+ {"dsisr", Uint, 4, Hex},
+ {"exception", Uint, 4, Hex}};
// Altivec registers
-static DNBRegisterInfo g_vec_registers[] =
-{
- { "vr0" , Vector, 16, VectorOfFloat32 },
- { "vr1" , Vector, 16, VectorOfFloat32 },
- { "vr2" , Vector, 16, VectorOfFloat32 },
- { "vr3" , Vector, 16, VectorOfFloat32 },
- { "vr4" , Vector, 16, VectorOfFloat32 },
- { "vr5" , Vector, 16, VectorOfFloat32 },
- { "vr6" , Vector, 16, VectorOfFloat32 },
- { "vr7" , Vector, 16, VectorOfFloat32 },
- { "vr8" , Vector, 16, VectorOfFloat32 },
- { "vr9" , Vector, 16, VectorOfFloat32 },
- { "vr10" , Vector, 16, VectorOfFloat32 },
- { "vr11" , Vector, 16, VectorOfFloat32 },
- { "vr12" , Vector, 16, VectorOfFloat32 },
- { "vr13" , Vector, 16, VectorOfFloat32 },
- { "vr14" , Vector, 16, VectorOfFloat32 },
- { "vr15" , Vector, 16, VectorOfFloat32 },
- { "vr16" , Vector, 16, VectorOfFloat32 },
- { "vr17" , Vector, 16, VectorOfFloat32 },
- { "vr18" , Vector, 16, VectorOfFloat32 },
- { "vr19" , Vector, 16, VectorOfFloat32 },
- { "vr20" , Vector, 16, VectorOfFloat32 },
- { "vr21" , Vector, 16, VectorOfFloat32 },
- { "vr22" , Vector, 16, VectorOfFloat32 },
- { "vr23" , Vector, 16, VectorOfFloat32 },
- { "vr24" , Vector, 16, VectorOfFloat32 },
- { "vr25" , Vector, 16, VectorOfFloat32 },
- { "vr26" , Vector, 16, VectorOfFloat32 },
- { "vr27" , Vector, 16, VectorOfFloat32 },
- { "vr28" , Vector, 16, VectorOfFloat32 },
- { "vr29" , Vector, 16, VectorOfFloat32 },
- { "vr30" , Vector, 16, VectorOfFloat32 },
- { "vr31" , Vector, 16, VectorOfFloat32 },
- { "vscr" , Uint, 16, Hex },
- { "vrvalid" , Uint, 4, Hex }
-};
+static DNBRegisterInfo g_vec_registers[] = {
+ {"vr0", Vector, 16, VectorOfFloat32},
+ {"vr1", Vector, 16, VectorOfFloat32},
+ {"vr2", Vector, 16, VectorOfFloat32},
+ {"vr3", Vector, 16, VectorOfFloat32},
+ {"vr4", Vector, 16, VectorOfFloat32},
+ {"vr5", Vector, 16, VectorOfFloat32},
+ {"vr6", Vector, 16, VectorOfFloat32},
+ {"vr7", Vector, 16, VectorOfFloat32},
+ {"vr8", Vector, 16, VectorOfFloat32},
+ {"vr9", Vector, 16, VectorOfFloat32},
+ {"vr10", Vector, 16, VectorOfFloat32},
+ {"vr11", Vector, 16, VectorOfFloat32},
+ {"vr12", Vector, 16, VectorOfFloat32},
+ {"vr13", Vector, 16, VectorOfFloat32},
+ {"vr14", Vector, 16, VectorOfFloat32},
+ {"vr15", Vector, 16, VectorOfFloat32},
+ {"vr16", Vector, 16, VectorOfFloat32},
+ {"vr17", Vector, 16, VectorOfFloat32},
+ {"vr18", Vector, 16, VectorOfFloat32},
+ {"vr19", Vector, 16, VectorOfFloat32},
+ {"vr20", Vector, 16, VectorOfFloat32},
+ {"vr21", Vector, 16, VectorOfFloat32},
+ {"vr22", Vector, 16, VectorOfFloat32},
+ {"vr23", Vector, 16, VectorOfFloat32},
+ {"vr24", Vector, 16, VectorOfFloat32},
+ {"vr25", Vector, 16, VectorOfFloat32},
+ {"vr26", Vector, 16, VectorOfFloat32},
+ {"vr27", Vector, 16, VectorOfFloat32},
+ {"vr28", Vector, 16, VectorOfFloat32},
+ {"vr29", Vector, 16, VectorOfFloat32},
+ {"vr30", Vector, 16, VectorOfFloat32},
+ {"vr31", Vector, 16, VectorOfFloat32},
+ {"vscr", Uint, 16, Hex},
+ {"vrvalid", Uint, 4, Hex}};
// Number of registers in each register set
-const size_t k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo);
-const size_t k_num_fpr_registers = sizeof(g_fpr_registers)/sizeof(DNBRegisterInfo);
-const size_t k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo);
-const size_t k_num_vec_registers = sizeof(g_vec_registers)/sizeof(DNBRegisterInfo);
+const size_t k_num_gpr_registers =
+ sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
+const size_t k_num_fpr_registers =
+ sizeof(g_fpr_registers) / sizeof(DNBRegisterInfo);
+const size_t k_num_exc_registers =
+ sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
+const size_t k_num_vec_registers =
+ sizeof(g_vec_registers) / sizeof(DNBRegisterInfo);
// Total number of registers for this architecture
-const size_t k_num_ppc_registers = k_num_gpr_registers + k_num_fpr_registers + k_num_exc_registers + k_num_vec_registers;
+const size_t k_num_ppc_registers = k_num_gpr_registers + k_num_fpr_registers +
+ k_num_exc_registers + k_num_vec_registers;
//----------------------------------------------------------------------
// Register set definitions. The first definitions at register set index
// of zero is for all registers, followed by other registers sets. The
// register information for the all register set need not be filled in.
//----------------------------------------------------------------------
-static const DNBRegisterSetInfo g_reg_sets[] =
-{
- { "PowerPC Registers", NULL, k_num_ppc_registers },
- { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers },
- { "Floating Point Registers", g_fpr_registers, k_num_fpr_registers },
- { "Exception State Registers", g_exc_registers, k_num_exc_registers },
- { "Altivec Registers", g_vec_registers, k_num_vec_registers }
-};
+static const DNBRegisterSetInfo g_reg_sets[] = {
+ {"PowerPC Registers", NULL, k_num_ppc_registers},
+ {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
+ {"Floating Point Registers", g_fpr_registers, k_num_fpr_registers},
+ {"Exception State Registers", g_exc_registers, k_num_exc_registers},
+ {"Altivec Registers", g_vec_registers, k_num_vec_registers}};
// Total number of register sets for this architecture
-const size_t k_num_register_sets = sizeof(g_reg_sets)/sizeof(DNBRegisterSetInfo);
-
+const size_t k_num_register_sets =
+ sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo);
const DNBRegisterSetInfo *
-DNBArchMachPPC::GetRegisterSetInfo(nub_size_t *num_reg_sets) const
-{
- *num_reg_sets = k_num_register_sets;
- return g_reg_sets;
-}
-
-bool
-DNBArchMachPPC::GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value) const
-{
- if (set == REGISTER_SET_GENERIC)
- {
- switch (reg)
- {
- case GENERIC_REGNUM_PC: // Program Counter
- set = e_regSetGPR;
- reg = e_regNumGPR_srr0;
- break;
-
- case GENERIC_REGNUM_SP: // Stack Pointer
- set = e_regSetGPR;
- reg = e_regNumGPR_r1;
- break;
-
- case GENERIC_REGNUM_FP: // Frame Pointer
- // Return false for now instead of returning r30 as gcc 3.x would
- // use a variety of registers for the FP and it takes inspecting
- // the stack to make sure there is a frame pointer before we can
- // determine the FP.
- return false;
-
- case GENERIC_REGNUM_RA: // Return Address
- set = e_regSetGPR;
- reg = e_regNumGPR_lr;
- break;
-
- case GENERIC_REGNUM_FLAGS: // Processor flags register
- set = e_regSetGPR;
- reg = e_regNumGPR_srr1;
- break;
+DNBArchMachPPC::GetRegisterSetInfo(nub_size_t *num_reg_sets) const {
+ *num_reg_sets = k_num_register_sets;
+ return g_reg_sets;
+}
+
+bool DNBArchMachPPC::GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value) const {
+ if (set == REGISTER_SET_GENERIC) {
+ switch (reg) {
+ case GENERIC_REGNUM_PC: // Program Counter
+ set = e_regSetGPR;
+ reg = e_regNumGPR_srr0;
+ break;
+
+ case GENERIC_REGNUM_SP: // Stack Pointer
+ set = e_regSetGPR;
+ reg = e_regNumGPR_r1;
+ break;
+
+ case GENERIC_REGNUM_FP: // Frame Pointer
+ // Return false for now instead of returning r30 as gcc 3.x would
+ // use a variety of registers for the FP and it takes inspecting
+ // the stack to make sure there is a frame pointer before we can
+ // determine the FP.
+ return false;
+
+ case GENERIC_REGNUM_RA: // Return Address
+ set = e_regSetGPR;
+ reg = e_regNumGPR_lr;
+ break;
+
+ case GENERIC_REGNUM_FLAGS: // Processor flags register
+ set = e_regSetGPR;
+ reg = e_regNumGPR_srr1;
+ break;
- default:
- return false;
- }
+ default:
+ return false;
}
+ }
- if (!m_state.RegsAreValid(set))
- return false;
+ if (!m_state.RegsAreValid(set))
+ return false;
- const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
- if (regInfo)
- {
- value->info = *regInfo;
- switch (set)
+ const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
+ if (regInfo) {
+ value->info = *regInfo;
+ switch (set) {
+ case e_regSetGPR:
+ if (reg < k_num_gpr_registers) {
+ value->value.uint32 =
+ (&m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0))[reg];
+ return true;
+ }
+ break;
+
+ case e_regSetFPR:
+ if (reg < 32) {
+ value->value.float64 =
+ m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpregs)[reg];
+ return true;
+ } else if (reg == 32) {
+ value->value.uint32 =
+ m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpscr);
+ return true;
+ }
+ break;
+
+ case e_regSetEXC:
+ if (reg < k_num_exc_registers) {
+ value->value.uint32 =
+ (&m_state.exc.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(dar))[reg];
+ return true;
+ }
+ break;
+
+ case e_regSetVEC:
+ if (reg < k_num_vec_registers) {
+ if (reg < 33) // FP0 - FP31 and VSCR
+ {
+ // Copy all 4 uint32 values for this vector register
+ value->value.v_uint32[0] =
+ m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
+ [0];
+ value->value.v_uint32[1] =
+ m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
+ [1];
+ value->value.v_uint32[2] =
+ m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
+ [2];
+ value->value.v_uint32[3] =
+ m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
+ [3];
+ return true;
+ } else if (reg == 34) // VRVALID
{
- case e_regSetGPR:
- if (reg < k_num_gpr_registers)
- {
- value->value.uint32 = (&m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0))[reg];
- return true;
- }
- break;
-
- case e_regSetFPR:
- if (reg < 32)
- {
- value->value.float64 = m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpregs)[reg];
- return true;
- }
- else if (reg == 32)
- {
- value->value.uint32 = m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpscr);
- return true;
- }
- break;
-
- case e_regSetEXC:
- if (reg < k_num_exc_registers)
- {
- value->value.uint32 = (&m_state.exc.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(dar))[reg];
- return true;
- }
- break;
-
- case e_regSetVEC:
- if (reg < k_num_vec_registers)
- {
- if (reg < 33) // FP0 - FP31 and VSCR
- {
- // Copy all 4 uint32 values for this vector register
- value->value.v_uint32[0] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][0];
- value->value.v_uint32[1] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][1];
- value->value.v_uint32[2] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][2];
- value->value.v_uint32[3] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][3];
- return true;
- }
- else if (reg == 34) // VRVALID
- {
- value->value.uint32 = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vrvalid);
- return true;
- }
- }
- break;
+ value->value.uint32 =
+ m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vrvalid);
+ return true;
}
+ }
+ break;
}
- return false;
-}
-
-
-kern_return_t
-DNBArchMachPPC::GetRegisterState(int set, bool force)
-{
- switch (set)
- {
- case e_regSetALL:
- return GetGPRState(force) |
- GetFPRState(force) |
- GetEXCState(force) |
- GetVECState(force);
- case e_regSetGPR: return GetGPRState(force);
- case e_regSetFPR: return GetFPRState(force);
- case e_regSetEXC: return GetEXCState(force);
- case e_regSetVEC: return GetVECState(force);
- default: break;
- }
- return KERN_INVALID_ARGUMENT;
+ }
+ return false;
}
-kern_return_t
-DNBArchMachPPC::SetRegisterState(int set)
-{
- // Make sure we have a valid context to set.
- kern_return_t err = GetRegisterState(set, false);
- if (err != KERN_SUCCESS)
- return err;
-
- switch (set)
- {
- case e_regSetALL: return SetGPRState() | SetFPRState() | SetEXCState() | SetVECState();
- case e_regSetGPR: return SetGPRState();
- case e_regSetFPR: return SetFPRState();
- case e_regSetEXC: return SetEXCState();
- case e_regSetVEC: return SetVECState();
- default: break;
- }
- return KERN_INVALID_ARGUMENT;
+kern_return_t DNBArchMachPPC::GetRegisterState(int set, bool force) {
+ switch (set) {
+ case e_regSetALL:
+ return GetGPRState(force) | GetFPRState(force) | GetEXCState(force) |
+ GetVECState(force);
+ case e_regSetGPR:
+ return GetGPRState(force);
+ case e_regSetFPR:
+ return GetFPRState(force);
+ case e_regSetEXC:
+ return GetEXCState(force);
+ case e_regSetVEC:
+ return GetVECState(force);
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
+}
+
+kern_return_t DNBArchMachPPC::SetRegisterState(int set) {
+ // Make sure we have a valid context to set.
+ kern_return_t err = GetRegisterState(set, false);
+ if (err != KERN_SUCCESS)
+ return err;
+
+ switch (set) {
+ case e_regSetALL:
+ return SetGPRState() | SetFPRState() | SetEXCState() | SetVECState();
+ case e_regSetGPR:
+ return SetGPRState();
+ case e_regSetFPR:
+ return SetFPRState();
+ case e_regSetEXC:
+ return SetEXCState();
+ case e_regSetVEC:
+ return SetVECState();
+ default:
+ break;
+ }
+ return KERN_INVALID_ARGUMENT;
}
-bool
-DNBArchMachPPC::RegisterSetStateIsValid (int set) const
-{
- return m_state.RegsAreValid(set);
+bool DNBArchMachPPC::RegisterSetStateIsValid(int set) const {
+ return m_state.RegsAreValid(set);
}
-
-#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
-
+#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
Modified: lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/ppc/DNBArchImpl.h Tue Sep 6 15:57:50 2016
@@ -14,166 +14,147 @@
#ifndef __DebugNubArchMachPPC_h__
#define __DebugNubArchMachPPC_h__
-#if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
+#if defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)
#include "DNBArch.h"
class MachThread;
-class DNBArchMachPPC : public DNBArchProtocol
-{
+class DNBArchMachPPC : public DNBArchProtocol {
public:
- DNBArchMachPPC(MachThread *thread) :
- m_thread(thread),
- m_state()
- {
- }
+ DNBArchMachPPC(MachThread *thread) : m_thread(thread), m_state() {}
- virtual ~DNBArchMachPPC()
- {
- }
+ virtual ~DNBArchMachPPC() {}
- virtual const DNBRegisterSetInfo *
- GetRegisterSetInfo(nub_size_t *num_reg_sets) const;
- virtual bool GetRegisterValue(uint32_t set, uint32_t reg, DNBRegisterValue *value) const;
- virtual kern_return_t GetRegisterState (int set, bool force);
- virtual kern_return_t SetRegisterState (int set);
- virtual bool RegisterSetStateIsValid (int set) const;
-
- virtual uint64_t GetPC(uint64_t failValue); // Get program counter
- virtual kern_return_t SetPC(uint64_t value);
- virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
- virtual bool ThreadWillResume();
- virtual bool ThreadDidStop();
+ virtual const DNBRegisterSetInfo *
+ GetRegisterSetInfo(nub_size_t *num_reg_sets) const;
+ virtual bool GetRegisterValue(uint32_t set, uint32_t reg,
+ DNBRegisterValue *value) const;
+ virtual kern_return_t GetRegisterState(int set, bool force);
+ virtual kern_return_t SetRegisterState(int set);
+ virtual bool RegisterSetStateIsValid(int set) const;
+
+ virtual uint64_t GetPC(uint64_t failValue); // Get program counter
+ virtual kern_return_t SetPC(uint64_t value);
+ virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
+ virtual bool ThreadWillResume();
+ virtual bool ThreadDidStop();
- static const uint8_t * SoftwareBreakpointOpcode (nub_size_t byte_size);
- static uint32_t GetCPUType();
+ static const uint8_t *SoftwareBreakpointOpcode(nub_size_t byte_size);
+ static uint32_t GetCPUType();
protected:
+ kern_return_t EnableHardwareSingleStep(bool enable);
-
- kern_return_t EnableHardwareSingleStep (bool enable);
-
- typedef enum RegisterSetTag
- {
- e_regSetALL = REGISTER_SET_ALL,
- e_regSetGPR,
- e_regSetFPR,
- e_regSetEXC,
- e_regSetVEC,
- kNumRegisterSets
- } RegisterSet;
-
- typedef enum RegisterSetWordSizeTag
- {
- e_regSetWordSizeGPR = PPC_THREAD_STATE_COUNT,
- e_regSetWordSizeFPR = PPC_FLOAT_STATE_COUNT,
- e_regSetWordSizeEXC = PPC_EXCEPTION_STATE_COUNT,
- e_regSetWordSizeVEC = PPC_VECTOR_STATE_COUNT
- } RegisterSetWordSize;
-
- enum
- {
- Read = 0,
- Write = 1,
- kNumErrors = 2
- };
-
- struct State
- {
- ppc_thread_state_t gpr;
- ppc_float_state_t fpr;
- ppc_exception_state_t exc;
- ppc_vector_state_t vec;
- kern_return_t gpr_errs[2]; // Read/Write errors
- kern_return_t fpr_errs[2]; // Read/Write errors
- kern_return_t exc_errs[2]; // Read/Write errors
- kern_return_t vec_errs[2]; // Read/Write errors
-
- State()
- {
- uint32_t i;
- for (i=0; i<kNumErrors; i++)
- {
- gpr_errs[i] = -1;
- fpr_errs[i] = -1;
- exc_errs[i] = -1;
- vec_errs[i] = -1;
- }
- }
- void InvalidateAllRegisterStates()
- {
- SetError (e_regSetALL, Read, -1);
- }
- kern_return_t GetError (int set, uint32_t err_idx) const
- {
- if (err_idx < kNumErrors)
- {
- switch (set)
- {
- // When getting all errors, just OR all values together to see if
- // we got any kind of error.
- case e_regSetALL: return gpr_errs[err_idx] | fpr_errs[err_idx] | exc_errs[err_idx] | vec_errs[err_idx];
- case e_regSetGPR: return gpr_errs[err_idx];
- case e_regSetFPR: return fpr_errs[err_idx];
- case e_regSetEXC: return exc_errs[err_idx];
- case e_regSetVEC: return vec_errs[err_idx];
- default: break;
- }
- }
- return -1;
- }
- bool SetError (int set, uint32_t err_idx, kern_return_t err)
- {
- if (err_idx < kNumErrors)
- {
- switch (set)
- {
- case e_regSetALL:
- gpr_errs[err_idx] = fpr_errs[err_idx] = exc_errs[err_idx] = vec_errs[err_idx] = err;
- return true;
-
- case e_regSetGPR:
- gpr_errs[err_idx] = err;
- return true;
-
- case e_regSetFPR:
- fpr_errs[err_idx] = err;
- return true;
-
- case e_regSetEXC:
- exc_errs[err_idx] = err;
- return true;
-
- case e_regSetVEC:
- vec_errs[err_idx] = err;
- return true;
-
- default: break;
- }
- }
- return false;
+ typedef enum RegisterSetTag {
+ e_regSetALL = REGISTER_SET_ALL,
+ e_regSetGPR,
+ e_regSetFPR,
+ e_regSetEXC,
+ e_regSetVEC,
+ kNumRegisterSets
+ } RegisterSet;
+
+ typedef enum RegisterSetWordSizeTag {
+ e_regSetWordSizeGPR = PPC_THREAD_STATE_COUNT,
+ e_regSetWordSizeFPR = PPC_FLOAT_STATE_COUNT,
+ e_regSetWordSizeEXC = PPC_EXCEPTION_STATE_COUNT,
+ e_regSetWordSizeVEC = PPC_VECTOR_STATE_COUNT
+ } RegisterSetWordSize;
+
+ enum { Read = 0, Write = 1, kNumErrors = 2 };
+
+ struct State {
+ ppc_thread_state_t gpr;
+ ppc_float_state_t fpr;
+ ppc_exception_state_t exc;
+ ppc_vector_state_t vec;
+ kern_return_t gpr_errs[2]; // Read/Write errors
+ kern_return_t fpr_errs[2]; // Read/Write errors
+ kern_return_t exc_errs[2]; // Read/Write errors
+ kern_return_t vec_errs[2]; // Read/Write errors
+
+ State() {
+ uint32_t i;
+ for (i = 0; i < kNumErrors; i++) {
+ gpr_errs[i] = -1;
+ fpr_errs[i] = -1;
+ exc_errs[i] = -1;
+ vec_errs[i] = -1;
+ }
+ }
+ void InvalidateAllRegisterStates() { SetError(e_regSetALL, Read, -1); }
+ kern_return_t GetError(int set, uint32_t err_idx) const {
+ if (err_idx < kNumErrors) {
+ switch (set) {
+ // When getting all errors, just OR all values together to see if
+ // we got any kind of error.
+ case e_regSetALL:
+ return gpr_errs[err_idx] | fpr_errs[err_idx] | exc_errs[err_idx] |
+ vec_errs[err_idx];
+ case e_regSetGPR:
+ return gpr_errs[err_idx];
+ case e_regSetFPR:
+ return fpr_errs[err_idx];
+ case e_regSetEXC:
+ return exc_errs[err_idx];
+ case e_regSetVEC:
+ return vec_errs[err_idx];
+ default:
+ break;
}
- bool RegsAreValid (int set) const
- {
- return GetError(set, Read) == KERN_SUCCESS;
+ }
+ return -1;
+ }
+ bool SetError(int set, uint32_t err_idx, kern_return_t err) {
+ if (err_idx < kNumErrors) {
+ switch (set) {
+ case e_regSetALL:
+ gpr_errs[err_idx] = fpr_errs[err_idx] = exc_errs[err_idx] =
+ vec_errs[err_idx] = err;
+ return true;
+
+ case e_regSetGPR:
+ gpr_errs[err_idx] = err;
+ return true;
+
+ case e_regSetFPR:
+ fpr_errs[err_idx] = err;
+ return true;
+
+ case e_regSetEXC:
+ exc_errs[err_idx] = err;
+ return true;
+
+ case e_regSetVEC:
+ vec_errs[err_idx] = err;
+ return true;
+
+ default:
+ break;
}
- };
+ }
+ return false;
+ }
+ bool RegsAreValid(int set) const {
+ return GetError(set, Read) == KERN_SUCCESS;
+ }
+ };
- kern_return_t GetGPRState (bool force);
- kern_return_t GetFPRState (bool force);
- kern_return_t GetEXCState (bool force);
- kern_return_t GetVECState (bool force);
-
- kern_return_t SetGPRState ();
- kern_return_t SetFPRState ();
- kern_return_t SetEXCState ();
- kern_return_t SetVECState ();
+ kern_return_t GetGPRState(bool force);
+ kern_return_t GetFPRState(bool force);
+ kern_return_t GetEXCState(bool force);
+ kern_return_t GetVECState(bool force);
+
+ kern_return_t SetGPRState();
+ kern_return_t SetFPRState();
+ kern_return_t SetEXCState();
+ kern_return_t SetVECState();
protected:
- MachThread * m_thread;
- State m_state;
+ MachThread *m_thread;
+ State m_state;
};
-#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
-#endif // #ifndef __DebugNubArchMachPPC_h__
+#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
+#endif // #ifndef __DebugNubArchMachPPC_h__
Modified: lldb/trunk/tools/debugserver/source/MacOSX/stack_logging.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/stack_logging.h?rev=280751&r1=280750&r2=280751&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/stack_logging.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/stack_logging.h Tue Sep 6 15:57:50 2016
@@ -2,14 +2,14 @@
* Copyright (c) 1999-2007 Apple Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
- *
+ *
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
* compliance with the License. Please obtain a copy of the License at
* http://www.opensource.apple.com/apsl/ and read it before using this
* file.
- *
+ *
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
@@ -17,7 +17,7 @@
* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
* Please see the License for the specific language governing rights and
* limitations under the License.
- *
+ *
* @APPLE_LICENSE_HEADER_END@
*/
@@ -26,96 +26,132 @@
#import <malloc/malloc.h>
-#define stack_logging_type_free 0
-#define stack_logging_type_generic 1 /* anything that is not allocation/deallocation */
-#define stack_logging_type_alloc 2 /* malloc, realloc, etc... */
-#define stack_logging_type_dealloc 4 /* free, realloc, etc... */
+#define stack_logging_type_free 0
+#define stack_logging_type_generic \
+ 1 /* anything that is not allocation/deallocation */
+#define stack_logging_type_alloc 2 /* malloc, realloc, etc... */
+#define stack_logging_type_dealloc 4 /* free, realloc, etc... */
// Following flags are absorbed by stack_logging_log_stack()
-#define stack_logging_flag_zone 8 /* NSZoneMalloc, etc... */
-#define stack_logging_flag_calloc 16 /* multiply arguments to get the size */
-#define stack_logging_flag_object 32 /* NSAllocateObject(Class, extraBytes, zone) */
-#define stack_logging_flag_cleared 64 /* for NewEmptyHandle */
-#define stack_logging_flag_handle 128 /* for Handle (de-)allocation routines */
-#define stack_logging_flag_set_handle_size 256 /* (Handle, newSize) treated specially */
+#define stack_logging_flag_zone 8 /* NSZoneMalloc, etc... */
+#define stack_logging_flag_calloc 16 /* multiply arguments to get the size */
+#define stack_logging_flag_object \
+ 32 /* NSAllocateObject(Class, extraBytes, zone) */
+#define stack_logging_flag_cleared 64 /* for NewEmptyHandle */
+#define stack_logging_flag_handle 128 /* for Handle (de-)allocation routines \
+ */
+#define stack_logging_flag_set_handle_size \
+ 256 /* (Handle, newSize) treated specially */
/* Macro used to disguise addresses so that leak finding can work */
-#define STACK_LOGGING_DISGUISE(address) ((address) ^ 0x00005555) /* nicely idempotent */
-
-extern "C" int stack_logging_enable_logging; /* when clear, no logging takes place */
-extern "C" int stack_logging_dontcompact; /* default is to compact; when set does not compact alloc/free logs; useful for tracing history */
-
-
-extern "C" void stack_logging_log_stack(unsigned type, unsigned arg1, unsigned arg2, unsigned arg3, unsigned result, unsigned num_hot_to_skip);
-/* This is the old log-to-memory logger, which is now deprecated. It remains for compatibility with performance tools that haven't been updated to disk_stack_logging_log_stack() yet. */
-
-extern "C" void __disk_stack_logging_log_stack(uint32_t type_flags, uintptr_t zone_ptr, uintptr_t size, uintptr_t ptr_arg, uintptr_t return_val, uint32_t num_hot_to_skip);
-/* Fits as the malloc_logger; logs malloc/free/realloc events and can log custom events if called directly */
+#define STACK_LOGGING_DISGUISE(address) \
+ ((address) ^ 0x00005555) /* nicely idempotent */
+extern "C" int
+ stack_logging_enable_logging; /* when clear, no logging takes place */
+extern "C" int stack_logging_dontcompact; /* default is to compact; when set
+ does not compact alloc/free logs;
+ useful for tracing history */
+
+extern "C" void stack_logging_log_stack(unsigned type, unsigned arg1,
+ unsigned arg2, unsigned arg3,
+ unsigned result,
+ unsigned num_hot_to_skip);
+/* This is the old log-to-memory logger, which is now deprecated. It remains
+ * for compatibility with performance tools that haven't been updated to
+ * disk_stack_logging_log_stack() yet. */
+
+extern "C" void
+__disk_stack_logging_log_stack(uint32_t type_flags, uintptr_t zone_ptr,
+ uintptr_t size, uintptr_t ptr_arg,
+ uintptr_t return_val, uint32_t num_hot_to_skip);
+/* Fits as the malloc_logger; logs malloc/free/realloc events and can log custom
+ * events if called directly */
/* 64-bit-aware stack log access. */
typedef struct {
- uint32_t type_flags;
- uint64_t stack_identifier;
- uint64_t argument;
- mach_vm_address_t address;
+ uint32_t type_flags;
+ uint64_t stack_identifier;
+ uint64_t argument;
+ mach_vm_address_t address;
} mach_stack_logging_record_t;
-extern "C" kern_return_t __mach_stack_logging_get_frames(task_t task, mach_vm_address_t address, mach_vm_address_t *stack_frames_buffer, uint32_t max_stack_frames, uint32_t *count);
+extern "C" kern_return_t
+__mach_stack_logging_get_frames(task_t task, mach_vm_address_t address,
+ mach_vm_address_t *stack_frames_buffer,
+ uint32_t max_stack_frames, uint32_t *count);
/* Gets the last allocation record (malloc, realloc, or free) about address */
-extern "C" kern_return_t __mach_stack_logging_enumerate_records(task_t task, mach_vm_address_t address, void enumerator(mach_stack_logging_record_t, void *), void *context);
-/* Applies enumerator to all records involving address sending context as enumerator's second parameter; if !address, applies enumerator to all records */
+extern "C" kern_return_t __mach_stack_logging_enumerate_records(
+ task_t task, mach_vm_address_t address,
+ void enumerator(mach_stack_logging_record_t, void *), void *context);
+/* Applies enumerator to all records involving address sending context as
+ * enumerator's second parameter; if !address, applies enumerator to all records
+ */
-extern "C" kern_return_t __mach_stack_logging_frames_for_uniqued_stack(task_t task, uint64_t stack_identifier, mach_vm_address_t *stack_frames_buffer, uint32_t max_stack_frames, uint32_t *count);
+extern "C" kern_return_t __mach_stack_logging_frames_for_uniqued_stack(
+ task_t task, uint64_t stack_identifier,
+ mach_vm_address_t *stack_frames_buffer, uint32_t max_stack_frames,
+ uint32_t *count);
/* Given a uniqued_stack fills stack_frames_buffer */
-
#pragma mark -
#pragma mark Legacy
-/* The following is the old 32-bit-only, in-process-memory stack logging. This is deprecated and clients should move to the above 64-bit-aware disk stack logging SPI. */
+/* The following is the old 32-bit-only, in-process-memory stack logging. This
+ * is deprecated and clients should move to the above 64-bit-aware disk stack
+ * logging SPI. */
typedef struct {
- unsigned type;
- unsigned uniqued_stack;
- unsigned argument;
- unsigned address; /* disguised, to avoid confusing leaks */
+ unsigned type;
+ unsigned uniqued_stack;
+ unsigned argument;
+ unsigned address; /* disguised, to avoid confusing leaks */
} stack_logging_record_t;
typedef struct {
- unsigned overall_num_bytes;
- unsigned num_records;
- unsigned lock; /* 0 means OK to lock; used for inter-process locking */
- unsigned *uniquing_table; /* allocated using vm_allocate() */
- /* hashtable organized as (PC, uniqued parent)
- Only the second half of the table is active
- To enable us to grow dynamically */
- unsigned uniquing_table_num_pages; /* number of pages of the table */
- unsigned extra_retain_count; /* not used by stack_logging_log_stack */
- unsigned filler[2]; /* align to cache lines for better performance */
- stack_logging_record_t records[0]; /* records follow here */
+ unsigned overall_num_bytes;
+ unsigned num_records;
+ unsigned lock; /* 0 means OK to lock; used for inter-process locking */
+ unsigned *uniquing_table; /* allocated using vm_allocate() */
+ /* hashtable organized as (PC, uniqued parent)
+ Only the second half of the table is active
+ To enable us to grow dynamically */
+ unsigned uniquing_table_num_pages; /* number of pages of the table */
+ unsigned extra_retain_count; /* not used by stack_logging_log_stack */
+ unsigned filler[2]; /* align to cache lines for better performance */
+ stack_logging_record_t records[0]; /* records follow here */
} stack_logging_record_list_t;
extern "C" stack_logging_record_list_t *stack_logging_the_record_list;
/* This is the global variable containing all logs */
-extern "C" kern_return_t stack_logging_get_frames(task_t task, memory_reader_t reader, vm_address_t address, vm_address_t *stack_frames_buffer, unsigned max_stack_frames, unsigned *num_frames);
+extern "C" kern_return_t
+stack_logging_get_frames(task_t task, memory_reader_t reader,
+ vm_address_t address,
+ vm_address_t *stack_frames_buffer,
+ unsigned max_stack_frames, unsigned *num_frames);
/* Gets the last record in stack_logging_the_record_list about address */
-#define STACK_LOGGING_ENUMERATION_PROVIDED 1 // temporary to avoid dependencies between projects
+#define STACK_LOGGING_ENUMERATION_PROVIDED \
+ 1 // temporary to avoid dependencies between projects
-extern "C" kern_return_t stack_logging_enumerate_records(task_t task, memory_reader_t reader, vm_address_t address, void enumerator(stack_logging_record_t, void *), void *context);
+extern "C" kern_return_t stack_logging_enumerate_records(
+ task_t task, memory_reader_t reader, vm_address_t address,
+ void enumerator(stack_logging_record_t, void *), void *context);
/* Gets all the records about address;
If !address, gets all records */
-extern "C" kern_return_t stack_logging_frames_for_uniqued_stack(task_t task, memory_reader_t reader, unsigned uniqued_stack, vm_address_t *stack_frames_buffer, unsigned max_stack_frames, unsigned *num_frames);
+extern "C" kern_return_t stack_logging_frames_for_uniqued_stack(
+ task_t task, memory_reader_t reader, unsigned uniqued_stack,
+ vm_address_t *stack_frames_buffer, unsigned max_stack_frames,
+ unsigned *num_frames);
/* Given a uniqued_stack fills stack_frames_buffer */
-
-
-extern "C" void thread_stack_pcs(vm_address_t *buffer, unsigned max, unsigned *num);
-/* Convenience to fill buffer with the PCs of the frames, starting with the hot frames;
+extern "C" void thread_stack_pcs(vm_address_t *buffer, unsigned max,
+ unsigned *num);
+/* Convenience to fill buffer with the PCs of the frames, starting with the hot
+ frames;
num: returned number of frames
*/
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