[Lldb-commits] [PATCH] [MIPS] Emulation of MIPS64 floating-point branch instructions
Jaydeep Patil
jaydeep.patil at imgtec.com
Tue Jun 16 20:59:50 PDT 2015
REPOSITORY
rL LLVM
================
Comment at: source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp:640-678
@@ -639,3 +639,41 @@
- m_disasm_ap.reset (new LLVMCDisassembler(triple, flavor, *this));
+ const char *cpu = "";
+
+ switch (arch.GetCore())
+ {
+ case ArchSpec::eCore_mips32:
+ case ArchSpec::eCore_mips32el:
+ cpu = "mips32"; break;
+ case ArchSpec::eCore_mips32r2:
+ case ArchSpec::eCore_mips32r2el:
+ cpu = "mips32r2"; break;
+ case ArchSpec::eCore_mips32r3:
+ case ArchSpec::eCore_mips32r3el:
+ cpu = "mips32r3"; break;
+ case ArchSpec::eCore_mips32r5:
+ case ArchSpec::eCore_mips32r5el:
+ cpu = "mips32r5"; break;
+ case ArchSpec::eCore_mips32r6:
+ case ArchSpec::eCore_mips32r6el:
+ cpu = "mips32r6"; break;
+ case ArchSpec::eCore_mips64:
+ case ArchSpec::eCore_mips64el:
+ cpu = "mips64"; break;
+ case ArchSpec::eCore_mips64r2:
+ case ArchSpec::eCore_mips64r2el:
+ cpu = "mips64r2"; break;
+ case ArchSpec::eCore_mips64r3:
+ case ArchSpec::eCore_mips64r3el:
+ cpu = "mips64r3"; break;
+ case ArchSpec::eCore_mips64r5:
+ case ArchSpec::eCore_mips64r5el:
+ cpu = "mips64r5"; break;
+ case ArchSpec::eCore_mips64r6:
+ case ArchSpec::eCore_mips64r6el:
+ cpu = "mips64r6"; break;
+ default:
+ cpu = ""; break;
+ }
+
+ m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this));
if (!m_disasm_ap->IsValid())
----------------
clayborg wrote:
> Is CPU needed here? We are passing the triple which should contain the CPU name right? Why do we need "cpu" here as a separate thing?
The triple does not contain MIPS ISA revision (like r2, r3, r5, r6 etc.) which is required for disassembly.
http://reviews.llvm.org/D10355
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