[Lldb-commits] [PATCH] [MIPS] Emulation of MIPS64 floating-point branch instructions

[Greg Clayton]

REPOSITORY
  rL LLVM

================
Comment at: source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp:640
@@ -639,2 +639,3 @@
 
-    m_disasm_ap.reset (new LLVMCDisassembler(triple, flavor, *this));
+    const char *cpu;
+    
----------------
Initialize this with "" for now and then remove the setting to "" in the default. Just in case someone later adds code and doesn't set cpu to something.

================
Comment at: source/Plugins/Process/Linux/NativeProcessLinux.cpp:3487-3505
@@ +3486,21 @@
+
+#if defined (__mips__)
+    /*
+     * The breakpoint might be in a delay slot. In this case PC points
+     * to the delayed branch instruction rather then the instruction
+     * in the delay slot. If the CAUSE.BD flag is set then adjust the 
+     * PC based on the size of the branch instruction.
+    */
+    const RegisterInfo *cause_reg_info = context_sp->GetRegisterInfoByName ("cause");
+    uint32_t cause = context_sp->ReadRegisterAsUnsigned (cause_reg_info, 0);
+    if ((!error.Success () || !breakpoint_sp) && (cause >> 31))
+    {
+        uint64_t branch_delay = 0;
+        if (log)
+            log->Printf ("NativeProcessLinux::%s MIPS cause register 0x%" PRIx32, __FUNCTION__, cause);
+        branch_delay = 4;   // FIXME - Adjust according to size of branch instruction at PC
+        breakpoint_addr = initial_pc_addr + branch_delay;
+        error = m_breakpoint_list.GetBreakpoint (breakpoint_addr, breakpoint_sp);
+    }
+#endif
+
----------------
This should probably be moved somewhere more generic so that this code doesn't get duplicated for each process plug-in.

http://reviews.llvm.org/D10355

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