[Lldb-commits] [PATCH] Fix breakpoint trap opcode detection for arm linux
Greg Clayton
clayborg at gmail.com
Fri Apr 10 10:18:52 PDT 2015
Looks good.
One thing to comment on: If you accidentally set an ARM breakpoint in thumb code you will hose your program by executing opcode 0x01f0:
ASR (immediate) (isa = T32, encoding = T2)
Arithmetic Shift Right (immediate)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
,---------------------------------------------------------------.
| 0 0 0 | 0 0 | 0 0 1 1 1 | 1 1 0 | 0 0 0 |
| | op | imm5 | Rn | Rd |
`---------------------------------------------------------------'
[12:11] op = 0 (0x0)
[10: 6] imm5 = 7 (0x7)
[ 5: 3] Rn = 6 (0x6)
[ 2: 0] Rd = 0 (0x0)
Followed by a branch for 0xE7F0:
B (isa = T32, encoding = T2)
Branch
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
,---------------------------------------------------------------.
| 1 1 1 0 0 | 1 1 1 1 1 1 1 0 0 0 0 |
| | imm11 |
`---------------------------------------------------------------'
[10: 0] imm11 = 2032 (0x7f0)
What we do is always try to use a 32 bit ARM instructions whose lower 16 bits would also trigger a Thumb breakpoint. If you look at the ARM opcode you are using:
UDF (isa = A32, encoding = A1)
Permanently Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
,-------------------------------------------------------------------------------------------------------------------------------.
| 1 1 1 0 0 1 1 1 1 1 1 1 | 0 0 0 0 0 0 0 0 0 0 0 1 | 1 1 1 1 | 0 0 0 0 |
| | imm12 | | imm4 |
`-------------------------------------------------------------------------------------------------------------------------------'
[19: 8] imm12 = 1 (0x1)
[ 3: 0] imm4 = 0 (0x0)
And the thumb breakpoint opcode you are using:
B (isa = T32, encoding = T1)
Permanently Undefined
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
,---------------------------------------------------------------.
| 1 1 0 1 | 1 1 1 0 | 0 0 0 0 0 0 0 1 |
| | cond | imm8 |
`---------------------------------------------------------------'
[11: 8] cond = 14 (0xe)
[ 7: 0] imm8 = 1 (0x1)
You can then play with the ARM instruction and modify the imm12 and imm4 so you can change to use 0xE7f0def1:
UDF (isa = A32, encoding = A1)
Permanently Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
,-------------------------------------------------------------------------------------------------------------------------------.
| 1 1 1 0 0 1 1 1 1 1 1 1 | 0 0 0 0 1 1 0 1 1 1 1 0 | 1 1 1 1 | 0 0 0 1 |
| | imm12 | | imm4 |
`-------------------------------------------------------------------------------------------------------------------------------'
[19: 8] imm12 = 222 (0xde)
[ 3: 0] imm4 = 1 (0x1)
And for Thumb use 0xdef1:
B (isa = T32, encoding = T1)
Branch
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
,---------------------------------------------------------------.
| 1 1 0 1 | 1 1 1 0 | 1 1 1 1 0 0 0 1 |
| | cond | imm8 |
`---------------------------------------------------------------'
[11: 8] cond = 14 (0xe)
[ 7: 0] imm8 = 241 (0xf1)
Now you have an ARM opcode that will mostly trigger a thumb breakpoint correctly even if you set it wrong. I say mostly because if you accidentally set the ARM breakpoint in the middle of a 32 bit Thumb instruction things could still go wrong.
http://reviews.llvm.org/D8975
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