[Lldb-commits] [lldb] r194302 - Fixed up registers in debugserver.
Greg Clayton
gclayton at apple.com
Fri Nov 8 16:33:47 PST 2013
Author: gclayton
Date: Fri Nov 8 18:33:46 2013
New Revision: 194302
URL: http://llvm.org/viewvc/llvm-project?rev=194302&view=rev
Log:
Fixed up registers in debugserver.
- removed all gaps from the g/G packets
- optimized registers for x86_64 to not send/receive xmm0-xmm15 as well as ymm0-ymm15, now we only send ymm0-15 and xmm0-15 are now pseudo regs
- Fixed x86_64 floating point register gaps
- Fixed x86_64 so that xmm8-xmm15 don't overlap with ymm0-ymm3. This could lead to bad values showing in the debugger and was due to bad register info structure contents
- Fixed i386 so we only send ymm0-ymm7 and xmm0-xmm7 are now pseudo regs.
- Fixed ARM register definitions to not have any gaps
- Fixed it so value registers and invalidation registers are specified using register names which avoid games we had to play with register numbering in the ARM plugin.
Modified:
lldb/trunk/tools/debugserver/source/DNBDefs.h
lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp
lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h
lldb/trunk/tools/debugserver/source/RNBRemote.cpp
lldb/trunk/tools/debugserver/source/RNBRemote.h
lldb/trunk/tools/debugserver/source/debugserver.cpp
Modified: lldb/trunk/tools/debugserver/source/DNBDefs.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/DNBDefs.h?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/DNBDefs.h (original)
+++ lldb/trunk/tools/debugserver/source/DNBDefs.h Fri Nov 8 18:33:46 2013
@@ -208,8 +208,8 @@ struct DNBRegisterInfo
uint32_t reg_dwarf; // DWARF register number (INVALID_NUB_REGNUM when none)
uint32_t reg_generic; // Generic register number (INVALID_NUB_REGNUM when none)
uint32_t reg_gdb; // The GDB register number (INVALID_NUB_REGNUM when none)
- uint32_t *pseudo_regs; // If this register is a part of another register, list the one or more registers
- uint32_t *update_regs; // If modifying this register will invalidate other registers, list them here
+ const char **value_regs; // If this register is a part of other registers, list the register names terminated by NULL
+ const char **update_regs; // If modifying this register will invalidate other registers, list the register names terminated by NULL
};
struct DNBRegisterSetInfo
Modified: lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp Fri Nov 8 18:33:46 2013
@@ -63,7 +63,7 @@
#define WATCHPOINT_OCCURRED ((uint32_t)(10u))
static const uint8_t g_arm_breakpoint_opcode[] = { 0xFE, 0xDE, 0xFF, 0xE7 };
-static const uint8_t g_thumb_breakpooint_opcode[] = { 0xFE, 0xDE };
+static const uint8_t g_thumb_breakpoint_opcode[] = { 0xFE, 0xDE };
// ARM constants used during decoding
#define REG_RD 0
@@ -126,7 +126,7 @@ DNBArchMachARM::SoftwareBreakpointOpcode
{
switch (byte_size)
{
- case 2: return g_thumb_breakpooint_opcode;
+ case 2: return g_thumb_breakpoint_opcode;
case 4: return g_arm_breakpoint_opcode;
}
return NULL;
@@ -260,7 +260,8 @@ static void
DumpDBGState(const DNBArchMachARM::DBG& dbg)
{
uint32_t i = 0;
- for (i=0; i<16; i++) {
+ for (i=0; i<16; i++)
+ {
DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
i, i, dbg.__bvr[i], dbg.__bcr[i],
i, i, dbg.__wvr[i], dbg.__wcr[i]);
@@ -481,7 +482,7 @@ DNBArchMachARM::StepNotComplete ()
{
if (m_state.context.gpr.__pc == m_hw_single_chained_step_addr)
{
- DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8x", m_hw_single_chained_step_addr);
+ DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8llx", (uint64_t) m_hw_single_chained_step_addr);
return true;
}
}
@@ -879,7 +880,8 @@ static uint32_t LoHi[16] = { 0 };
uint32_t
DNBArchMachARM::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task)
{
- DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint(addr = 0x%8.8llx, size = %llu, read = %u, write = %u)", (uint64_t)addr, (uint64_t)size, read, write);
+
+ DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint(addr = 0x%8.8llx, size = %zu, read = %u, write = %u)", (uint64_t)addr, size, read, write);
const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
@@ -1183,7 +1185,7 @@ enum gpr_regnums
enum
{
- vfp_s0 = 17, // match the g_gdb_register_map_arm table in RNBRemote.cpp
+ vfp_s0 = 0,
vfp_s1,
vfp_s2,
vfp_s3,
@@ -1214,12 +1216,8 @@ enum
vfp_s28,
vfp_s29,
vfp_s30,
- vfp_s31
-};
-
-enum
-{
- vfp_d0 = 49, // match the g_gdb_register_map_arm table in RNBRemote.cpp
+ vfp_s31,
+ vfp_d0,
vfp_d1,
vfp_d2,
vfp_d3,
@@ -1250,12 +1248,8 @@ enum
vfp_d28,
vfp_d29,
vfp_d30,
- vfp_d31
-};
-
-enum
-{
- vfp_q0 = 81, // match the g_gdb_register_map_arm table in RNBRemote.cpp
+ vfp_d31,
+ vfp_q0,
vfp_q1,
vfp_q2,
vfp_q3,
@@ -1298,15 +1292,7 @@ enum
// FIQ, SYS, USR, etc..), we should invalidate r8-r14 if the CPSR
// gets modified.
-uint32_t g_invalidate_cpsr[] = {
- gpr_r8,
- gpr_r9,
- gpr_r10,
- gpr_r11,
- gpr_r12,
- gpr_sp,
- gpr_lr,
- INVALID_NUB_REGNUM };
+const char * g_invalidate_cpsr[] = { "r8", "r9", "r10", "r11", "r12", "sp", "lr", NULL };
// General purpose registers
const DNBRegisterInfo
@@ -1331,39 +1317,39 @@ DNBArchMachARM::g_gpr_registers[] =
DEFINE_GPR_NAME (cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr)
};
-uint32_t g_contained_q0[] {vfp_q0, INVALID_NUB_REGNUM };
-uint32_t g_contained_q1[] {vfp_q1, INVALID_NUB_REGNUM };
-uint32_t g_contained_q2[] {vfp_q2, INVALID_NUB_REGNUM };
-uint32_t g_contained_q3[] {vfp_q3, INVALID_NUB_REGNUM };
-uint32_t g_contained_q4[] {vfp_q4, INVALID_NUB_REGNUM };
-uint32_t g_contained_q5[] {vfp_q5, INVALID_NUB_REGNUM };
-uint32_t g_contained_q6[] {vfp_q6, INVALID_NUB_REGNUM };
-uint32_t g_contained_q7[] {vfp_q7, INVALID_NUB_REGNUM };
-uint32_t g_contained_q8[] {vfp_q8, INVALID_NUB_REGNUM };
-uint32_t g_contained_q9[] {vfp_q9, INVALID_NUB_REGNUM };
-uint32_t g_contained_q10[] {vfp_q10, INVALID_NUB_REGNUM };
-uint32_t g_contained_q11[] {vfp_q11, INVALID_NUB_REGNUM };
-uint32_t g_contained_q12[] {vfp_q12, INVALID_NUB_REGNUM };
-uint32_t g_contained_q13[] {vfp_q13, INVALID_NUB_REGNUM };
-uint32_t g_contained_q14[] {vfp_q14, INVALID_NUB_REGNUM };
-uint32_t g_contained_q15[] {vfp_q15, INVALID_NUB_REGNUM };
-
-uint32_t g_invalidate_q0[] {vfp_q0, vfp_d0, vfp_d1, vfp_s0, vfp_s1, vfp_s2, vfp_s3, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q1[] {vfp_q1, vfp_d2, vfp_d3, vfp_s4, vfp_s5, vfp_s6, vfp_s7, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q2[] {vfp_q2, vfp_d4, vfp_d5, vfp_s8, vfp_s9, vfp_s10, vfp_s11, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q3[] {vfp_q3, vfp_d6, vfp_d7, vfp_s12, vfp_s13, vfp_s14, vfp_s15, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q4[] {vfp_q4, vfp_d8, vfp_d9, vfp_s16, vfp_s17, vfp_s18, vfp_s19, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q5[] {vfp_q5, vfp_d10, vfp_d11, vfp_s20, vfp_s21, vfp_s22, vfp_s23, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q6[] {vfp_q6, vfp_d12, vfp_d13, vfp_s24, vfp_s25, vfp_s26, vfp_s27, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q7[] {vfp_q7, vfp_d14, vfp_d15, vfp_s28, vfp_s29, vfp_s30, vfp_s31, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q8[] {vfp_q8, vfp_d16, vfp_d17, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q9[] {vfp_q9, vfp_d18, vfp_d19, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q10[] {vfp_q10, vfp_d20, vfp_d21, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q11[] {vfp_q11, vfp_d22, vfp_d23, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q12[] {vfp_q12, vfp_d24, vfp_d25, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q13[] {vfp_q13, vfp_d26, vfp_d27, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q14[] {vfp_q14, vfp_d28, vfp_d29, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_q15[] {vfp_q15, vfp_d30, vfp_d31, INVALID_NUB_REGNUM };
+const char *g_contained_q0 [] { "q0", NULL };
+const char *g_contained_q1 [] { "q1", NULL };
+const char *g_contained_q2 [] { "q2", NULL };
+const char *g_contained_q3 [] { "q3", NULL };
+const char *g_contained_q4 [] { "q4", NULL };
+const char *g_contained_q5 [] { "q5", NULL };
+const char *g_contained_q6 [] { "q6", NULL };
+const char *g_contained_q7 [] { "q7", NULL };
+const char *g_contained_q8 [] { "q8", NULL };
+const char *g_contained_q9 [] { "q9", NULL };
+const char *g_contained_q10[] { "q10", NULL };
+const char *g_contained_q11[] { "q11", NULL };
+const char *g_contained_q12[] { "q12", NULL };
+const char *g_contained_q13[] { "q13", NULL };
+const char *g_contained_q14[] { "q14", NULL };
+const char *g_contained_q15[] { "q15", NULL };
+
+const char *g_invalidate_q0[] { "q0", "d0" , "d1" , "s0" , "s1" , "s2" , "s3" , NULL };
+const char *g_invalidate_q1[] { "q1", "d2" , "d3" , "s4" , "s5" , "s6" , "s7" , NULL };
+const char *g_invalidate_q2[] { "q2", "d4" , "d5" , "s8" , "s9" , "s10", "s11", NULL };
+const char *g_invalidate_q3[] { "q3", "d6" , "d7" , "s12", "s13", "s14", "s15", NULL };
+const char *g_invalidate_q4[] { "q4", "d8" , "d9" , "s16", "s17", "s18", "s19", NULL };
+const char *g_invalidate_q5[] { "q5", "d10", "d11", "s20", "s21", "s22", "s23", NULL };
+const char *g_invalidate_q6[] { "q6", "d12", "d13", "s24", "s25", "s26", "s27", NULL };
+const char *g_invalidate_q7[] { "q7", "d14", "d15", "s28", "s29", "s30", "s31", NULL };
+const char *g_invalidate_q8[] { "q8", "d16", "d17", NULL };
+const char *g_invalidate_q9[] { "q9", "d18", "d19", NULL };
+const char *g_invalidate_q10[] { "q10", "d20", "d21", NULL };
+const char *g_invalidate_q11[] { "q11", "d22", "d23", NULL };
+const char *g_invalidate_q12[] { "q12", "d24", "d25", NULL };
+const char *g_invalidate_q13[] { "q13", "d26", "d27", NULL };
+const char *g_invalidate_q14[] { "q14", "d28", "d29", NULL };
+const char *g_invalidate_q15[] { "q15", "d30", "d31", NULL };
#define VFP_S_OFFSET_IDX(idx) (offsetof (DNBArchMachARM::FPU, __r[(idx)]) + offsetof (DNBArchMachARM::Context, vfp))
#define VFP_D_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX ((idx) * 2))
@@ -1373,9 +1359,9 @@ uint32_t g_invalidate_q15[] {vfp_q15, v
#define FLOAT_FORMAT Float
-#define DEFINE_VFP_S_IDX(idx) e_regSetVFP, vfp_s##idx - vfp_s0, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
-#define DEFINE_VFP_D_IDX(idx) e_regSetVFP, vfp_d##idx - vfp_s0, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
-#define DEFINE_VFP_Q_IDX(idx) e_regSetVFP, vfp_q##idx - vfp_s0, "q" #idx, NULL, Vector, VectorOfUInt8, 16, VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
+#define DEFINE_VFP_S_IDX(idx) e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, 0, INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
+#define DEFINE_VFP_D_IDX(idx) e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, 0, INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
+#define DEFINE_VFP_Q_IDX(idx) e_regSetVFP, vfp_q##idx, "q" #idx, NULL, Vector, VectorOfUInt8, 16, VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
// Floating point registers
const DNBRegisterInfo
@@ -1565,10 +1551,9 @@ DNBArchMachARM::GetRegisterValue(int set
// "reg" is an index into the floating point register set at this point.
// We need to translate it up so entry 0 in the fp reg set is the same as vfp_s0
// in the enumerated values for case statement below.
- reg += vfp_s0;
if (reg >= vfp_s0 && reg <= vfp_s31)
{
- value->value.uint32 = m_state.context.vfp.__r[reg - vfp_s0];
+ value->value.uint32 = m_state.context.vfp.__r[reg];
return true;
}
else if (reg >= vfp_d0 && reg <= vfp_d31)
@@ -1585,7 +1570,6 @@ DNBArchMachARM::GetRegisterValue(int set
memcpy (&value->value.v_uint8, (uint8_t *) &m_state.context.vfp.__r[s_reg_idx], 16);
return true;
}
-
else if (reg == vfp_fpscr)
{
value->value.uint32 = m_state.context.vfp.__fpscr;
@@ -1663,11 +1647,9 @@ DNBArchMachARM::SetRegisterValue(int set
// "reg" is an index into the floating point register set at this point.
// We need to translate it up so entry 0 in the fp reg set is the same as vfp_s0
// in the enumerated values for case statement below.
- reg += vfp_s0;
-
if (reg >= vfp_s0 && reg <= vfp_s31)
{
- m_state.context.vfp.__r[reg - vfp_s0] = value->value.uint32;
+ m_state.context.vfp.__r[reg] = value->value.uint32;
success = true;
}
else if (reg >= vfp_d0 && reg <= vfp_d31)
@@ -1757,7 +1739,9 @@ DNBArchMachARM::RegisterSetStateIsValid
nub_size_t
DNBArchMachARM::GetRegisterContext (void *buf, nub_size_t buf_len)
{
- nub_size_t size = sizeof (m_state.context);
+ nub_size_t size = sizeof (m_state.context.gpr) +
+ sizeof (m_state.context.vfp) +
+ sizeof (m_state.context.exc);
if (buf && buf_len)
{
@@ -1767,7 +1751,19 @@ DNBArchMachARM::GetRegisterContext (void
bool force = false;
if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
return 0;
- ::memcpy (buf, &m_state.context, size);
+
+ // Copy each struct individually to avoid any padding that might be between the structs in m_state.context
+ uint8_t *p = (uint8_t *)buf;
+ ::memcpy (p, &m_state.context.gpr, sizeof(m_state.context.gpr));
+ p += sizeof(m_state.context.gpr);
+ ::memcpy (p, &m_state.context.vfp, sizeof(m_state.context.vfp));
+ p += sizeof(m_state.context.vfp);
+ ::memcpy (p, &m_state.context.exc, sizeof(m_state.context.exc));
+ p += sizeof(m_state.context.exc);
+
+ size_t bytes_written = p - (uint8_t *)buf;
+ assert (bytes_written == size);
+
}
DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::GetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
// Return the size of the register context even if NULL was passed in
@@ -1777,7 +1773,10 @@ DNBArchMachARM::GetRegisterContext (void
nub_size_t
DNBArchMachARM::SetRegisterContext (const void *buf, nub_size_t buf_len)
{
- nub_size_t size = sizeof (m_state.context);
+ nub_size_t size = sizeof (m_state.context.gpr) +
+ sizeof (m_state.context.vfp) +
+ sizeof (m_state.context.exc);
+
if (buf == NULL || buf_len == 0)
size = 0;
@@ -1786,10 +1785,20 @@ DNBArchMachARM::SetRegisterContext (cons
if (size > buf_len)
size = buf_len;
- ::memcpy (&m_state.context, buf, size);
- SetGPRState();
- SetVFPState();
- SetEXCState();
+ // Copy each struct individually to avoid any padding that might be between the structs in m_state.context
+ uint8_t *p = (uint8_t *)buf;
+ ::memcpy (&m_state.context.gpr, p, sizeof(m_state.context.gpr));
+ p += sizeof(m_state.context.gpr);
+ ::memcpy (&m_state.context.vfp, p, sizeof(m_state.context.vfp));
+ p += sizeof(m_state.context.vfp);
+ ::memcpy (&m_state.context.exc, p, sizeof(m_state.context.exc));
+ p += sizeof(m_state.context.exc);
+
+ size_t bytes_written = p - (uint8_t *)buf;
+ assert (bytes_written == size);
+
+ if (SetGPRState() | SetVFPState() | SetEXCState())
+ return 0;
}
DNBLogThreadedIf (LOG_THREAD, "DNBArchMachARM::SetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
return size;
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp Fri Nov 8 18:33:46 2013
@@ -1011,9 +1011,9 @@ DNBArchImplI386::EnableHardwareSingleSte
// Register information defintions
//----------------------------------------------------------------------
-#define DEFINE_GPR_PSEUDO_16(reg16,reg32) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, GPR_OFFSET(reg32) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
-#define DEFINE_GPR_PSEUDO_8H(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, GPR_OFFSET(reg32)+1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
-#define DEFINE_GPR_PSEUDO_8L(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, GPR_OFFSET(reg32) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
+#define DEFINE_GPR_PSEUDO_16(reg16,reg32) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
+#define DEFINE_GPR_PSEUDO_8H(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
+#define DEFINE_GPR_PSEUDO_8L(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg32, g_invalidate_##reg32 }
#define GPR_OFFSET(reg) (offsetof (DNBArchImplI386::GPR, __##reg))
@@ -1040,23 +1040,23 @@ DNBArchImplI386::EnableHardwareSingleSte
// the register state structures are defined correctly and have the correct
// sizes and offsets.
-uint32_t g_contained_eax[] = { gpr_eax, INVALID_NUB_REGNUM };
-uint32_t g_contained_ebx[] = { gpr_ebx, INVALID_NUB_REGNUM };
-uint32_t g_contained_ecx[] = { gpr_ecx, INVALID_NUB_REGNUM };
-uint32_t g_contained_edx[] = { gpr_edx, INVALID_NUB_REGNUM };
-uint32_t g_contained_edi[] = { gpr_edi, INVALID_NUB_REGNUM };
-uint32_t g_contained_esi[] = { gpr_esi, INVALID_NUB_REGNUM };
-uint32_t g_contained_ebp[] = { gpr_ebp, INVALID_NUB_REGNUM };
-uint32_t g_contained_esp[] = { gpr_esp, INVALID_NUB_REGNUM };
-
-uint32_t g_invalidate_eax[] = { gpr_eax , gpr_ax , gpr_ah , gpr_al, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_ebx[] = { gpr_ebx , gpr_bx , gpr_bh , gpr_bl, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_ecx[] = { gpr_ecx , gpr_cx , gpr_ch , gpr_cl, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_edx[] = { gpr_edx , gpr_dx , gpr_dh , gpr_dl, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_edi[] = { gpr_edi , gpr_di , gpr_dil , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_esi[] = { gpr_esi , gpr_si , gpr_sil , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_ebp[] = { gpr_ebp , gpr_bp , gpr_bpl , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_esp[] = { gpr_esp , gpr_sp , gpr_spl , INVALID_NUB_REGNUM };
+const char * g_contained_eax[] = { "eax", NULL };
+const char * g_contained_ebx[] = { "ebx", NULL };
+const char * g_contained_ecx[] = { "ecx", NULL };
+const char * g_contained_edx[] = { "edx", NULL };
+const char * g_contained_edi[] = { "edi", NULL };
+const char * g_contained_esi[] = { "esi", NULL };
+const char * g_contained_ebp[] = { "ebp", NULL };
+const char * g_contained_esp[] = { "esp", NULL };
+
+const char * g_invalidate_eax[] = { "eax", "ax", "ah", "al", NULL };
+const char * g_invalidate_ebx[] = { "ebx", "bx", "bh", "bl", NULL };
+const char * g_invalidate_ecx[] = { "ecx", "cx", "ch", "cl", NULL };
+const char * g_invalidate_edx[] = { "edx", "dx", "dh", "dl", NULL };
+const char * g_invalidate_edi[] = { "edi", "di", "dil", NULL };
+const char * g_invalidate_esi[] = { "esi", "si", "sil", NULL };
+const char * g_invalidate_ebp[] = { "ebp", "bp", "bpl", NULL };
+const char * g_invalidate_esp[] = { "esp", "sp", "spl", NULL };
// General purpose registers for 64 bit
const DNBRegisterInfo
@@ -1134,6 +1134,17 @@ DNBArchImplI386::g_fpu_registers_no_avx[
{ e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7), FPU_OFFSET(xmm7), INVALID_NUB_REGNUM, dwarf_xmm7, INVALID_NUB_REGNUM, gdb_xmm7, NULL, NULL }
};
+
+static const char *g_contained_ymm0 [] = { "ymm0", NULL };
+static const char *g_contained_ymm1 [] = { "ymm1", NULL };
+static const char *g_contained_ymm2 [] = { "ymm2", NULL };
+static const char *g_contained_ymm3 [] = { "ymm3", NULL };
+static const char *g_contained_ymm4 [] = { "ymm4", NULL };
+static const char *g_contained_ymm5 [] = { "ymm5", NULL };
+static const char *g_contained_ymm6 [] = { "ymm6", NULL };
+static const char *g_contained_ymm7 [] = { "ymm7", NULL };
+
+
const DNBRegisterInfo
DNBArchImplI386::g_fpu_registers_avx[] =
{
@@ -1157,15 +1168,6 @@ DNBArchImplI386::g_fpu_registers_avx[] =
{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6, INVALID_NUB_REGNUM, gdb_stmm6, NULL, NULL },
{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7, INVALID_NUB_REGNUM, gdb_stmm7, NULL, NULL },
-{ e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0), AVX_OFFSET(xmm0), INVALID_NUB_REGNUM, dwarf_xmm0, INVALID_NUB_REGNUM, gdb_xmm0, NULL, NULL },
-{ e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1), AVX_OFFSET(xmm1), INVALID_NUB_REGNUM, dwarf_xmm1, INVALID_NUB_REGNUM, gdb_xmm1, NULL, NULL },
-{ e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2), AVX_OFFSET(xmm2), INVALID_NUB_REGNUM, dwarf_xmm2, INVALID_NUB_REGNUM, gdb_xmm2, NULL, NULL },
-{ e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3), AVX_OFFSET(xmm3), INVALID_NUB_REGNUM, dwarf_xmm3, INVALID_NUB_REGNUM, gdb_xmm3, NULL, NULL },
-{ e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4), AVX_OFFSET(xmm4), INVALID_NUB_REGNUM, dwarf_xmm4, INVALID_NUB_REGNUM, gdb_xmm4, NULL, NULL },
-{ e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5), AVX_OFFSET(xmm5), INVALID_NUB_REGNUM, dwarf_xmm5, INVALID_NUB_REGNUM, gdb_xmm5, NULL, NULL },
-{ e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6), AVX_OFFSET(xmm6), INVALID_NUB_REGNUM, dwarf_xmm6, INVALID_NUB_REGNUM, gdb_xmm6, NULL, NULL },
-{ e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7), AVX_OFFSET(xmm7), INVALID_NUB_REGNUM, dwarf_xmm7, INVALID_NUB_REGNUM, gdb_xmm7, NULL, NULL },
-
{ e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0), AVX_OFFSET_YMM(0), INVALID_NUB_REGNUM, dwarf_ymm0, INVALID_NUB_REGNUM, gdb_ymm0, NULL, NULL },
{ e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1), AVX_OFFSET_YMM(1), INVALID_NUB_REGNUM, dwarf_ymm1, INVALID_NUB_REGNUM, gdb_ymm1, NULL, NULL },
{ e_regSetFPU, fpu_ymm2, "ymm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2), AVX_OFFSET_YMM(2), INVALID_NUB_REGNUM, dwarf_ymm2, INVALID_NUB_REGNUM, gdb_ymm2, NULL, NULL },
@@ -1173,7 +1175,17 @@ DNBArchImplI386::g_fpu_registers_avx[] =
{ e_regSetFPU, fpu_ymm4, "ymm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4), AVX_OFFSET_YMM(4), INVALID_NUB_REGNUM, dwarf_ymm4, INVALID_NUB_REGNUM, gdb_ymm4, NULL, NULL },
{ e_regSetFPU, fpu_ymm5, "ymm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5), AVX_OFFSET_YMM(5), INVALID_NUB_REGNUM, dwarf_ymm5, INVALID_NUB_REGNUM, gdb_ymm5, NULL, NULL },
{ e_regSetFPU, fpu_ymm6, "ymm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6), AVX_OFFSET_YMM(6), INVALID_NUB_REGNUM, dwarf_ymm6, INVALID_NUB_REGNUM, gdb_ymm6, NULL, NULL },
-{ e_regSetFPU, fpu_ymm7, "ymm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7), AVX_OFFSET_YMM(7), INVALID_NUB_REGNUM, dwarf_ymm7, INVALID_NUB_REGNUM, gdb_ymm7, NULL, NULL }
+{ e_regSetFPU, fpu_ymm7, "ymm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7), AVX_OFFSET_YMM(7), INVALID_NUB_REGNUM, dwarf_ymm7, INVALID_NUB_REGNUM, gdb_ymm7, NULL, NULL },
+
+{ e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0), 0, INVALID_NUB_REGNUM, dwarf_xmm0, INVALID_NUB_REGNUM, gdb_xmm0, g_contained_ymm0, NULL },
+{ e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1), 0, INVALID_NUB_REGNUM, dwarf_xmm1, INVALID_NUB_REGNUM, gdb_xmm1, g_contained_ymm1, NULL },
+{ e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2), 0, INVALID_NUB_REGNUM, dwarf_xmm2, INVALID_NUB_REGNUM, gdb_xmm2, g_contained_ymm2, NULL },
+{ e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3), 0, INVALID_NUB_REGNUM, dwarf_xmm3, INVALID_NUB_REGNUM, gdb_xmm3, g_contained_ymm3, NULL },
+{ e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4), 0, INVALID_NUB_REGNUM, dwarf_xmm4, INVALID_NUB_REGNUM, gdb_xmm4, g_contained_ymm4, NULL },
+{ e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5), 0, INVALID_NUB_REGNUM, dwarf_xmm5, INVALID_NUB_REGNUM, gdb_xmm5, g_contained_ymm5, NULL },
+{ e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6), 0, INVALID_NUB_REGNUM, dwarf_xmm6, INVALID_NUB_REGNUM, gdb_xmm6, g_contained_ymm6, NULL },
+{ e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7), 0, INVALID_NUB_REGNUM, dwarf_xmm7, INVALID_NUB_REGNUM, gdb_xmm7, g_contained_ymm7, NULL },
+
};
const DNBRegisterInfo
@@ -1557,10 +1569,41 @@ DNBArchImplI386::SetRegisterValue(int se
}
+uint32_t
+DNBArchImplI386::GetRegisterContextSize()
+{
+ static uint32_t g_cached_size = 0;
+ if (g_cached_size == 0)
+ {
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ {
+ for (size_t i=0; i<k_num_fpu_registers_avx; ++i)
+ {
+ if (g_fpu_registers_avx[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_avx[i].size;
+ }
+ }
+ else
+ {
+ for (size_t i=0; i<k_num_fpu_registers_no_avx; ++i)
+ {
+ if (g_fpu_registers_no_avx[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_no_avx[i].size;
+ }
+ }
+ DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR = %zu, FPU = %u, EXC = %zu", sizeof(GPR), g_cached_size, sizeof(EXC));
+ g_cached_size += sizeof(GPR);
+ g_cached_size += sizeof(EXC);
+ DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR + FPU + EXC = %u", g_cached_size);
+ }
+ return g_cached_size;
+}
+
+
nub_size_t
DNBArchImplI386::GetRegisterContext (void *buf, nub_size_t buf_len)
{
- nub_size_t size = sizeof (m_state.context);
+ uint32_t size = GetRegisterContextSize();
if (buf && buf_len)
{
@@ -1586,8 +1629,72 @@ DNBArchImplI386::GetRegisterContext (voi
}
else
{
- // Success
- ::memcpy (buf, &m_state.context, size);
+ uint8_t *p = (uint8_t *)buf;
+ // Copy the GPR registers
+ memcpy(p, &m_state.context.gpr, sizeof(GPR));
+ p += sizeof(GPR);
+
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ {
+ // Walk around the gaps in the FPU regs
+ memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5);
+ p += 5;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8);
+ p += 8;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6);
+ p += 6;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10);
+ p += 10;
+ }
+
+ // Interleave the XMM and YMMH registers to make the YMM registers
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16);
+ p += 16;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16);
+ p += 16;
+ }
+ }
+ else
+ {
+ // Walk around the gaps in the FPU regs
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
+ p += 5;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
+ p += 8;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
+ p += 6;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
+ p += 10;
+ }
+
+ // Copy the XMM registers in a single block
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 8 * 16);
+ p += 8 * 16;
+ }
+
+ // Copy the exception registers
+ memcpy(p, &m_state.context.exc, sizeof(EXC));
+ p += sizeof(EXC);
+
+ // make sure we end up with exactly what we think we should have
+ size_t bytes_written = p - (uint8_t *)buf;
+ assert (bytes_written == size);
}
}
DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::GetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
@@ -1607,7 +1714,72 @@ DNBArchImplI386::SetRegisterContext (con
if (size > buf_len)
size = buf_len;
- ::memcpy (&m_state.context, buf, size);
+ uint8_t *p = (uint8_t *)buf;
+ // Copy the GPR registers
+ memcpy(&m_state.context.gpr, p, sizeof(GPR));
+ p += sizeof(GPR);
+
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ {
+ // Walk around the gaps in the FPU regs
+ memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5);
+ p += 5;
+ memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8);
+ p += 8;
+ memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6);
+ p += 6;
+ memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10);
+ p += 10;
+ }
+
+ // Interleave the XMM and YMMH registers to make the YMM registers
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16);
+ p += 16;
+ memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16);
+ p += 16;
+ }
+ }
+ else
+ {
+ // Copy fcw through mxcsrmask as there is no padding
+ memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
+ p += 5;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
+ p += 8;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
+ p += 6;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
+ p += 10;
+ }
+
+ // Copy the XMM registers in a single block
+ memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 8 * 16);
+ p += 8 * 16;
+ }
+
+ // Copy the exception registers
+ memcpy(&m_state.context.exc, p, sizeof(EXC));
+ p += sizeof(EXC);
+
+ // make sure we end up with exactly what we think we should have
+ size_t bytes_written = p - (uint8_t *)buf;
+ assert (bytes_written == size);
kern_return_t kret;
if ((kret = SetGPRState()) != KERN_SUCCESS)
DNBLogThreadedIf (LOG_THREAD, "DNBArchImplI386::SetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to write: %u", buf, (uint64_t)buf_len, kret);
Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h Fri Nov 8 18:33:46 2013
@@ -220,6 +220,9 @@ protected:
static const DNBRegisterSetInfo *
GetRegisterSetInfo(nub_size_t *num_reg_sets);
+ static uint32_t
+ GetRegisterContextSize();
+
// Helper functions for watchpoint manipulations.
static void SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write);
static void ClearWatchpoint(DBG &debug_state, uint32_t hw_index);
Modified: lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp Fri Nov 8 18:33:46 2013
@@ -270,9 +270,9 @@ DNBArchImplX86_64::GetFPUState(bool forc
m_state.context.fpu.avx.__fpu_fop = 2;
m_state.context.fpu.avx.__fpu_ip = 3;
m_state.context.fpu.avx.__fpu_cs = 4;
- m_state.context.fpu.avx.__fpu_rsrv2 = 5;
- m_state.context.fpu.avx.__fpu_dp = 6;
- m_state.context.fpu.avx.__fpu_ds = 7;
+ m_state.context.fpu.avx.__fpu_rsrv2 = UINT8_MAX;
+ m_state.context.fpu.avx.__fpu_dp = 5;
+ m_state.context.fpu.avx.__fpu_ds = 6;
m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
m_state.context.fpu.avx.__fpu_mxcsr = 8;
m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
@@ -302,39 +302,39 @@ DNBArchImplX86_64::GetFPUState(bool forc
m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
}
- m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
- m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
- m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
- m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
- m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
- m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
- m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
- m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
- m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8';
- m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9';
- m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A';
- m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B';
- m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C';
- m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D';
- m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E';
- m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F';
+ m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E' + 2 * i;
+ m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F' + 2 * i;
- m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
- m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
- m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
- m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
- m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
- m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
- m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
- m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
- m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8';
- m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9';
- m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A';
- m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B';
- m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C';
- m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D';
- m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E';
- m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F';
+ m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0' + i;
+ m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1' + i;
+ m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2' + i;
+ m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3' + i;
+ m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4' + i;
+ m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5' + i;
+ m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6' + i;
+ m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7' + i;
+ m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8' + i;
+ m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9' + i;
+ m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A' + i;
+ m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B' + i;
+ m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C' + i;
+ m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D' + i;
+ m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E' + i;
+ m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F' + i;
}
for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
@@ -1256,13 +1256,7 @@ enum gdb_regnums
#define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx))
#define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx))
#define EXC_OFFSET(reg) (offsetof (DNBArchImplX86_64::EXC, __##reg) + offsetof (DNBArchImplX86_64::Context, exc))
-
-// This does not accurately identify the location of ymm0...7 in
-// Context.fpu.avx. That is because there is a bunch of padding
-// in Context.fpu.avx that we don't need. Offset macros lay out
-// the register state that Debugserver transmits to the debugger
-// -- not to interpret the thread_get_state info.
-#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n))
+#define AVX_OFFSET_YMM(n) (AVX_OFFSET(ymmh0) + (32 * n))
#define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg))
#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg))
@@ -1281,46 +1275,46 @@ enum gdb_regnums
#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg, NULL, NULL }
#define DEFINE_GPR_ALT4(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg, NULL, NULL }
-#define DEFINE_GPR_PSEUDO_32(reg32,reg64) { e_regSetGPR, gpr_##reg32, #reg32, NULL, Uint, Hex, 4, GPR_OFFSET(reg64) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
-#define DEFINE_GPR_PSEUDO_16(reg16,reg64) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, GPR_OFFSET(reg64) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
-#define DEFINE_GPR_PSEUDO_8H(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, GPR_OFFSET(reg64)+1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
-#define DEFINE_GPR_PSEUDO_8L(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, GPR_OFFSET(reg64) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
+#define DEFINE_GPR_PSEUDO_32(reg32,reg64) { e_regSetGPR, gpr_##reg32, #reg32, NULL, Uint, Hex, 4, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
+#define DEFINE_GPR_PSEUDO_16(reg16,reg64) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
+#define DEFINE_GPR_PSEUDO_8H(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
+#define DEFINE_GPR_PSEUDO_8L(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
// General purpose registers for 64 bit
-uint32_t g_contained_rax[] = { gpr_rax, INVALID_NUB_REGNUM };
-uint32_t g_contained_rbx[] = { gpr_rbx, INVALID_NUB_REGNUM };
-uint32_t g_contained_rcx[] = { gpr_rcx, INVALID_NUB_REGNUM };
-uint32_t g_contained_rdx[] = { gpr_rdx, INVALID_NUB_REGNUM };
-uint32_t g_contained_rdi[] = { gpr_rdi, INVALID_NUB_REGNUM };
-uint32_t g_contained_rsi[] = { gpr_rsi, INVALID_NUB_REGNUM };
-uint32_t g_contained_rbp[] = { gpr_rbp, INVALID_NUB_REGNUM };
-uint32_t g_contained_rsp[] = { gpr_rsp, INVALID_NUB_REGNUM };
-uint32_t g_contained_r8[] = { gpr_r8 , INVALID_NUB_REGNUM };
-uint32_t g_contained_r9[] = { gpr_r9 , INVALID_NUB_REGNUM };
-uint32_t g_contained_r10[] = { gpr_r10, INVALID_NUB_REGNUM };
-uint32_t g_contained_r11[] = { gpr_r11, INVALID_NUB_REGNUM };
-uint32_t g_contained_r12[] = { gpr_r12, INVALID_NUB_REGNUM };
-uint32_t g_contained_r13[] = { gpr_r13, INVALID_NUB_REGNUM };
-uint32_t g_contained_r14[] = { gpr_r14, INVALID_NUB_REGNUM };
-uint32_t g_contained_r15[] = { gpr_r15, INVALID_NUB_REGNUM };
-
-uint32_t g_invalidate_rax[] = { gpr_rax, gpr_eax , gpr_ax , gpr_ah , gpr_al, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rbx[] = { gpr_rbx, gpr_ebx , gpr_bx , gpr_bh , gpr_bl, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rcx[] = { gpr_rcx, gpr_ecx , gpr_cx , gpr_ch , gpr_cl, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rdx[] = { gpr_rdx, gpr_edx , gpr_dx , gpr_dh , gpr_dl, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rdi[] = { gpr_rdi, gpr_edi , gpr_di , gpr_dil , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rsi[] = { gpr_rsi, gpr_esi , gpr_si , gpr_sil , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rbp[] = { gpr_rbp, gpr_ebp , gpr_bp , gpr_bpl , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_rsp[] = { gpr_rsp, gpr_esp , gpr_sp , gpr_spl , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r8 [] = { gpr_r8 , gpr_r8d , gpr_r8w , gpr_r8l , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r9 [] = { gpr_r9 , gpr_r9d , gpr_r9w , gpr_r9l , INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r10[] = { gpr_r10, gpr_r10d, gpr_r10w, gpr_r10l, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r11[] = { gpr_r11, gpr_r11d, gpr_r11w, gpr_r11l, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r12[] = { gpr_r12, gpr_r12d, gpr_r12w, gpr_r12l, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r13[] = { gpr_r13, gpr_r13d, gpr_r13w, gpr_r13l, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r14[] = { gpr_r14, gpr_r14d, gpr_r14w, gpr_r14l, INVALID_NUB_REGNUM };
-uint32_t g_invalidate_r15[] = { gpr_r15, gpr_r15d, gpr_r15w, gpr_r15l, INVALID_NUB_REGNUM };
+const char *g_contained_rax[] = { "rax", NULL };
+const char *g_contained_rbx[] = { "rbx", NULL };
+const char *g_contained_rcx[] = { "rcx", NULL };
+const char *g_contained_rdx[] = { "rdx", NULL };
+const char *g_contained_rdi[] = { "rdi", NULL };
+const char *g_contained_rsi[] = { "rsi", NULL };
+const char *g_contained_rbp[] = { "rbp", NULL };
+const char *g_contained_rsp[] = { "rsp", NULL };
+const char *g_contained_r8[] = { "r8", NULL };
+const char *g_contained_r9[] = { "r9", NULL };
+const char *g_contained_r10[] = { "r10", NULL };
+const char *g_contained_r11[] = { "r11", NULL };
+const char *g_contained_r12[] = { "r12", NULL };
+const char *g_contained_r13[] = { "r13", NULL };
+const char *g_contained_r14[] = { "r14", NULL };
+const char *g_contained_r15[] = { "r15", NULL };
+
+const char *g_invalidate_rax[] = { "rax", "eax", "ax", "ah", "al", NULL };
+const char *g_invalidate_rbx[] = { "rbx", "ebx", "bx", "bh", "bl", NULL };
+const char *g_invalidate_rcx[] = { "rcx", "ecx", "cx", "ch", "cl", NULL };
+const char *g_invalidate_rdx[] = { "rdx", "edx", "dx", "dh", "dl", NULL };
+const char *g_invalidate_rdi[] = { "rdi", "edi", "di", "dil", NULL };
+const char *g_invalidate_rsi[] = { "rsi", "esi", "si", "sil", NULL };
+const char *g_invalidate_rbp[] = { "rbp", "ebp", "bp", "bpl", NULL };
+const char *g_invalidate_rsp[] = { "rsp", "esp", "sp", "spl", NULL };
+const char *g_invalidate_r8 [] = { "r8", "r8d", "r8w", "r8l", NULL };
+const char *g_invalidate_r9 [] = { "r9", "r9d", "r9w", "r9l", NULL };
+const char *g_invalidate_r10[] = { "r10", "r10d", "r10w", "r10l", NULL };
+const char *g_invalidate_r11[] = { "r11", "r11d", "r11w", "r11l", NULL };
+const char *g_invalidate_r12[] = { "r12", "r12d", "r12w", "r12l", NULL };
+const char *g_invalidate_r13[] = { "r13", "r13d", "r13w", "r13l", NULL };
+const char *g_invalidate_r14[] = { "r14", "r14d", "r14w", "r14l", NULL };
+const char *g_invalidate_r15[] = { "r15", "r15d", "r15w", "r15l", NULL };
const DNBRegisterInfo
DNBArchImplX86_64::g_gpr_registers[] =
@@ -1442,6 +1436,23 @@ DNBArchImplX86_64::g_fpu_registers_no_av
{ e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, NULL, NULL },
};
+static const char *g_contained_ymm0 [] = { "ymm0", NULL };
+static const char *g_contained_ymm1 [] = { "ymm1", NULL };
+static const char *g_contained_ymm2 [] = { "ymm2", NULL };
+static const char *g_contained_ymm3 [] = { "ymm3", NULL };
+static const char *g_contained_ymm4 [] = { "ymm4", NULL };
+static const char *g_contained_ymm5 [] = { "ymm5", NULL };
+static const char *g_contained_ymm6 [] = { "ymm6", NULL };
+static const char *g_contained_ymm7 [] = { "ymm7", NULL };
+static const char *g_contained_ymm8 [] = { "ymm8", NULL };
+static const char *g_contained_ymm9 [] = { "ymm9", NULL };
+static const char *g_contained_ymm10[] = { "ymm10", NULL };
+static const char *g_contained_ymm11[] = { "ymm11", NULL };
+static const char *g_contained_ymm12[] = { "ymm12", NULL };
+static const char *g_contained_ymm13[] = { "ymm13", NULL };
+static const char *g_contained_ymm14[] = { "ymm14", NULL };
+static const char *g_contained_ymm15[] = { "ymm15", NULL };
+
const DNBRegisterInfo
DNBArchImplX86_64::g_fpu_registers_avx[] =
{
@@ -1465,23 +1476,6 @@ DNBArchImplX86_64::g_fpu_registers_avx[]
{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6, NULL, NULL },
{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7, NULL, NULL },
- { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 , NULL, NULL },
- { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 , NULL, NULL },
- { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 , NULL, NULL },
- { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 , NULL, NULL },
- { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 , NULL, NULL },
- { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 , NULL, NULL },
- { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 , NULL, NULL },
- { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 , NULL, NULL },
- { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 , NULL, NULL },
- { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 , NULL, NULL },
- { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10, NULL, NULL },
- { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11, NULL, NULL },
- { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12, NULL, NULL },
- { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13, NULL, NULL },
- { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14, NULL, NULL },
- { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, NULL, NULL },
-
{ e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1U, gdb_ymm0, NULL, NULL },
{ e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1U, gdb_ymm1, NULL, NULL },
{ e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1U, gdb_ymm2, NULL, NULL },
@@ -1497,7 +1491,26 @@ DNBArchImplX86_64::g_fpu_registers_avx[]
{ e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1U, gdb_ymm12, NULL, NULL },
{ e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1U, gdb_ymm13, NULL, NULL },
{ e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1U, gdb_ymm14, NULL, NULL },
- { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1U, gdb_ymm15, NULL, NULL }
+ { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1U, gdb_ymm15, NULL, NULL },
+
+ { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , 0, gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 , g_contained_ymm0 , NULL },
+ { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , 0, gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 , g_contained_ymm1 , NULL },
+ { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , 0, gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 , g_contained_ymm2 , NULL },
+ { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , 0, gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 , g_contained_ymm3 , NULL },
+ { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , 0, gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 , g_contained_ymm4 , NULL },
+ { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , 0, gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 , g_contained_ymm5 , NULL },
+ { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , 0, gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 , g_contained_ymm6 , NULL },
+ { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , 0, gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 , g_contained_ymm7 , NULL },
+ { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , 0, gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 , g_contained_ymm8 , NULL },
+ { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , 0, gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 , g_contained_ymm9 , NULL },
+ { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , 0, gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10, g_contained_ymm10, NULL },
+ { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , 0, gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11, g_contained_ymm11, NULL },
+ { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , 0, gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12, g_contained_ymm12, NULL },
+ { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , 0, gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13, g_contained_ymm13, NULL },
+ { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , 0, gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14, g_contained_ymm14, NULL },
+ { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , 0, gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, g_contained_ymm15, NULL }
+
+
};
// Exception registers
@@ -1951,31 +1964,58 @@ DNBArchImplX86_64::SetRegisterValue(int
return false;
}
+uint32_t
+DNBArchImplX86_64::GetRegisterContextSize()
+{
+ static uint32_t g_cached_size = 0;
+ if (g_cached_size == 0)
+ {
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ {
+ for (size_t i=0; i<k_num_fpu_registers_avx; ++i)
+ {
+ if (g_fpu_registers_avx[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_avx[i].size;
+ }
+ }
+ else
+ {
+ for (size_t i=0; i<k_num_fpu_registers_no_avx; ++i)
+ {
+ if (g_fpu_registers_no_avx[i].value_regs == NULL)
+ g_cached_size += g_fpu_registers_no_avx[i].size;
+ }
+ }
+ DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR = %zu, FPU = %u, EXC = %zu", sizeof(GPR), g_cached_size, sizeof(EXC));
+ g_cached_size += sizeof(GPR);
+ g_cached_size += sizeof(EXC);
+ DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR + FPU + EXC = %u", g_cached_size);
+ }
+ return g_cached_size;
+}
nub_size_t
DNBArchImplX86_64::GetRegisterContext (void *buf, nub_size_t buf_len)
{
- nub_size_t size = sizeof (m_state.context);
+ uint32_t size = GetRegisterContextSize();
if (buf && buf_len)
{
- if (size > buf_len)
- size = buf_len;
-
bool force = false;
kern_return_t kret;
+
if ((kret = GetGPRState(force)) != KERN_SUCCESS)
{
DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to read: %u ", buf, (uint64_t)buf_len, kret);
size = 0;
}
- else
+ else
if ((kret = GetFPUState(force)) != KERN_SUCCESS)
{
DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: %s regs failed to read: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
size = 0;
}
- else
+ else
if ((kret = GetEXCState(force)) != KERN_SUCCESS)
{
DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: EXC regs failed to read: %u", buf, (uint64_t)buf_len, kret);
@@ -1983,11 +2023,77 @@ DNBArchImplX86_64::GetRegisterContext (v
}
else
{
- // Success
- ::memcpy (buf, &m_state.context, size);
+ uint8_t *p = (uint8_t *)buf;
+ // Copy the GPR registers
+ memcpy(p, &m_state.context.gpr, sizeof(GPR));
+ p += sizeof(GPR);
+
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ {
+ // Walk around the gaps in the FPU regs
+ memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5);
+ p += 5;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8);
+ p += 8;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6);
+ p += 6;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10);
+ p += 10;
+ }
+
+ // Interleave the XMM and YMMH registers to make the YMM registers
+ for (size_t i=0; i<16; ++i)
+ {
+ memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16);
+ p += 16;
+ memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16);
+ p += 16;
+ }
+ }
+ else
+ {
+ // Walk around the gaps in the FPU regs
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
+ p += 5;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
+ p += 8;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
+ p += 6;
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
+ p += 10;
+ }
+
+ // Copy the XMM registers in a single block
+ memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 16 * 16);
+ p += 16 * 16;
+ }
+
+ // Copy the exception registers
+ memcpy(p, &m_state.context.exc, sizeof(EXC));
+ p += sizeof(EXC);
+
+ // make sure we end up with exactly what we think we should have
+ size_t bytes_written = p - (uint8_t *)buf;
+ assert (bytes_written == size);
}
+
}
- DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size);
+
+ DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) => %u", buf, (uint64_t)buf_len, size);
// Return the size of the register context even if NULL was passed in
return size;
}
@@ -1995,7 +2101,7 @@ DNBArchImplX86_64::GetRegisterContext (v
nub_size_t
DNBArchImplX86_64::SetRegisterContext (const void *buf, nub_size_t buf_len)
{
- nub_size_t size = sizeof (m_state.context);
+ uint32_t size = GetRegisterContextSize();
if (buf == NULL || buf_len == 0)
size = 0;
@@ -2004,7 +2110,73 @@ DNBArchImplX86_64::SetRegisterContext (c
if (size > buf_len)
size = buf_len;
- ::memcpy (&m_state.context, buf, size);
+ uint8_t *p = (uint8_t *)buf;
+ // Copy the GPR registers
+ memcpy(&m_state.context.gpr, p, sizeof(GPR));
+ p += sizeof(GPR);
+
+ if (CPUHasAVX() || FORCE_AVX_REGS)
+ {
+ // Walk around the gaps in the FPU regs
+ memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5);
+ p += 5;
+ memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8);
+ p += 8;
+ memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6);
+ p += 6;
+ memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10);
+ p += 10;
+ }
+
+ // Interleave the XMM and YMMH registers to make the YMM registers
+ for (size_t i=0; i<16; ++i)
+ {
+ memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16);
+ p += 16;
+ memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16);
+ p += 16;
+ }
+ }
+ else
+ {
+ // Copy fcw through mxcsrmask as there is no padding
+ memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
+ p += 5;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
+ p += 8;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
+ p += 6;
+ memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
+ p += 8;
+
+ // Work around the padding between the stmm registers as they are 16
+ // byte structs with 10 bytes of the value in each
+ for (size_t i=0; i<8; ++i)
+ {
+ memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
+ p += 10;
+ }
+
+ // Copy the XMM registers in a single block
+ memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 16 * 16);
+ p += 16 * 16;
+ }
+
+ // Copy the exception registers
+ memcpy(&m_state.context.exc, p, sizeof(EXC));
+ p += sizeof(EXC);
+
+ // make sure we end up with exactly what we think we should have
+ size_t bytes_written = p - (uint8_t *)buf;
+ assert (bytes_written == size);
+
kern_return_t kret;
if ((kret = SetGPRState()) != KERN_SUCCESS)
DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to write: %u", buf, (uint64_t)buf_len, kret);
Modified: lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h (original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.h Fri Nov 8 18:33:46 2013
@@ -227,6 +227,8 @@ protected:
static const DNBRegisterSetInfo *
GetRegisterSetInfo(nub_size_t *num_reg_sets);
+ static uint32_t GetRegisterContextSize();
+
// Helper functions for watchpoint manipulations.
static void SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write);
static void ClearWatchpoint(DBG &debug_state, uint32_t hw_index);
Modified: lldb/trunk/tools/debugserver/source/RNBRemote.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/RNBRemote.cpp?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/RNBRemote.cpp (original)
+++ lldb/trunk/tools/debugserver/source/RNBRemote.cpp Fri Nov 8 18:33:46 2013
@@ -74,7 +74,6 @@ RNBRemote::RNBRemote () :
m_max_payload_size(DEFAULT_GDB_REMOTE_PROTOCOL_BUFSIZE - 4),
m_extended_mode(false),
m_noack_mode(false),
- m_use_native_regs (false),
m_thread_suffix_supported (false),
m_list_threads_in_stop_reply (false)
{
@@ -842,11 +841,10 @@ decode_binary_data (const char *str, siz
typedef struct register_map_entry
{
uint32_t gdb_regnum; // gdb register number
- uint32_t gdb_size; // gdb register size in bytes (can be greater than or less than to debugnub size...)
- const char * gdb_name; // gdb register name
+ uint32_t offset; // Offset in bytes into the register context data with no padding between register values
DNBRegisterInfo nub_info; // debugnub register info
- const uint8_t* fail_value; // Value to print if case we fail to reg this register (if this is NULL, we will return an error)
- int expedite; // expedite delivery of this register in last stop reply packets
+ std::vector<uint32_t> value_regnums;
+ std::vector<uint32_t> invalidate_regnums;
} register_map_entry_t;
@@ -860,242 +858,6 @@ static std::vector<register_map_entry_t>
static register_map_entry_t *g_reg_entries = NULL;
static size_t g_num_reg_entries = 0;
-static void
-RegisterEntryNotAvailable (register_map_entry_t *reg_entry)
-{
- reg_entry->fail_value = k_zero_bytes;
- reg_entry->nub_info.set = INVALID_NUB_REGNUM;
- reg_entry->nub_info.reg = INVALID_NUB_REGNUM;
- reg_entry->nub_info.name = NULL;
- reg_entry->nub_info.alt = NULL;
- reg_entry->nub_info.type = InvalidRegType;
- reg_entry->nub_info.format = InvalidRegFormat;
- reg_entry->nub_info.size = 0;
- reg_entry->nub_info.offset = 0;
- reg_entry->nub_info.reg_gcc = INVALID_NUB_REGNUM;
- reg_entry->nub_info.reg_dwarf = INVALID_NUB_REGNUM;
- reg_entry->nub_info.reg_generic = INVALID_NUB_REGNUM;
- reg_entry->nub_info.reg_gdb = INVALID_NUB_REGNUM;
- reg_entry->nub_info.pseudo_regs = NULL;
- reg_entry->nub_info.update_regs = NULL;
-}
-
-
-//----------------------------------------------------------------------
-// ARM regiseter sets as gdb knows them
-//----------------------------------------------------------------------
-register_map_entry_t
-g_gdb_register_map_arm[] =
-{
- { 0, 4, "r0", {0}, NULL, 1},
- { 1, 4, "r1", {0}, NULL, 1},
- { 2, 4, "r2", {0}, NULL, 1},
- { 3, 4, "r3", {0}, NULL, 1},
- { 4, 4, "r4", {0}, NULL, 1},
- { 5, 4, "r5", {0}, NULL, 1},
- { 6, 4, "r6", {0}, NULL, 1},
- { 7, 4, "r7", {0}, NULL, 1},
- { 8, 4, "r8", {0}, NULL, 1},
- { 9, 4, "r9", {0}, NULL, 1},
- { 10, 4, "r10", {0}, NULL, 1},
- { 11, 4, "r11", {0}, NULL, 1},
- { 12, 4, "r12", {0}, NULL, 1},
- { 13, 4, "sp", {0}, NULL, 1},
- { 14, 4, "lr", {0}, NULL, 1},
- { 15, 4, "pc", {0}, NULL, 1},
- { 16, 4,"cpsr", {0}, NULL, 1}, // current program status register
- { 17, 4, "s0", {0}, NULL, 0},
- { 18, 4, "s1", {0}, NULL, 0},
- { 19, 4, "s2", {0}, NULL, 0},
- { 20, 4, "s3", {0}, NULL, 0},
- { 21, 4, "s4", {0}, NULL, 0},
- { 22, 4, "s5", {0}, NULL, 0},
- { 23, 4, "s6", {0}, NULL, 0},
- { 24, 4, "s7", {0}, NULL, 0},
- { 25, 4, "s8", {0}, NULL, 0},
- { 26, 4, "s9", {0}, NULL, 0},
- { 27, 4, "s10", {0}, NULL, 0},
- { 28, 4, "s11", {0}, NULL, 0},
- { 29, 4, "s12", {0}, NULL, 0},
- { 30, 4, "s13", {0}, NULL, 0},
- { 31, 4, "s14", {0}, NULL, 0},
- { 32, 4, "s15", {0}, NULL, 0},
- { 33, 4, "s16", {0}, NULL, 0},
- { 34, 4, "s17", {0}, NULL, 0},
- { 35, 4, "s18", {0}, NULL, 0},
- { 36, 4, "s19", {0}, NULL, 0},
- { 37, 4, "s20", {0}, NULL, 0},
- { 38, 4, "s21", {0}, NULL, 0},
- { 39, 4, "s22", {0}, NULL, 0},
- { 40, 4, "s23", {0}, NULL, 0},
- { 41, 4, "s24", {0}, NULL, 0},
- { 42, 4, "s25", {0}, NULL, 0},
- { 43, 4, "s26", {0}, NULL, 0},
- { 44, 4, "s27", {0}, NULL, 0},
- { 45, 4, "s28", {0}, NULL, 0},
- { 46, 4, "s29", {0}, NULL, 0},
- { 47, 4, "s30", {0}, NULL, 0},
- { 48, 4, "s31", {0}, NULL, 0},
- { 49, 8, "d0", {0}, NULL, 0},
- { 50, 8, "d1", {0}, NULL, 0},
- { 51, 8, "d2", {0}, NULL, 0},
- { 52, 8, "d3", {0}, NULL, 0},
- { 53, 8, "d4", {0}, NULL, 0},
- { 54, 8, "d5", {0}, NULL, 0},
- { 55, 8, "d6", {0}, NULL, 0},
- { 56, 8, "d7", {0}, NULL, 0},
- { 57, 8, "d8", {0}, NULL, 0},
- { 58, 8, "d9", {0}, NULL, 0},
- { 59, 8, "d10", {0}, NULL, 0},
- { 60, 8, "d11", {0}, NULL, 0},
- { 61, 8, "d12", {0}, NULL, 0},
- { 62, 8, "d13", {0}, NULL, 0},
- { 63, 8, "d14", {0}, NULL, 0},
- { 64, 8, "d15", {0}, NULL, 0},
- { 65, 8, "d16", {0}, NULL, 0},
- { 66, 8, "d17", {0}, NULL, 0},
- { 67, 8, "d18", {0}, NULL, 0},
- { 68, 8, "d19", {0}, NULL, 0},
- { 69, 8, "d20", {0}, NULL, 0},
- { 70, 8, "d21", {0}, NULL, 0},
- { 71, 8, "d22", {0}, NULL, 0},
- { 72, 8, "d23", {0}, NULL, 0},
- { 73, 8, "d24", {0}, NULL, 0},
- { 74, 8, "d25", {0}, NULL, 0},
- { 75, 8, "d26", {0}, NULL, 0},
- { 76, 8, "d27", {0}, NULL, 0},
- { 77, 8, "d28", {0}, NULL, 0},
- { 78, 8, "d29", {0}, NULL, 0},
- { 79, 8, "d30", {0}, NULL, 0},
- { 80, 8, "d31", {0}, NULL, 0},
- { 81, 16, "q0", {0}, NULL, 0},
- { 82, 16, "q1", {0}, NULL, 0},
- { 83, 16, "q2", {0}, NULL, 0},
- { 84, 16, "q3", {0}, NULL, 0},
- { 85, 16, "q4", {0}, NULL, 0},
- { 86, 16, "q5", {0}, NULL, 0},
- { 87, 16, "q6", {0}, NULL, 0},
- { 88, 16, "q7", {0}, NULL, 0},
- { 89, 16, "q8", {0}, NULL, 0},
- { 90, 16, "q9", {0}, NULL, 0},
- { 91, 16, "q10", {0}, NULL, 0},
- { 92, 16, "q11", {0}, NULL, 0},
- { 93, 16, "q12", {0}, NULL, 0},
- { 94, 16, "q13", {0}, NULL, 0},
- { 95, 16, "q14", {0}, NULL, 0},
- { 96, 16, "q15", {0}, NULL, 0},
- { 97, 4, "fpscr", {0}, NULL, 0}
-};
-
-register_map_entry_t
-g_gdb_register_map_i386[] =
-{
- { 0, 4, "eax" , {0}, NULL, 0 },
- { 1, 4, "ecx" , {0}, NULL, 0 },
- { 2, 4, "edx" , {0}, NULL, 0 },
- { 3, 4, "ebx" , {0}, NULL, 0 },
- { 4, 4, "esp" , {0}, NULL, 1 },
- { 5, 4, "ebp" , {0}, NULL, 1 },
- { 6, 4, "esi" , {0}, NULL, 0 },
- { 7, 4, "edi" , {0}, NULL, 0 },
- { 8, 4, "eip" , {0}, NULL, 1 },
- { 9, 4, "eflags" , {0}, NULL, 0 },
- { 10, 4, "cs" , {0}, NULL, 0 },
- { 11, 4, "ss" , {0}, NULL, 0 },
- { 12, 4, "ds" , {0}, NULL, 0 },
- { 13, 4, "es" , {0}, NULL, 0 },
- { 14, 4, "fs" , {0}, NULL, 0 },
- { 15, 4, "gs" , {0}, NULL, 0 },
- { 16, 10, "stmm0" , {0}, NULL, 0 },
- { 17, 10, "stmm1" , {0}, NULL, 0 },
- { 18, 10, "stmm2" , {0}, NULL, 0 },
- { 19, 10, "stmm3" , {0}, NULL, 0 },
- { 20, 10, "stmm4" , {0}, NULL, 0 },
- { 21, 10, "stmm5" , {0}, NULL, 0 },
- { 22, 10, "stmm6" , {0}, NULL, 0 },
- { 23, 10, "stmm7" , {0}, NULL, 0 },
- { 24, 4, "fctrl" , {0}, NULL, 0 },
- { 25, 4, "fstat" , {0}, NULL, 0 },
- { 26, 4, "ftag" , {0}, NULL, 0 },
- { 27, 4, "fiseg" , {0}, NULL, 0 },
- { 28, 4, "fioff" , {0}, NULL, 0 },
- { 29, 4, "foseg" , {0}, NULL, 0 },
- { 30, 4, "fooff" , {0}, NULL, 0 },
- { 31, 4, "fop" , {0}, NULL, 0 },
- { 32, 16, "xmm0" , {0}, NULL, 0 },
- { 33, 16, "xmm1" , {0}, NULL, 0 },
- { 34, 16, "xmm2" , {0}, NULL, 0 },
- { 35, 16, "xmm3" , {0}, NULL, 0 },
- { 36, 16, "xmm4" , {0}, NULL, 0 },
- { 37, 16, "xmm5" , {0}, NULL, 0 },
- { 38, 16, "xmm6" , {0}, NULL, 0 },
- { 39, 16, "xmm7" , {0}, NULL, 0 },
- { 40, 4, "mxcsr" , {0}, NULL, 0 },
-};
-
-register_map_entry_t
-g_gdb_register_map_x86_64[] =
-{
- { 0, 8, "rax" , {0}, NULL, 0 },
- { 1, 8, "rbx" , {0}, NULL, 0 },
- { 2, 8, "rcx" , {0}, NULL, 0 },
- { 3, 8, "rdx" , {0}, NULL, 0 },
- { 4, 8, "rsi" , {0}, NULL, 0 },
- { 5, 8, "rdi" , {0}, NULL, 0 },
- { 6, 8, "rbp" , {0}, NULL, 1 },
- { 7, 8, "rsp" , {0}, NULL, 1 },
- { 8, 8, "r8" , {0}, NULL, 0 },
- { 9, 8, "r9" , {0}, NULL, 0 },
- { 10, 8, "r10" , {0}, NULL, 0 },
- { 11, 8, "r11" , {0}, NULL, 0 },
- { 12, 8, "r12" , {0}, NULL, 0 },
- { 13, 8, "r13" , {0}, NULL, 0 },
- { 14, 8, "r14" , {0}, NULL, 0 },
- { 15, 8, "r15" , {0}, NULL, 0 },
- { 16, 8, "rip" , {0}, NULL, 1 },
- { 17, 4, "rflags", {0}, NULL, 0 },
- { 18, 4, "cs" , {0}, NULL, 0 },
- { 19, 4, "ss" , {0}, NULL, 0 },
- { 20, 4, "ds" , {0}, NULL, 0 },
- { 21, 4, "es" , {0}, NULL, 0 },
- { 22, 4, "fs" , {0}, NULL, 0 },
- { 23, 4, "gs" , {0}, NULL, 0 },
- { 24, 10, "stmm0" , {0}, NULL, 0 },
- { 25, 10, "stmm1" , {0}, NULL, 0 },
- { 26, 10, "stmm2" , {0}, NULL, 0 },
- { 27, 10, "stmm3" , {0}, NULL, 0 },
- { 28, 10, "stmm4" , {0}, NULL, 0 },
- { 29, 10, "stmm5" , {0}, NULL, 0 },
- { 30, 10, "stmm6" , {0}, NULL, 0 },
- { 31, 10, "stmm7" , {0}, NULL, 0 },
- { 32, 4, "fctrl" , {0}, NULL, 0 },
- { 33, 4, "fstat" , {0}, NULL, 0 },
- { 34, 4, "ftag" , {0}, NULL, 0 },
- { 35, 4, "fiseg" , {0}, NULL, 0 },
- { 36, 4, "fioff" , {0}, NULL, 0 },
- { 37, 4, "foseg" , {0}, NULL, 0 },
- { 38, 4, "fooff" , {0}, NULL, 0 },
- { 39, 4, "fop" , {0}, NULL, 0 },
- { 40, 16, "xmm0" , {0}, NULL, 0 },
- { 41, 16, "xmm1" , {0}, NULL, 0 },
- { 42, 16, "xmm2" , {0}, NULL, 0 },
- { 43, 16, "xmm3" , {0}, NULL, 0 },
- { 44, 16, "xmm4" , {0}, NULL, 0 },
- { 45, 16, "xmm5" , {0}, NULL, 0 },
- { 46, 16, "xmm6" , {0}, NULL, 0 },
- { 47, 16, "xmm7" , {0}, NULL, 0 },
- { 48, 16, "xmm8" , {0}, NULL, 0 },
- { 49, 16, "xmm9" , {0}, NULL, 0 },
- { 50, 16, "xmm10" , {0}, NULL, 0 },
- { 51, 16, "xmm11" , {0}, NULL, 0 },
- { 52, 16, "xmm12" , {0}, NULL, 0 },
- { 53, 16, "xmm13" , {0}, NULL, 0 },
- { 54, 16, "xmm14" , {0}, NULL, 0 },
- { 55, 16, "xmm15" , {0}, NULL, 0 },
- { 56, 4, "mxcsr" , {0}, NULL, 0 }
-};
-
-
void
RNBRemote::Initialize()
{
@@ -1110,112 +872,120 @@ RNBRemote::InitializeRegisters (bool for
if (pid == INVALID_NUB_PROCESS)
return false;
- if (m_use_native_regs)
+ DNBLogThreadedIf (LOG_RNB_PROC, "RNBRemote::%s() getting native registers from DNB interface", __FUNCTION__);
+ // Discover the registers by querying the DNB interface and letting it
+ // state the registers that it would like to export. This allows the
+ // registers to be discovered using multiple qRegisterInfo calls to get
+ // all register information after the architecture for the process is
+ // determined.
+ if (force)
{
- DNBLogThreadedIf (LOG_RNB_PROC, "RNBRemote::%s() getting native registers from DNB interface", __FUNCTION__);
- // Discover the registers by querying the DNB interface and letting it
- // state the registers that it would like to export. This allows the
- // registers to be discovered using multiple qRegisterInfo calls to get
- // all register information after the architecture for the process is
- // determined.
- if (force)
- {
- g_dynamic_register_map.clear();
- g_reg_entries = NULL;
- g_num_reg_entries = 0;
- }
+ g_dynamic_register_map.clear();
+ g_reg_entries = NULL;
+ g_num_reg_entries = 0;
+ }
- if (g_dynamic_register_map.empty())
- {
- nub_size_t num_reg_sets = 0;
- const DNBRegisterSetInfo *reg_sets = DNBGetRegisterSetInfo (&num_reg_sets);
+ if (g_dynamic_register_map.empty())
+ {
+ nub_size_t num_reg_sets = 0;
+ const DNBRegisterSetInfo *reg_sets = DNBGetRegisterSetInfo (&num_reg_sets);
- assert (num_reg_sets > 0 && reg_sets != NULL);
+ assert (num_reg_sets > 0 && reg_sets != NULL);
+
+ uint32_t regnum = 0;
+ uint32_t reg_data_offset = 0;
+ typedef std::map<std::string, uint32_t> NameToRegNum;
+ NameToRegNum name_to_regnum;
+ for (nub_size_t set = 0; set < num_reg_sets; ++set)
+ {
+ if (reg_sets[set].registers == NULL)
+ continue;
- uint32_t regnum = 0;
- for (nub_size_t set = 0; set < num_reg_sets; ++set)
+ for (uint32_t reg=0; reg < reg_sets[set].num_registers; ++reg)
{
- if (reg_sets[set].registers == NULL)
- continue;
+ register_map_entry_t reg_entry = {
+ regnum++, // register number starts at zero and goes up with no gaps
+ reg_data_offset, // Offset into register context data, no gaps between registers
+ reg_sets[set].registers[reg] // DNBRegisterInfo
+ };
- for (uint32_t reg=0; reg < reg_sets[set].num_registers; ++reg)
- {
- register_map_entry_t reg_entry = {
- regnum++, // register number starts at zero and goes up with no gaps
- reg_sets[set].registers[reg].size, // register size in bytes
- reg_sets[set].registers[reg].name, // register name
- reg_sets[set].registers[reg], // DNBRegisterInfo
- NULL, // Value to print if case we fail to reg this register (if this is NULL, we will return an error)
- reg_sets[set].registers[reg].reg_generic != INVALID_NUB_REGNUM};
+ name_to_regnum[reg_entry.nub_info.name] = reg_entry.gdb_regnum;
- g_dynamic_register_map.push_back (reg_entry);
+ if (reg_entry.nub_info.value_regs == NULL)
+ {
+ DNBLogThreaded("%s -> %u", reg_entry.nub_info.name, reg_data_offset);
+ reg_data_offset += reg_entry.nub_info.size;
}
+
+ g_dynamic_register_map.push_back (reg_entry);
}
- g_reg_entries = g_dynamic_register_map.data();
- g_num_reg_entries = g_dynamic_register_map.size();
- }
- return true;
- }
- else
- {
- uint32_t cpu_type = DNBProcessGetCPUType (pid);
- if (cpu_type == 0)
- {
- DNBLog ("Unable to get the process cpu_type, making a best guess.");
- cpu_type = best_guess_cpu_type ();
}
-
- DNBLogThreadedIf (LOG_RNB_PROC, "RNBRemote::%s() getting gdb registers(%s)", __FUNCTION__, m_arch.c_str());
-#if defined (__i386__) || defined (__x86_64__)
- if (cpu_type == CPU_TYPE_X86_64)
- {
- const size_t num_regs = sizeof (g_gdb_register_map_x86_64) / sizeof (register_map_entry_t);
- for (uint32_t i=0; i<num_regs; ++i)
- {
- if (!DNBGetRegisterInfoByName (g_gdb_register_map_x86_64[i].gdb_name, &g_gdb_register_map_x86_64[i].nub_info))
+
+ // Now we must find any regsiters whose values are in other registers and fix up
+ // the offsets since we removed all gaps...
+ for (auto ®_entry: g_dynamic_register_map)
+ {
+ if (reg_entry.nub_info.value_regs)
+ {
+ uint32_t new_offset = UINT32_MAX;
+ for (size_t i=0; reg_entry.nub_info.value_regs[i] != NULL; ++i)
+ {
+ const char *name = reg_entry.nub_info.value_regs[i];
+ auto pos = name_to_regnum.find(name);
+ if (pos != name_to_regnum.end())
+ {
+ regnum = pos->second;
+ reg_entry.value_regnums.push_back(regnum);
+ if (regnum < g_dynamic_register_map.size())
+ {
+ // The offset for value_regs registers is the offset within the register with the lowest offset
+ const uint32_t reg_offset = g_dynamic_register_map[regnum].offset + reg_entry.nub_info.offset;
+ if (new_offset > reg_offset)
+ new_offset = reg_offset;
+ }
+ }
+ }
+
+ if (new_offset != UINT32_MAX)
{
- RegisterEntryNotAvailable (&g_gdb_register_map_x86_64[i]);
- assert (g_gdb_register_map_x86_64[i].gdb_size < MAX_REGISTER_BYTE_SIZE);
+ reg_entry.offset = new_offset;
}
- }
- g_reg_entries = g_gdb_register_map_x86_64;
- g_num_reg_entries = sizeof (g_gdb_register_map_x86_64) / sizeof (register_map_entry_t);
- return true;
- }
- else if (cpu_type == CPU_TYPE_I386)
- {
- const size_t num_regs = sizeof (g_gdb_register_map_i386) / sizeof (register_map_entry_t);
- for (uint32_t i=0; i<num_regs; ++i)
- {
- if (!DNBGetRegisterInfoByName (g_gdb_register_map_i386[i].gdb_name, &g_gdb_register_map_i386[i].nub_info))
+ else
{
- RegisterEntryNotAvailable (&g_gdb_register_map_i386[i]);
- assert (g_gdb_register_map_i386[i].gdb_size <= MAX_REGISTER_BYTE_SIZE);
+ DNBLogThreaded("no offset was calculated entry for register %s", reg_entry.nub_info.name);
+ reg_entry.offset = UINT32_MAX;
}
}
- g_reg_entries = g_gdb_register_map_i386;
- g_num_reg_entries = sizeof (g_gdb_register_map_i386) / sizeof (register_map_entry_t);
- return true;
- }
-#elif defined (__arm__)
- if (cpu_type == CPU_TYPE_ARM)
- {
- const size_t num_regs = sizeof (g_gdb_register_map_arm) / sizeof (register_map_entry_t);
- for (uint32_t i=0; i<num_regs; ++i)
+
+ if (reg_entry.nub_info.update_regs)
{
- if (!DNBGetRegisterInfoByName (g_gdb_register_map_arm[i].gdb_name, &g_gdb_register_map_arm[i].nub_info))
+ for (size_t i=0; reg_entry.nub_info.update_regs[i] != NULL; ++i)
{
- RegisterEntryNotAvailable (&g_gdb_register_map_arm[i]);
- assert (g_gdb_register_map_arm[i].gdb_size <= MAX_REGISTER_BYTE_SIZE);
+ const char *name = reg_entry.nub_info.update_regs[i];
+ auto pos = name_to_regnum.find(name);
+ if (pos != name_to_regnum.end())
+ {
+ regnum = pos->second;
+ reg_entry.invalidate_regnums.push_back(regnum);
+ }
}
}
- g_reg_entries = g_gdb_register_map_arm;
- g_num_reg_entries = sizeof (g_gdb_register_map_arm) / sizeof (register_map_entry_t);
- return true;
}
-#endif
+
+
+// for (auto ®_entry: g_dynamic_register_map)
+// {
+// DNBLogThreaded("%4i: size = %3u, pseudo = %i, name = %s",
+// reg_entry.offset,
+// reg_entry.nub_info.size,
+// reg_entry.nub_info.value_regs != NULL,
+// reg_entry.nub_info.name);
+// }
+
+ g_reg_entries = g_dynamic_register_map.data();
+ g_num_reg_entries = g_dynamic_register_map.size();
}
- return false;
+ return true;
}
/* The inferior has stopped executing; send a packet
@@ -1669,15 +1439,13 @@ RNBRemote::HandlePacket_qRegisterInfo (c
{
const register_map_entry_t *reg_entry = &g_reg_entries[reg_num];
std::ostringstream ostrm;
- ostrm << "name:" << reg_entry->gdb_name << ';';
-
- if (reg_entry->nub_info.name && ::strcmp (reg_entry->gdb_name, reg_entry->nub_info.name))
- ostrm << "alt-name:" << reg_entry->nub_info.name << ';';
- else if (reg_entry->nub_info.alt && ::strcmp (reg_entry->gdb_name, reg_entry->nub_info.alt))
+ if (reg_entry->nub_info.name)
+ ostrm << "name:" << reg_entry->nub_info.name << ';';
+ if (reg_entry->nub_info.alt)
ostrm << "alt-name:" << reg_entry->nub_info.alt << ';';
- ostrm << "bitsize:" << std::dec << reg_entry->gdb_size * 8 << ';';
- ostrm << "offset:" << std::dec << reg_entry->nub_info.offset << ';';
+ ostrm << "bitsize:" << std::dec << reg_entry->nub_info.size * 8 << ';';
+ ostrm << "offset:" << std::dec << reg_entry->offset << ';';
switch (reg_entry->nub_info.type)
{
@@ -1706,23 +1474,12 @@ RNBRemote::HandlePacket_qRegisterInfo (c
if (reg_set_info && reg_entry->nub_info.set < num_reg_sets)
ostrm << "set:" << reg_set_info[reg_entry->nub_info.set].name << ';';
-
- if (g_reg_entries != g_dynamic_register_map.data())
- {
- if (reg_entry->nub_info.reg_gdb != INVALID_NUB_REGNUM && reg_entry->nub_info.reg_gdb != reg_num)
- {
- printf("register %s is getting gdb reg_num of %u when the register info says %u\n",
- reg_entry->gdb_name, reg_num, reg_entry->nub_info.reg_gdb);
- }
- }
-
if (reg_entry->nub_info.reg_gcc != INVALID_NUB_REGNUM)
ostrm << "gcc:" << std::dec << reg_entry->nub_info.reg_gcc << ';';
if (reg_entry->nub_info.reg_dwarf != INVALID_NUB_REGNUM)
ostrm << "dwarf:" << std::dec << reg_entry->nub_info.reg_dwarf << ';';
-
switch (reg_entry->nub_info.reg_generic)
{
case GENERIC_REGNUM_FP: ostrm << "generic:fp;"; break;
@@ -1741,26 +1498,26 @@ RNBRemote::HandlePacket_qRegisterInfo (c
default: break;
}
- if (reg_entry->nub_info.pseudo_regs && reg_entry->nub_info.pseudo_regs[0] != INVALID_NUB_REGNUM)
+ if (!reg_entry->value_regnums.empty())
{
ostrm << "container-regs:";
- for (unsigned i=0; reg_entry->nub_info.pseudo_regs[i] != INVALID_NUB_REGNUM; ++i)
+ for (size_t i=0, n=reg_entry->value_regnums.size(); i < n; ++i)
{
if (i > 0)
ostrm << ',';
- ostrm << RAW_HEXBASE << reg_entry->nub_info.pseudo_regs[i];
+ ostrm << RAW_HEXBASE << reg_entry->value_regnums[i];
}
ostrm << ';';
}
- if (reg_entry->nub_info.update_regs && reg_entry->nub_info.update_regs[0] != INVALID_NUB_REGNUM)
+ if (!reg_entry->invalidate_regnums.empty())
{
ostrm << "invalidate-regs:";
- for (unsigned i=0; reg_entry->nub_info.update_regs[i] != INVALID_NUB_REGNUM; ++i)
+ for (size_t i=0, n=reg_entry->invalidate_regnums.size(); i < n; ++i)
{
if (i > 0)
ostrm << ',';
- ostrm << RAW_HEXBASE << reg_entry->nub_info.update_regs[i];
+ ostrm << RAW_HEXBASE << reg_entry->invalidate_regnums[i];
}
ostrm << ';';
}
@@ -2362,24 +2119,17 @@ register_value_in_hex_fixed_width (std::
if (reg_value_ptr)
{
- append_hex_value (ostrm, reg_value_ptr->value.v_uint8, reg->gdb_size, false);
+ append_hex_value (ostrm, reg_value_ptr->value.v_uint8, reg->nub_info.size, false);
}
else
{
// If we fail to read a regiser value, check if it has a default
// fail value. If it does, return this instead in case some of
// the registers are not available on the current system.
- if (reg->gdb_size > 0)
+ if (reg->nub_info.size > 0)
{
- if (reg->fail_value != NULL)
- {
- append_hex_value (ostrm, reg->fail_value, reg->gdb_size, false);
- }
- else
- {
- std::basic_string<uint8_t> zeros(reg->gdb_size, '\0');
- append_hex_value (ostrm, zeros.data(), zeros.size(), false);
- }
+ std::basic_string<uint8_t> zeros(reg->nub_info.size, '\0');
+ append_hex_value (ostrm, zeros.data(), zeros.size(), false);
}
}
}
@@ -2510,7 +2260,10 @@ RNBRemote::SendStopReplyPacketForThread
DNBRegisterValue reg_value;
for (uint32_t reg = 0; reg < g_num_reg_entries; reg++)
{
- if (g_reg_entries[reg].expedite)
+ // Expedite all registers in the first register set that aren't
+ // contained in other registers
+ if (g_reg_entries[reg].nub_info.set == 1 &&
+ g_reg_entries[reg].nub_info.value_regs == NULL)
{
if (!DNBThreadGetRegisterValueByID (pid, tid, g_reg_entries[reg].nub_info.set, g_reg_entries[reg].nub_info.reg, ®_value))
continue;
@@ -2815,30 +2568,22 @@ RNBRemote::HandlePacket_g (const char *p
if (tid == INVALID_NUB_THREAD)
return HandlePacket_ILLFORMED (__FILE__, __LINE__, p, "No thread specified in p packet");
- if (m_use_native_regs)
- {
- // Get the register context size first by calling with NULL buffer
- nub_size_t reg_ctx_size = DNBThreadGetRegisterContext(pid, tid, NULL, 0);
+ // Get the register context size first by calling with NULL buffer
+ nub_size_t reg_ctx_size = DNBThreadGetRegisterContext(pid, tid, NULL, 0);
+ if (reg_ctx_size)
+ {
+ // Now allocate enough space for the entire register context
+ std::vector<uint8_t> reg_ctx;
+ reg_ctx.resize(reg_ctx_size);
+ // Now read the register context
+ reg_ctx_size = DNBThreadGetRegisterContext(pid, tid, ®_ctx[0], reg_ctx.size());
if (reg_ctx_size)
{
- // Now allocate enough space for the entire register context
- std::vector<uint8_t> reg_ctx;
- reg_ctx.resize(reg_ctx_size);
- // Now read the register context
- reg_ctx_size = DNBThreadGetRegisterContext(pid, tid, ®_ctx[0], reg_ctx.size());
- if (reg_ctx_size)
- {
- append_hex_value (ostrm, reg_ctx.data(), reg_ctx.size(), false);
- return SendPacket (ostrm.str ());
- }
+ append_hex_value (ostrm, reg_ctx.data(), reg_ctx.size(), false);
+ return SendPacket (ostrm.str ());
}
}
-
- for (uint32_t reg = 0; reg < g_num_reg_entries; reg++)
- if (g_reg_entries[reg].nub_info.pseudo_regs == NULL) // skip registers that are a slice of a real register
- register_value_in_hex_fixed_width (ostrm, pid, tid, &g_reg_entries[reg], NULL);
-
- return SendPacket (ostrm.str ());
+ return SendPacket ("E74");
}
/* 'G XXX...' -- write registers
@@ -2864,55 +2609,31 @@ RNBRemote::HandlePacket_G (const char *p
if (tid == INVALID_NUB_THREAD)
return HandlePacket_ILLFORMED (__FILE__, __LINE__, p, "No thread specified in p packet");
- if (m_use_native_regs)
- {
- // Get the register context size first by calling with NULL buffer
- nub_size_t reg_ctx_size = DNBThreadGetRegisterContext(pid, tid, NULL, 0);
- if (reg_ctx_size)
+ // Get the register context size first by calling with NULL buffer
+ nub_size_t reg_ctx_size = DNBThreadGetRegisterContext(pid, tid, NULL, 0);
+ if (reg_ctx_size)
+ {
+ // Now allocate enough space for the entire register context
+ std::vector<uint8_t> reg_ctx;
+ reg_ctx.resize(reg_ctx_size);
+
+ const nub_size_t bytes_extracted = packet.GetHexBytes (®_ctx[0], reg_ctx.size(), 0xcc);
+ if (bytes_extracted == reg_ctx.size())
{
- // Now allocate enough space for the entire register context
- std::vector<uint8_t> reg_ctx;
- reg_ctx.resize(reg_ctx_size);
-
- const nub_size_t bytes_extracted = packet.GetHexBytes (®_ctx[0], reg_ctx.size(), 0xcc);
- if (bytes_extracted == reg_ctx.size())
- {
- // Now write the register context
- reg_ctx_size = DNBThreadSetRegisterContext(pid, tid, reg_ctx.data(), reg_ctx.size());
- if (reg_ctx_size == reg_ctx.size())
- return SendPacket ("OK");
- else
- return SendPacket ("E55");
- }
- else
- {
- DNBLogError("RNBRemote::HandlePacket_G(%s): extracted %llu of %llu bytes, size mismatch\n", p, (uint64_t)bytes_extracted, (uint64_t)reg_ctx_size);
- return SendPacket ("E64");
- }
+ // Now write the register context
+ reg_ctx_size = DNBThreadSetRegisterContext(pid, tid, reg_ctx.data(), reg_ctx.size());
+ if (reg_ctx_size == reg_ctx.size())
+ return SendPacket ("OK");
+ else
+ return SendPacket ("E55");
}
else
- return SendPacket ("E65");
- }
-
-
- DNBRegisterValue reg_value;
- for (uint32_t reg = 0; reg < g_num_reg_entries; reg++)
- {
- const register_map_entry_t *reg_entry = &g_reg_entries[reg];
- if (reg_entry->nub_info.pseudo_regs == NULL) // skip registers that are a slice of a real register
{
- reg_value.info = reg_entry->nub_info;
- if (packet.GetHexBytes (reg_value.value.v_sint8, reg_entry->gdb_size, 0xcc) != reg_entry->gdb_size)
- break;
-
- if (reg_entry->fail_value == NULL)
- {
- if (!DNBThreadSetRegisterValueByID (pid, tid, reg_entry->nub_info.set, reg_entry->nub_info.reg, ®_value))
- return SendPacket ("E15");
- }
+ DNBLogError("RNBRemote::HandlePacket_G(%s): extracted %llu of %llu bytes, size mismatch\n", p, (uint64_t)bytes_extracted, (uint64_t)reg_ctx_size);
+ return SendPacket ("E64");
}
}
- return SendPacket ("OK");
+ return SendPacket ("E65");
}
static bool
@@ -3440,17 +3161,10 @@ RNBRemote::HandlePacket_p (const char *p
}
else if (reg_entry->nub_info.reg == -1)
{
- if (reg_entry->gdb_size > 0)
+ if (reg_entry->nub_info.size > 0)
{
- if (reg_entry->fail_value != NULL)
- {
- append_hex_value(ostrm, reg_entry->fail_value, reg_entry->gdb_size, false);
- }
- else
- {
- std::basic_string<uint8_t> zeros(reg_entry->gdb_size, '\0');
- append_hex_value(ostrm, zeros.data(), zeros.size(), false);
- }
+ std::basic_string<uint8_t> zeros(reg_entry->nub_info.size, '\0');
+ append_hex_value(ostrm, zeros.data(), zeros.size(), false);
}
}
else
@@ -3512,7 +3226,7 @@ RNBRemote::HandlePacket_P (const char *p
DNBRegisterValue reg_value;
reg_value.info = reg_entry->nub_info;
- packet.GetHexBytes (reg_value.value.v_sint8, reg_entry->gdb_size, 0xcc);
+ packet.GetHexBytes (reg_value.value.v_sint8, reg_entry->nub_info.size, 0xcc);
nub_thread_t tid = ExtractThreadIDFromThreadSuffix (p);
if (tid == INVALID_NUB_THREAD)
Modified: lldb/trunk/tools/debugserver/source/RNBRemote.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/RNBRemote.h?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/RNBRemote.h (original)
+++ lldb/trunk/tools/debugserver/source/RNBRemote.h Fri Nov 8 18:33:46 2013
@@ -234,11 +234,6 @@ public:
RNBContext& Context() { return m_ctx; }
RNBSocket& Comm() { return m_comm; }
- void
- SetUseNativeRegisters (bool b)
- {
- m_use_native_regs = b;
- }
private:
// Outlaw some contructors
RNBRemote (const RNBRemote &);
@@ -317,7 +312,6 @@ protected:
uint32_t m_max_payload_size; // the maximum sized payload we should send to gdb
bool m_extended_mode; // are we in extended mode?
bool m_noack_mode; // are we in no-ack mode?
- bool m_use_native_regs; // Use native registers by querying DNB layer for register definitions?
bool m_thread_suffix_supported; // Set to true if the 'p', 'P', 'g', and 'G' packets should be prefixed with the thread ID and colon:
// "$pRR;thread:TTTT;" instead of "$pRR"
// "$PRR=VVVVVVVV;thread:TTTT;" instead of "$PRR=VVVVVVVV"
Modified: lldb/trunk/tools/debugserver/source/debugserver.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/debugserver.cpp?rev=194302&r1=194301&r2=194302&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/debugserver.cpp (original)
+++ lldb/trunk/tools/debugserver/source/debugserver.cpp Fri Nov 8 18:33:46 2013
@@ -1027,7 +1027,7 @@ main (int argc, char *argv[])
break;
case 'r':
- remote->SetUseNativeRegisters (true);
+ // Do nothing, native regs is the default these days
break;
case 'v':
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