[Lldb-commits] [lldb] r128559 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
Caroline Tice
ctice at apple.com
Wed Mar 30 10:54:52 PDT 2011
Author: ctice
Date: Wed Mar 30 12:54:52 2011
New Revision: 128559
URL: http://llvm.org/viewvc/llvm-project?rev=128559&view=rev
Log:
Fill in EmulateLDRDRegister to emulate LDRD (register) instruction.
Remove stubs for functions not-to-be-implemented at the moment.
Modified:
lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128559&r1=128558&r2=128559&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Mar 30 12:54:52 2011
@@ -9798,99 +9798,6 @@
return true;
}
-// A8.6.74 LDRH (immediate, ARM)
-bool
-EmulateInstructionARM::EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-// A8.6.69 LDREX
-bool
-EmulateInstructionARM::EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-// A8.6.62 LDRB (immediate, ARM)
-bool
-EmulateInstructionARM::EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-// A8.6.59 LDR (literal)
-bool
-EmulateInstructionARM::EmulateLDRLiteral (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-
-// A8.6.65 LDRBT
-bool
-EmulateInstructionARM::EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
// A8.6.66 LDRD (immediate)
// Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two
// words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing.
@@ -9950,6 +9857,8 @@
//if Rt<0> == â1â then UNPREDICTABLE;
//t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
t = Bits32 (opcode, 15, 12);
+ if (BitIsSet (t, 0))
+ return false;
t2 = t + 1;
n = Bits32 (opcode, 19, 16);
imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
@@ -10034,212 +9943,128 @@
return true;
}
-
-// A8.6.67 LDRD (literal)
-bool
-EmulateInstructionARM::EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
// A8.6.68 LDRD (register)
+// Load Register Dual (register) calculates an address from a base register value and a register offset, loads two
+// words from memory, and writes them to two registers. It can use offset, post-indexed or pre-indexed addressing.
bool
EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
+ if ConditionPassed() then
+ EncodingSpecificOperations();
+ offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
+ address = if index then offset_addr else R[n];
+ R[t] = MemA[address,4];
+ R[t2] = MemA[address+4,4];
+ if wback then R[n] = offset_addr;
#endif
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.70 LDREXB
-bool
-EmulateInstructionARM::EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.71 LDREXD
-bool
-EmulateInstructionARM::EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
+ bool success = false;
if (ConditionPassed(opcode))
{
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.72 LDREXH
-bool
-EmulateInstructionARM::EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
+ uint32_t t;
+ uint32_t t2;
+ uint32_t n;
+ uint32_t m;
+ bool index;
+ bool add;
+ bool wback;
- if (ConditionPassed(opcode))
- {
switch (encoding)
{
- }
- }
- return true;
-}
-
-
-
-// A8.6.77 LDRHT
-bool
-EmulateInstructionARM::EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
+ case eEncodingA1:
+ // if Rt<0> == â1â then UNPREDICTABLE;
+ // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
+ t = Bits32 (opcode, 15, 12);
+ if (BitIsSet (t, 0))
+ return false;
+ t2 = t + 1;
+ n = Bits32 (opcode, 19, 16);
+ m = Bits32 (opcode, 3, 0);
- //bool success = false;
+ // index = (P == â1â); add = (U == â1â); wback = (P == â0â) || (W == â1â);
+ index = BitIsSet (opcode, 24);
+ add = BitIsSet (opcode, 23);
+ wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
+ // if P == â0â && W == â1â then UNPREDICTABLE;
+ if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
+ return false;
+ // if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;
+ if ((t2 == 15) || (m == 15) || (m == t) || (m == t2))
+ return false;
-// A8.6.81 LDRSBT
-bool
-EmulateInstructionARM::EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
+ // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
+ if (wback && ((n == 15) || (n == t) || (n == t2)))
+ return false;
- //bool success = false;
+ // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
+ if ((ArchVersion() < 6) && wback && (m == n))
+ return false;
+ break;
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
+ default:
+ return false;
}
- }
- return true;
-}
-
-
-// A8.6.85 LDRSHT
-bool
-EmulateInstructionARM::EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
- //bool success = false;
+ uint32_t Rn = ReadCoreReg (n, &success);
+ if (!success)
+ return false;
+ Register base_reg;
+ base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
+ uint32_t Rm = ReadCoreReg (m, &success);
+ if (!success)
+ return false;
+ Register offset_reg;
+ offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
+ addr_t offset_addr;
+ if (add)
+ offset_addr = Rn + Rm;
+ else
+ offset_addr = Rn - Rm;
-// A8.6.86 LDRT
-bool
-EmulateInstructionARM::EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
+ // address = if index then offset_addr else R[n];
+ addr_t address;
+ if (index)
+ address = offset_addr;
+ else
+ address = Rn;
- //bool success = false;
+ EmulateInstruction::Context context;
+ context.type = eContextRegisterLoad;
+ context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
+ // R[t] = MemA[address,4];
+ const uint32_t addr_byte_size = GetAddressByteSize();
+ uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
+ if (!success)
+ return false;
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
+ return false;
+ // R[t2] = MemA[address+4,4];
-// A8.6.198 STRB (register)
-bool
-EmulateInstructionARM::EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
+ data = MemARead (context, address + 4, addr_byte_size, 0, &success);
+ if (!success)
+ return false;
- //bool success = false;
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data))
+ return false;
- if (ConditionPassed(opcode))
- {
- switch (encoding)
+ // if wback then R[n] = offset_addr;
+ if (wback)
{
- }
- }
- return true;
-}
-
-
-// A8.6.199 STRBT
-bool
-EmulateInstructionARM::EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
+ context.type = eContextAdjustBaseRegister;
+ context.SetAddress (offset_addr);
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
+ return false;
}
}
return true;
@@ -10255,12 +10080,12 @@
//bool success = false;
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
+// if (ConditionPassed(opcode))
+// {
+// switch (encoding)
+// {
+// }
+// }
return true;
}
@@ -10274,152 +10099,15 @@
//bool success = false;
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.203 STREXB
-bool
-EmulateInstructionARM::EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.204 STREXD
-bool
-EmulateInstructionARM::EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.205 STREXH
-bool
-EmulateInstructionARM::EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.206 STRH (immediate, Thumb)
-bool
-EmulateInstructionARM::EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-// A8.6.207 STRH (immediate, ARM)
-bool
-EmulateInstructionARM::EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-
-// A8.6.209 STRHT
-bool
-EmulateInstructionARM::EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- //bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
+// if (ConditionPassed(opcode))
+// {
+// switch (encoding)
+// {
+// }
+// }
+// return true;
}
-
-// A8.6.210 STRT
-bool
-EmulateInstructionARM::EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding)
-{
-#if 0
-#endif
-
- // bool success = false;
-
- if (ConditionPassed(opcode))
- {
- switch (encoding)
- {
- }
- }
- return true;
-}
-
-
-
-
EmulateInstructionARM::ARMOpcode*
EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
{
@@ -10598,6 +10286,7 @@
{ 0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
{ 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
{ 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
+ { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
//----------------------------------------------------------------------
// Store instructions
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