[Lldb-commits] [lldb] r126423 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h

[Johnny Chen]

Author: johnny
Date: Thu Feb 24 15:01:20 2011
New Revision: 126423

URL: http://llvm.org/viewvc/llvm-project?rev=126423&view=rev
Log:
Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the attempt to
switch to Jazelle state fails, thus treating BXJ as a BX operation.

Modified:
    lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
    lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h

Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126423&r1=126422&r2=126423&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Thu Feb 24 15:01:20 2011
@@ -129,6 +129,7 @@
 
 #define ARMV4T_ABOVE  (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8)
 #define ARMV5_ABOVE   (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8)
+#define ARMV5J_ABOVE  (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8)
 #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8)
 
 //----------------------------------------------------------------------
@@ -1247,7 +1248,6 @@
 }
 
 // Branch and Exchange causes a branch to an address and instruction set specified by a register.
-// BX
 bool
 EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding)
 {
@@ -1295,6 +1295,68 @@
     return true;
 }
 
+// Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an
+// address and instruction set specified by a register as though it were a BX instruction.
+//
+// TODO: Emulate Jazelle architecture?
+//       We currently assume that switching to Jazelle state fails, thus treating BXJ as a BX operation.
+bool
+EmulateInstructionARM::EmulateBXJRm (ARMEncoding encoding)
+{
+#if 0
+    // ARM pseudo code...
+    if (ConditionPassed())
+    {
+        EncodingSpecificOperations();
+        if JMCR.JE == ‘0’ || CurrentInstrSet() == InstrSet_ThumbEE then
+            BXWritePC(R[m]);
+        else
+            if JazelleAcceptsExecution() then
+                SwitchToJazelleExecution();
+            else
+                SUBARCHITECTURE_DEFINED handler call;
+    }
+#endif
+
+    bool success = false;
+    const uint32_t opcode = OpcodeAsUnsigned (&success);
+    if (!success)
+        return false;
+
+    if (ConditionPassed())
+    {
+        EmulateInstruction::Context context;
+        context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
+        uint32_t Rm; // the register with the target address
+        switch (encoding) {
+        case eEncodingT1:
+            Rm = Bits32(opcode, 19, 16);
+            if (BadReg(Rm))
+                return false;
+            if (InITBlock() && !LastInITBlock())
+                return false;
+            break;
+        case eEncodingA1:
+            Rm = Bits32(opcode, 3, 0);
+            if (Rm == 15)
+                return false;
+            break;
+        default:
+            return false;
+        }
+        addr_t target = ReadCoreReg (Rm, &success);
+        if (!success)
+            return false;
+                  
+        Register dwarf_reg;
+        dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+        context.SetRegister (dwarf_reg);
+        if (!BXWritePC(context, target))
+            return false;
+    }
+    return true;
+}
+
 // Set r7 to point to some ip offset.
 // SUB (immediate)
 bool
@@ -7069,6 +7131,8 @@
         { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE,   eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
         // for example, "bx lr"
         { 0x0ffffff0, 0x012fff10, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
+        // bxj
+        { 0x0ffffff0, 0x012fff20, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
 
         //----------------------------------------------------------------------
         // Data-processing instructions
@@ -7263,6 +7327,8 @@
         { 0xffffff87, 0x00004780, ARMV5_ABOVE,   eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
         // for example, "bx lr"
         { 0xffffff87, 0x00004700, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
+        // bxj
+        { 0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE,  eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
         // compare and branch
         { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"},
         // table branch byte

Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126423&r1=126422&r2=126423&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Thu Feb 24 15:01:20 2011
@@ -366,6 +366,10 @@
     bool
     EmulateBXRm (ARMEncoding encoding);
 
+    // A8.6.26 BXJ
+    bool
+    EmulateBXJRm (ARMEncoding encoding);
+
     // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
     bool
     EmulateSUBR7IPImm (ARMEncoding encoding);