[Lldb-commits] [lldb] r125542 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h

[Caroline Tice]

Author: ctice
Date: Mon Feb 14 18:19:42 2011
New Revision: 125542

URL: http://llvm.org/viewvc/llvm-project?rev=125542&view=rev
Log:

Add code to emulate the STMDA Arm instruction.


Modified:
    lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
    lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h

Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=125542&r1=125541&r2=125542&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Feb 14 18:19:42 2011
@@ -2877,6 +2877,134 @@
     return true;
 }
 
+// STMDA stores multiple registers to consecutive memory locations using an address from a base register.  The 
+// consecutive memory locations end at this address, and the address just below the lowest of those locations can 
+// optionally be written back to the base register.
+bool
+EmulateInstructionARM::EmulateSTMDA (ARMEncoding encoding)
+{
+#if 0
+    if ConditionPassed() then 
+        EncodingSpecificOperations();                   
+        address = R[n] - 4*BitCount(registers) + 4;
+                  
+        for i = 0 to 14 
+            if registers<i> == ’1’ then
+                if i == n && wback && i != LowestSetBit(registers) then 
+                    MemA[address,4] = bits(32) UNKNOWN;
+                else 
+                    MemA[address,4] = R[i];
+                address = address + 4;
+                  
+        if registers<15> == ’1’ then 
+            MemA[address,4] = PCStoreValue();
+                  
+        if wback then R[n] = R[n] - 4*BitCount(registers);
+#endif
+                  
+    bool success = false;
+    const uint32_t opcode = OpcodeAsUnsigned (&success);
+    if (!success)
+        return false;
+                  
+    if (ConditionPassed ())
+    {
+        uint32_t n;
+        uint32_t registers = 0;
+        bool wback;
+        const uint32_t addr_byte_size = GetAddressByteSize();
+                  
+        // EncodingSpecificOperations();
+        switch (encoding)
+        {
+            case eEncodingA1:
+                // n = UInt(Rn); registers = register_list; wback = (W == ’1’);
+                n = Bits32 (opcode, 19, 16);
+                registers = Bits32 (opcode, 15, 0);
+                wback = BitIsSet (opcode, 21);
+                  
+                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
+                if ((n == 15) || (BitCount (registers) < 1))
+                    return false;
+                break;
+            default:
+                return false;
+        }
+                  
+        // address = R[n] - 4*BitCount(registers) + 4;
+        int32_t offset = 0;
+        addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
+        if (!success)
+            return false;
+                  
+        address = address - (addr_byte_size * BitCount (registers)) + 4;
+                  
+        EmulateInstruction::Context context;
+        context.type = EmulateInstruction::eContextRegisterStore;
+        Register base_reg;
+        base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+                  
+        // for i = 0 to 14 
+        for (int i = 0; i < 14; ++i)
+        {
+            int lowest_bit_set = 14;
+            // if registers<i> == ’1’ then
+            if (BitIsSet (registers, i))
+            {
+                if (i < lowest_bit_set)
+                    lowest_bit_set = i;
+                //if i == n && wback && i != LowestSetBit(registers) then
+                if ((i == n) && wback && (i != lowest_bit_set))
+                    // MemA[address,4] = bits(32) UNKNOWN;
+                    WriteBits32UnknownToMemory (address + offset);
+                else
+                {
+                    // MemA[address,4] = R[i];
+                    uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
+                    if (!success)
+                        return false;
+                  
+                    Register data_reg;
+                    data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i);
+                    context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
+                    if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size))
+                        return false;
+                }
+                  
+                // address = address + 4;
+                offset += addr_byte_size;
+            }
+        }
+                  
+        // if registers<15> == ’1’ then 
+        //    MemA[address,4] = PCStoreValue();
+        if (BitIsSet (registers, 15))
+        {
+            Register pc_reg;
+            pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc);
+            context.SetRegisterPlusOffset (pc_reg, 8);
+            const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
+            if (!success)
+                return false;
+                  
+            if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size))
+                return false;
+        }
+                  
+        // if wback then R[n] = R[n] - 4*BitCount(registers);
+        if (wback)
+        {
+            offset = addr_byte_size * BitCount (registers);
+            context.type = EmulateInstruction::eContextAdjustBaseRegister;
+            context.SetImmediateSigned (offset);
+            addr_t data = address + offset;
+            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
+                return false;
+        }
+    }
+    return true;
+}
+                  
 EmulateInstructionARM::ARMOpcode*
 EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
 {
@@ -2952,7 +3080,9 @@
         //----------------------------------------------------------------------
         // Store instructions
         //----------------------------------------------------------------------
-        { 0x0fd00000, 0x08800000, ARMvAll,      eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }
+        { 0x0fd00000, 0x08800000, ARMvAll,      eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
+        { 0x0fd00000, 0x08000000, ARMvAll,      eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" }
+                  
         
     };
     static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);

Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=125542&r1=125541&r2=125542&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Mon Feb 14 18:19:42 2011
@@ -322,6 +322,9 @@
     bool
     EmulateSTM (ARMEncoding encoding);
     
+    bool
+    EmulateSTMDA (ARMEncoding encoding);
+    
     uint32_t m_arm_isa;
     Mode m_inst_mode;
     uint32_t m_inst_cpsr;