[Lldb-commits] [lldb] r125303 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
Johnny Chen
johnny.chen at apple.com
Thu Feb 10 11:54:05 PST 2011
Author: johnny
Date: Thu Feb 10 13:54:05 2011
New Revision: 125303
URL: http://llvm.org/viewvc/llvm-project?rev=125303&view=rev
Log:
Some refactorings to use the convenience function: Bits32(const uint32_t value, const uint32_t bit).
Modified:
lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=125303&r1=125302&r2=125303&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original)
+++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Thu Feb 10 13:54:05 2011
@@ -191,7 +191,7 @@
case eEncodingT1:
registers = Bits32(opcode, 7, 0);
// The M bit represents LR.
- if (Bits32(opcode, 8, 8))
+ if (Bits32(opcode, 8))
registers |= (1u << 14);
// if BitCount(registers) < 1 then UNPREDICTABLE;
if (BitCount(registers) < 1)
@@ -311,7 +311,7 @@
case eEncodingT1:
registers = Bits32(opcode, 7, 0);
// The P bit represents PC.
- if (Bits32(opcode, 8, 8))
+ if (Bits32(opcode, 8))
registers |= (1u << 15);
// if BitCount(registers) < 1 then UNPREDICTABLE;
if (BitCount(registers) < 1)
@@ -321,7 +321,7 @@
// Ignore bit 13.
registers = Bits32(opcode, 15, 0) & ~0x2000;
// if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
- if (BitCount(registers) < 2 || (Bits32(opcode, 15, 15) && Bits32(opcode, 14, 14)))
+ if (BitCount(registers) < 2 || (Bits32(opcode, 15) && Bits32(opcode, 14)))
return false;
break;
case eEncodingT3:
@@ -338,7 +338,7 @@
// if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;
// if registers<13> == â1â && ArchVersion() >= 7 then UNPREDICTABLE;
- if (Bits32(opcode, 13, 13))
+ if (Bits32(opcode, 13) && ArchVersion() >= ARMv7)
return false;
break;
case eEncodingA2:
@@ -555,7 +555,7 @@
switch (encoding) {
case eEncodingT1:
Rm = Bits32(opcode, 6, 3);
- Rd = Bits32(opcode, 7, 7) << 3 | Bits32(opcode, 2, 1);
+ Rd = Bits32(opcode, 7) << 3 | Bits32(opcode, 2, 1);
setflags = false;
break;
case eEncodingT2:
@@ -822,10 +822,10 @@
case eEncodingT1:
{
lr = (pc + 4) | 1u; // return address
- uint32_t S = Bits32(opcode, 26, 26);
+ uint32_t S = Bits32(opcode, 26);
uint32_t imm10 = Bits32(opcode, 25, 16);
- uint32_t J1 = Bits32(opcode, 13, 13);
- uint32_t J2 = Bits32(opcode, 11, 11);
+ uint32_t J1 = Bits32(opcode, 13);
+ uint32_t J2 = Bits32(opcode, 11);
uint32_t imm11 = Bits32(opcode, 10, 0);
uint32_t I1 = !(J1 ^ S);
uint32_t I2 = !(J2 ^ S);
@@ -839,10 +839,10 @@
case eEncodingT2:
{
lr = (pc + 4) | 1u; // return address
- uint32_t S = Bits32(opcode, 26, 26);
+ uint32_t S = Bits32(opcode, 26);
uint32_t imm10H = Bits32(opcode, 25, 16);
- uint32_t J1 = Bits32(opcode, 13, 13);
- uint32_t J2 = Bits32(opcode, 11, 11);
+ uint32_t J1 = Bits32(opcode, 13);
+ uint32_t J2 = Bits32(opcode, 11);
uint32_t imm10L = Bits32(opcode, 10, 1);
uint32_t I1 = !(J1 ^ S);
uint32_t I2 = !(J2 ^ S);
@@ -1232,7 +1232,7 @@
case eEncodingT1:
case eEncodingA1:
single_regs = false;
- d = Bits32(opcode, 22, 22) << 4 | Bits32(opcode, 15, 12);
+ d = Bits32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
// If UInt(imm8) is odd, see "FSTMX".
regs = Bits32(opcode, 7, 0) / 2;
@@ -1243,7 +1243,7 @@
case eEncodingT2:
case eEncodingA2:
single_regs = true;
- d = Bits32(opcode, 15, 12) << 1 | Bits32(opcode, 22, 22);
+ d = Bits32(opcode, 15, 12) << 1 | Bits32(opcode, 22);
imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
regs = Bits32(opcode, 7, 0);
// if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
@@ -1326,7 +1326,7 @@
case eEncodingT1:
case eEncodingA1:
single_regs = false;
- d = Bits32(opcode, 22, 22) << 4 | Bits32(opcode, 15, 12);
+ d = Bits32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
// If UInt(imm8) is odd, see "FLDMX".
regs = Bits32(opcode, 7, 0) / 2;
@@ -1337,7 +1337,7 @@
case eEncodingT2:
case eEncodingA2:
single_regs = true;
- d = Bits32(opcode, 15, 12) << 1 | Bits32(opcode, 22, 22);
+ d = Bits32(opcode, 15, 12) << 1 | Bits32(opcode, 22);
imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
regs = Bits32(opcode, 7, 0);
// if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
@@ -1487,10 +1487,10 @@
case eEncodingT3:
// The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
{
- uint32_t S = Bits32(opcode, 26, 26);
+ uint32_t S = Bits32(opcode, 26);
uint32_t imm6 = Bits32(opcode, 21, 16);
- uint32_t J1 = Bits32(opcode, 13, 13);
- uint32_t J2 = Bits32(opcode, 11, 11);
+ uint32_t J1 = Bits32(opcode, 13);
+ uint32_t J2 = Bits32(opcode, 11);
uint32_t imm11 = Bits32(opcode, 10, 0);
uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
imm32 = llvm::SignExtend32<21>(imm21);
@@ -1501,10 +1501,10 @@
}
case eEncodingT4:
{
- uint32_t S = Bits32(opcode, 26, 26);
+ uint32_t S = Bits32(opcode, 26);
uint32_t imm10 = Bits32(opcode, 25, 16);
- uint32_t J1 = Bits32(opcode, 13, 13);
- uint32_t J2 = Bits32(opcode, 11, 11);
+ uint32_t J1 = Bits32(opcode, 13);
+ uint32_t J2 = Bits32(opcode, 11);
uint32_t imm11 = Bits32(opcode, 10, 0);
uint32_t I1 = !(J1 ^ S);
uint32_t I2 = !(J2 ^ S);
@@ -1563,7 +1563,7 @@
bool nonzero;
switch (encoding) {
case eEncodingT1:
- imm32 = Bits32(opcode, 9, 9) << 6 | Bits32(opcode, 7, 3) << 1;
+ imm32 = Bits32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
nonzero = BitIsSet(opcode, 11);
target = pc + 4 + imm32;
context.arg1 = 4 + imm32; // signed offset
@@ -1615,7 +1615,7 @@
{
case eEncodingT2:
// setflags = FALSE
- Rd = Rn = Bits32(opcode, 7, 7) << 3 | Bits32(opcode, 2, 0);
+ Rd = Rn = Bits32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
Rm = Bits32(opcode, 6, 3);
if (Rn == 15 && Rm == 15)
return false;
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