[Lldb-commits] [lldb] r124141 - in /lldb/trunk/source/Plugins/Process/Utility: ARMUtils.h EmulateInstructionARM.cpp

[Johnny Chen]

Author: johnny
Date: Mon Jan 24 13:50:30 2011
New Revision: 124141

URL: http://llvm.org/viewvc/llvm-project?rev=124141&view=rev
Log:
Move some #define's to the ARMUtils.h header file.

Modified:
    lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h
    lldb/trunk/source/Plugins/Process/Utility/EmulateInstructionARM.cpp

Modified: lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h?rev=124141&r1=124140&r2=124141&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h (original)
+++ lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h Mon Jan 24 13:50:30 2011
@@ -10,10 +10,46 @@
 #ifndef lldb_ARMUtils_h_
 #define lldb_ARMUtils_h_
 
-// Utility functions for the ARM/Thumb Instruction Set Architecture.
+// Common utilities for the ARM/Thumb Instruction Set Architecture.
 
 namespace lldb_private {
 
+// ARM conditions
+#define COND_EQ     0x0
+#define COND_NE     0x1
+#define COND_CS     0x2
+#define COND_HS     0x2
+#define COND_CC     0x3
+#define COND_LO     0x3
+#define COND_MI     0x4
+#define COND_PL     0x5
+#define COND_VS     0x6
+#define COND_VC     0x7
+#define COND_HI     0x8
+#define COND_LS     0x9
+#define COND_GE     0xA
+#define COND_LT     0xB
+#define COND_GT     0xC
+#define COND_LE     0xD
+#define COND_AL     0xE
+#define COND_UNCOND 0xF
+
+// Masks for CPSR
+#define MASK_CPSR_MODE_MASK     (0x0000001fu)
+#define MASK_CPSR_T         (1u << 5)
+#define MASK_CPSR_F         (1u << 6)
+#define MASK_CPSR_I         (1u << 7)
+#define MASK_CPSR_A         (1u << 8)
+#define MASK_CPSR_E         (1u << 9)
+#define MASK_CPSR_GE_MASK   (0x000f0000u)
+#define MASK_CPSR_J         (1u << 24)
+#define MASK_CPSR_Q         (1u << 27)
+#define MASK_CPSR_V         (1u << 28)
+#define MASK_CPSR_C         (1u << 29)
+#define MASK_CPSR_Z         (1u << 30)
+#define MASK_CPSR_N         (1u << 31)
+
+
 // This function performs the check for the register numbers 13 and 15 that are
 // not permitted for many Thumb register specifiers.
 static inline bool BadReg(uint32_t n) { return n == 13 || n == 15; }

Modified: lldb/trunk/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/EmulateInstructionARM.cpp?rev=124141&r1=124140&r2=124141&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Process/Utility/EmulateInstructionARM.cpp (original)
+++ lldb/trunk/source/Plugins/Process/Utility/EmulateInstructionARM.cpp Mon Jan 24 13:50:30 2011
@@ -19,42 +19,6 @@
 #define PC_REG          15
 #define PC_REGLIST_BIT  0x8000
 
-// ARM conditions
-#define COND_EQ     0x0
-#define COND_NE     0x1
-#define COND_CS     0x2
-#define COND_HS     0x2
-#define COND_CC     0x3
-#define COND_LO     0x3
-#define COND_MI     0x4
-#define COND_PL     0x5
-#define COND_VS     0x6
-#define COND_VC     0x7
-#define COND_HI     0x8
-#define COND_LS     0x9
-#define COND_GE     0xA
-#define COND_LT     0xB
-#define COND_GT     0xC
-#define COND_LE     0xD
-#define COND_AL     0xE
-#define COND_UNCOND 0xF
-
-
-#define MASK_CPSR_MODE_MASK     (0x0000001fu)
-#define MASK_CPSR_T         (1u << 5)
-#define MASK_CPSR_F         (1u << 6)
-#define MASK_CPSR_I         (1u << 7)
-#define MASK_CPSR_A         (1u << 8)
-#define MASK_CPSR_E         (1u << 9)
-#define MASK_CPSR_GE_MASK   (0x000f0000u)
-#define MASK_CPSR_J         (1u << 24)
-#define MASK_CPSR_Q         (1u << 27)
-#define MASK_CPSR_V         (1u << 28)
-#define MASK_CPSR_C         (1u << 29)
-#define MASK_CPSR_Z         (1u << 30)
-#define MASK_CPSR_N         (1u << 31)
-
-
 #define ARMv4     (1u << 0)
 #define ARMv4T    (1u << 1)
 #define ARMv5T    (1u << 2)