[libcxx-commits] [clang] [libcxx] [llvm] [CLANG][LIBCXX][LLVM] Partial program correctness. P1494R5, P3641R0 (PR #237335)

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@@ -7950,8 +7950,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
   case Intrinsic::experimental_noalias_scope_decl:
   case Intrinsic::var_annotation:
   case Intrinsic::sideeffect:
-    // Discard annotate attributes, noalias scope declarations, assumptions, and
-    // artificial side-effects.
+  case Intrinsic::observable_checkpoint:
+    // Discard annotate attributes, noalias scope declarations, assumptions,
+    // artificial side-effects, and observable checkpoints.
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DenisGZM wrote:

It can hoist instructions upper previous checkpoint slot, yes. But what do you mean by undefined behavior in terms of platform specific MIR, if I get it right and you're talking about MIR-level machine scheduler.

https://github.com/llvm/llvm-project/pull/237335