[libcxx-commits] [libcxx] [libcxx] Implementation of P1831R1 (PR #101439)

[Josh Karns via libcxx-commits]

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@@ -74,7 +74,7 @@ struct atomic<_Tp*> : public __atomic_base<_Tp*> {
   _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR atomic(_Tp* __d) _NOEXCEPT : __base(__d) {}
 
   _LIBCPP_HIDE_FROM_ABI _Tp* operator=(_Tp* __d) volatile _NOEXCEPT
-    requires __base::is_always_lock_free
+    _LIBCPP_REQUIRE_IS_ALWAYS_LOCK_FREE
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jkarns275 wrote:

I understand that it is not a guarantee, but I am not sure I an write a test that will run on any ISAs i have access to since ARM and x86 both have instructions to atomically write 16 bytes of data.

Perhaps I can restrict the test to MIPS or some simpler architecture? I'm not familiar enough with the testing infrastructure to know the correct manner to proceed here.

https://github.com/llvm/llvm-project/pull/101439