[libcxx-commits] [PATCH] D156642: libunwind: riscv: disable vector test when __riscv_v not defined

[Sean Cross via Phabricator via libcxx-commits]

xobs added a comment.

My configuration is building libunwind via the Rust build system. This links libunwind into compiled programs in order to unwind the stack.

The build command is:

  running: "riscv-none-elf-gcc" "-O3" "-ffunction-sections" "-fdata-sections" "-fPIC" "-march=rv32imac" "-mabi=ilp32" "-mcmodel=medany" "-static" "-I" "/opt/Xous/rust-next/src/llvm-project/libunwind/include" "-nostdinc++" "-fno-exceptions" "-fno-rtti" "-fstrict-aliasing" "-funwind-tables" "-fvisibility=hidden" "-fno-stack-protector" "-ffreestanding" "-U_FORTIFY_SOURCE" "-std=c++11" "-D_LIBUNWIND_DISABLE_VISIBILITY_ANNOTATIONS" "-D_FORTIFY_SOURCE=0" "-DRUST_SGX=1" "-D__NO_STRING_INLINES" "-D__NO_MATH_INLINES" "-D_LIBUNWIND_IS_BAREMETAL" "-D__LIBUNWIND_IS_NATIVE_ONLY" "-D_LIBUNWIND_REMEMBER_HEAP_ALLOC" "-DNDEBUG" "-o" "/opt/Xous/rust-next/build/riscv32imac-unknown-xous-elf/native/libunwind/libunwind.o" "-c" "/opt/Xous/rust-next/src/llvm-project/libunwind/src/libunwind.cpp"
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp: Assembler messages:
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp:4106: Error: unrecognized opcode `csrr a0,0xC22'
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp:4106: Error: unrecognized opcode `csrr a5,0xC22'
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp:4106: Error: unrecognized opcode `csrr a4,0xC22'
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp:4106: Error: unrecognized opcode `csrr a0,0xC22'
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp:4106: Error: unrecognized opcode `csrr s4,0xC22'
  cargo:warning=/opt/Xous/rust-next/src/llvm-project/libunwind/src/Registers.hpp:4106: Error: unrecognized opcode `csrr a0,0xC22'
  exit status: 1

The arch is either "rv32imac" or "rv32imac_zicsr" depending on the underlying version of the compiler, however note that "rv32imac" is still a perfectly valid target -- it just has no CSR opcodes.

Ultimately I would like this to build for "rv32imac", and the patch provided accomplishes that.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D156642