[libcxx-commits] [PATCH] D136257: [libc++abi][AIX] Use reserved slot in stack to pass the address of exception object
Xing Xue via Phabricator via libcxx-commits
libcxx-commits at lists.llvm.org
Wed Oct 19 07:23:12 PDT 2022
xingxue created this revision.
xingxue added reviewers: ldionne, MaskRay, compnerd, hubert.reinterpretcast, cebowleratibm, daltenty.
xingxue added a project: LLVM.
Herald added a subscriber: StephenFan.
Herald added a project: All.
xingxue requested review of this revision.
Herald added a project: libc++abi.
Herald added a subscriber: libcxx-commits.
Herald added a reviewer: libc++abi.
The existing implementation of the personality for legacy IBM xlclang++ compiler generated code passes the address of exception object in r14 for the landing pad to retrieve with a call to `__xlc_exception_handle()`. This clobbers the content of r14 in user code (and potentially, when running cleanup actions, the address of another exception object being passed). This patch changes to use the stack slot reserved for compilers to pass the address. It has been confirmed that xlclang++-generated code does not use this slot. The following is the AIX stack frame layout.
Low Address
SP----> +---------------------------------------+
| back chain to caller | 0 0
+---------------------------------------+
| saved CR | 4 8 (8-11)
+---------------------------------------+
| saved LR | 8 16
+---------------------------------------+
| reserved for compilers | 12 24 <=======
+---------------------------------------+
| reserved for binders | 16 32
+---------------------------------------+
| saved TOC pointer | 20 40
+---------------------------------------+
| Parameter save area (+padding*) (P) | 24 48
+---------------------------------------+
| Alloca space (A) | 24+P etc.
+---------------------------------------+
| Local variable space (L) | 24+P+A
+---------------------------------------+
| Float/int conversion temporary (X) | 24+P+A+L
+---------------------------------------+
| Save area for AltiVec registers (W) | 24+P+A+L+X
+---------------------------------------+
| AltiVec alignment padding (Y) | 24+P+A+L+X+W
+---------------------------------------+
| Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
+---------------------------------------+
| Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
+---------------------------------------+
| Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
+---------------------------------------+
old SP->| back chain to caller's caller |
+---------------------------------------+
| saved CR | 4 8 (8-11)
+---------------------------------------+
| saved LR | 8 16
+---------------------------------------+
High Address
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D136257
Files:
libcxxabi/src/aix_state_tab_eh.inc
libcxxabi/test/vendor/ibm/Inputs/aix_xlclang_nested_excp.cpp
libcxxabi/test/vendor/ibm/Inputs/aix_xlclang_nested_excp_32.o
libcxxabi/test/vendor/ibm/Inputs/aix_xlclang_nested_excp_64.o
libcxxabi/test/vendor/ibm/aix_xlclang_nested_excp_32.sh.cpp
libcxxabi/test/vendor/ibm/aix_xlclang_nested_excp_64.sh.cpp
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