[libcxx-commits] [PATCH] D80690: [RISCV] Support libunwind for riscv32

[Kito Cheng via Phabricator via libcxx-commits]

kito-cheng added inline comments.


================
Comment at: libunwind/include/__libunwind_config.h:132
 #    define _LIBUNWIND_TARGET_RISCV 1
-#    define _LIBUNWIND_CONTEXT_SIZE 64
+#    define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + __riscv_flen) / 64)
 #    define _LIBUNWIND_CURSOR_SIZE 76
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kamleshbhalui wrote:
> luismarques wrote:
> > This doesn't seem correct.
> OK so it appears that in principle we could have 4 combinations 
> 
> ILP32 + "f" : xlen = 32, flen = 32
> ILP32 + "fd" : xlen = 32, flen = 64
> LP64 + "f" : xlen = 64, flen = 32
> LP64 + "fd" : xlen = 64, flen = 64
> 
> So instead of having fixed size area for each kind of register thought of having packed size.
> please point me where it can cause problem?
> 
> 
I am not family with libunwind and don't know what's _LIBUNWIND_CURSOR_SIZE , but I am curious about does here different value for xlen=32/flen=and xlen=64/flen=0?

And I think add an #else + #error to catch any unsupported value would be better, since the flen could be 128 (Q), although LLVM didn't implement yet, but in case we implemented in future we'll know we need fix here.


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  https://reviews.llvm.org/D80690/new/

https://reviews.llvm.org/D80690