[libcxx-commits] [libcxx] r366868 - [RISCV] Implement benchmark::cycleclock::Now

[Hans Wennborg via libcxx-commits]

Merged to release_90 in r367813.

On Sat, Jul 27, 2019 at 4:13 PM Roger Ferrer Ibanez via libcxx-commits
<libcxx-commits at lists.llvm.org> wrote:
>
> Author: rogfer01
> Date: Tue Jul 23 22:33:46 2019
> New Revision: 366868
>
> URL: http://llvm.org/viewvc/llvm-project?rev=366868&view=rev
> Log:
> [RISCV] Implement benchmark::cycleclock::Now
>
> This is a cherrypick of D64237 onto llvm/utils/benchmark and
> libcxx/utils/google-benchmark.
>
> Differential Revision: https://reviews.llvm.org/D65142
>
> Modified:
>     libcxx/trunk/utils/google-benchmark/README.LLVM
>     libcxx/trunk/utils/google-benchmark/src/cycleclock.h
>
> Modified: libcxx/trunk/utils/google-benchmark/README.LLVM
> URL: http://llvm.org/viewvc/llvm-project/libcxx/trunk/utils/google-benchmark/README.LLVM?rev=366868&r1=366867&r2=366868&view=diff
> ==============================================================================
> --- libcxx/trunk/utils/google-benchmark/README.LLVM (original)
> +++ libcxx/trunk/utils/google-benchmark/README.LLVM Tue Jul 23 22:33:46 2019
> @@ -4,3 +4,9 @@ LLVM notes
>  This directory contains the Google Benchmark source code with some unnecessary
>  files removed. Note that this directory is under a different license than
>  libc++.
> +
> +Changes:
> +* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
> +  is applied on top of
> +  https://github.com/google/benchmark/commit/4528c76b718acc9b57956f63069c699ae21edcab
> +  to add RISC-V timer support.
>
> Modified: libcxx/trunk/utils/google-benchmark/src/cycleclock.h
> URL: http://llvm.org/viewvc/llvm-project/libcxx/trunk/utils/google-benchmark/src/cycleclock.h?rev=366868&r1=366867&r2=366868&view=diff
> ==============================================================================
> --- libcxx/trunk/utils/google-benchmark/src/cycleclock.h (original)
> +++ libcxx/trunk/utils/google-benchmark/src/cycleclock.h Tue Jul 23 22:33:46 2019
> @@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t N
>    uint64_t tsc;
>    asm("stck %0" : "=Q"(tsc) : : "cc");
>    return tsc;
> +#elif defined(__riscv) // RISC-V
> +  // Use RDCYCLE (and RDCYCLEH on riscv32)
> +#if __riscv_xlen == 32
> +  uint64_t cycles_low, cycles_hi0, cycles_hi1;
> +  asm("rdcycleh %0" : "=r"(cycles_hi0));
> +  asm("rdcycle %0" : "=r"(cycles_lo));
> +  asm("rdcycleh %0" : "=r"(cycles_hi1));
> +  // This matches the PowerPC overflow detection, above
> +  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
> +  return (cycles_hi1 << 32) | cycles_lo;
> +#else
> +  uint64_t cycles;
> +  asm("rdcycle %0" : "=r"(cycles));
> +  return cycles;
> +#endif
>  #else
>  // The soft failover to a generic implementation is automatic only for ARM.
>  // For other platforms the developer is expected to make an attempt to create
>
>
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