[Libclc-dev] [PATCH v3 1/1] R600: Add new intrinsic to read work dimensions

[Jan Vesely]

v2: Add SI lowering
    Add test

v3: Work dimensions after the kernel arguments.

Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
---

I stayed with the r600_ prefix for now. I think it'd be better to do
one big rename than mix different prefixes


 include/llvm/IR/IntrinsicsR600.td         |  2 ++
 lib/Target/R600/R600ISelLowering.cpp      |  4 ++++
 lib/Target/R600/SIISelLowering.cpp        |  4 ++++
 test/CodeGen/R600/work-item-intrinsics.ll | 16 ++++++++++++++++
 4 files changed, 26 insertions(+)

diff --git a/include/llvm/IR/IntrinsicsR600.td b/include/llvm/IR/IntrinsicsR600.td
index ba69eaa..37a9771 100644
--- a/include/llvm/IR/IntrinsicsR600.td
+++ b/include/llvm/IR/IntrinsicsR600.td
@@ -33,6 +33,8 @@ defm int_r600_read_tgid : R600ReadPreloadRegisterIntrinsic_xyz <
                                        "__builtin_r600_read_tgid">;
 defm int_r600_read_tidig : R600ReadPreloadRegisterIntrinsic_xyz <
                                        "__builtin_r600_read_tidig">;
+def int_r600_read_workdim : R600ReadPreloadRegisterIntrinsic <
+                                       "__builtin_r600_read_workdim">;
 
 } // End TargetPrefix = "r600"
 
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index 8877cc8..a04a20e 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -805,6 +805,10 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
       return LowerImplicitParameter(DAG, VT, DL, 7);
     case Intrinsic::r600_read_local_size_z:
       return LowerImplicitParameter(DAG, VT, DL, 8);
+    case Intrinsic::r600_read_workdim: {
+      const size_t arg_size = DAG.getMachineFunction().getFunction()->arg_size();
+      return LowerImplicitParameter(DAG, VT, DL, 9 + arg_size);
+    }
 
     case Intrinsic::r600_read_tgid_x:
       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index f7717da..e156d84 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -864,6 +864,10 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
   case Intrinsic::r600_read_local_size_z:
     return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
+  case Intrinsic::r600_read_workdim: {
+    const size_t arg_size = DAG.getMachineFunction().getFunction()->arg_size();
+    return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 36 + (arg_size * 4), false);
+  }
   case Intrinsic::r600_read_tgid_x:
     return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
       AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0), VT);
diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll
index 1dbd9b8..7322510 100644
--- a/test/CodeGen/R600/work-item-intrinsics.ll
+++ b/test/CodeGen/R600/work-item-intrinsics.ll
@@ -128,6 +128,20 @@ entry:
   ret void
 }
 
+; FUNC-LABEL: @get_work_dim
+; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
+; EG: MOV [[VAL]], KC0[2].Z
+
+; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0xa
+; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; SI: BUFFER_STORE_DWORD [[VVAL]]
+define void @get_work_dim (i32 addrspace(1)* %out) {
+entry:
+  %0 = call i32 @llvm.r600.read.workdim() #0
+  store i32 %0, i32 addrspace(1)* %out
+  ret void
+}
+
 ; The tgid values are stored in sgprs offset by the number of user sgprs.
 ; Currently we always use exactly 2 user sgprs for the pointer to the
 ; kernel arguments, but this may change in the future.
@@ -209,4 +223,6 @@ declare i32 @llvm.r600.read.tidig.x() #0
 declare i32 @llvm.r600.read.tidig.y() #0
 declare i32 @llvm.r600.read.tidig.z() #0
 
+declare i32 @llvm.r600.read.workdim() #0
+
 attributes #0 = { readnone }
-- 
1.9.3