[libc-commits] [libc] [libc][ARM] Defend banked SP setup against register allocator (PR #206757)

[Simon Tatham via libc-commits]

statham-arm wrote:

I don't think I'd call it a codegen bug. The only problem with the compiler code generation is that it's not taking account of the mode switch effectively corrupting registers. You could imagine trying to work around it more minimally by rewriting each mode switch as an asm statement mentioning which registers it clobbers:
```c
asm volatile("mov cpsr_c,%0" : : "r"(0x1f) : "lr");
```
But I don't think it's reasonable to expect the compiler to figure that out for itself when it sees `__arm_wsr`, because the register-clobbering effects of a write to CPSR_c in general depend on what _value_ you're writing, which isn't reliably known at compile time. Even worse, they depend on what value was in CPSR_c beforehand, because a switch to _or from_ FIQ mode banks r8 and above as well as sp/lr. Conversely, there are other bits you might want to change in CPSR_c which don't trigger a bank switch at all, like disabling interrupts, which if you're doing it at all you're probably doing it in a hurry and wouldn't appreciate a precautionary assumption that half your registers were clobbered.

I think you could only put the responsibility on the compiler to anticipate and avoid register bank switches if you were willing to statically track the CPU mode at every instant in the program, which would need a completely different source syntax!

https://github.com/llvm/llvm-project/pull/206757