[libc-commits] [clang] [libc] [llvm] AMDGPU: Add a subtarget feature for fine-grained remote memory support (PR #96442)

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git-clang-format --diff 87de49753d4bd860fed5165e9411c703107ad3a5 8a87e14737f121a931fe7f1b15f5263627fc883d -- llvm/include/llvm/CodeGen/MachineBranchProbabilityInfo.h llvm/include/llvm/InitializePasses.h llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/lib/CodeGen/BranchFolding.cpp llvm/lib/CodeGen/EarlyIfConversion.cpp llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp llvm/lib/CodeGen/IfConversion.cpp llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp llvm/lib/CodeGen/MachineBlockPlacement.cpp llvm/lib/CodeGen/MachineBranchProbabilityInfo.cpp llvm/lib/CodeGen/MachineSink.cpp llvm/lib/CodeGen/MachineTraceMetrics.cpp llvm/lib/CodeGen/TailDuplication.cpp llvm/lib/Passes/PassBuilder.cpp llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp llvm/lib/Target/AMDGPU/GCNSubtarget.h llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
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diff --git a/llvm/include/llvm/CodeGen/MachineBranchProbabilityInfo.h b/llvm/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
index bd544421bc..236d5e8b42 100644
--- a/llvm/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
@@ -60,7 +60,6 @@ public:
                                     const MachineBasicBlock *Src,
                                     const MachineBasicBlock *Dst) const;
 };
-
 }
 
 
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 4ddb7112a4..c44aa8c6d6 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -182,7 +182,7 @@ void initializeMIRPrintingPassPass(PassRegistry&);
 void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
 void initializeMachineBlockPlacementPass(PassRegistry&);
 void initializeMachineBlockPlacementStatsPass(PassRegistry&);
-void initializeMachineBranchProbabilityInfoPass(PassRegistry&);
+void initializeMachineBranchProbabilityInfoPass(PassRegistry &);
 void initializeMachineCFGPrinterPass(PassRegistry &);
 void initializeMachineCSEPass(PassRegistry&);
 void initializeMachineCombinerPass(PassRegistry&);
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 03f6882e68..b10435db59 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -1056,8 +1056,8 @@ bool HexagonEarlyIfConversion::runOnMachineFunction(MachineFunction &MF) {
   MRI = &MF.getRegInfo();
   MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
   MLI = &getAnalysis<MachineLoopInfo>();
-  MBPI = EnableHexagonBP ? &getAnalysis<MachineBranchProbabilityInfo>() :
-    nullptr;
+  MBPI =
+      EnableHexagonBP ? &getAnalysis<MachineBranchProbabilityInfo>() : nullptr;
 
   Deleted.clear();
   bool Changed = false;

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https://github.com/llvm/llvm-project/pull/96442