[libc-commits] [clang-tools-extra] [clang] [libcxx] [compiler-rt] [lldb] [llvm] [flang] [lld] [libc] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
Philip Reames via libc-commits
libc-commits at lists.llvm.org
Thu Feb 1 11:15:28 PST 2024
================
@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+ case TTI::SK_ExtractSubvector:
+ if (isa<FixedVectorType>(SubTp)) {
+ unsigned TpRegs = getRegUsageForType(Tp);
+ unsigned NumElems =
+ divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+ // Whole vector extract - just the vector itself + (possible) vsetvli.
+ // TODO: consider adding the cost for vsetvli.
+ if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
----------------
preames wrote:
I think this check would be more clearly expressed as an and of the following clauses
a) ST->getRealMaxVLen() == ST->getRealMinVLen()
b) NumElems * ElementSizeInBits == VLEN
c) Index % NumElems == 0
Note that this only supports m1 full extracts. But starting there and extending it to m2, and m4 later seems entirely reasonable.
https://github.com/llvm/llvm-project/pull/80164
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