[libc-commits] [libc] e3087c4 - [libc] Start to refactor riscv platform abstraction to support both 32 and 64 bits versions
Mikhail R. Gadelha via libc-commits
libc-commits at lists.llvm.org
Tue Sep 26 08:32:48 PDT 2023
Author: Mikhail R. Gadelha
Date: 2023-09-26T12:32:25-03:00
New Revision: e3087c4b8cee20094c1a72b94b0a7f5f543cf37d
URL: https://github.com/llvm/llvm-project/commit/e3087c4b8cee20094c1a72b94b0a7f5f543cf37d
DIFF: https://github.com/llvm/llvm-project/commit/e3087c4b8cee20094c1a72b94b0a7f5f543cf37d.diff
LOG: [libc] Start to refactor riscv platform abstraction to support both 32 and 64 bits versions
This patch enables the compilation of libc for rv32 by unifying the
current rv64 and rv32 implementation into a single rv implementation.
We updated the cmake file to match the new riscv32 arch and force
LIBC_TARGET_ARCHITECTURE to be "riscv" whenever we find "riscv32" or
"riscv64". This is required as LIBC_TARGET_ARCHITECTURE is used in the
path for several platform specific implementations.
Reviewed By: michaelrj
Differential Revision: https://reviews.llvm.org/D148797
Added:
libc/config/baremetal/riscv/entrypoints.txt
libc/config/baremetal/riscv/headers.txt
libc/config/linux/riscv/entrypoints.txt
libc/config/linux/riscv/headers.txt
libc/src/__support/FPUtil/riscv/FEnvImpl.h
libc/src/__support/FPUtil/riscv/FMA.h
libc/src/__support/FPUtil/riscv/sqrt.h
libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
libc/src/__support/OSUtil/linux/riscv/syscall.h
libc/src/setjmp/riscv/CMakeLists.txt
libc/src/setjmp/riscv/longjmp.cpp
libc/src/setjmp/riscv/setjmp.cpp
libc/startup/linux/riscv/CMakeLists.txt
libc/startup/linux/riscv/start.cpp
Modified:
libc/cmake/modules/LLVMLibCArchitectures.cmake
libc/config/linux/app.h
libc/src/__support/FPUtil/FEnvImpl.h
libc/src/__support/FPUtil/FMA.h
libc/src/__support/FPUtil/sqrt.h
libc/src/__support/OSUtil/linux/syscall.h
libc/src/__support/macros/properties/architectures.h
libc/src/__support/threads/linux/thread.cpp
libc/src/__support/threads/thread.h
libc/test/src/fenv/enabled_exceptions_test.cpp
libc/test/src/fenv/feenableexcept_test.cpp
libc/test/src/fenv/feholdexcept_test.cpp
Removed:
libc/config/baremetal/riscv32/entrypoints.txt
libc/config/baremetal/riscv32/headers.txt
libc/config/linux/riscv64/entrypoints.txt
libc/config/linux/riscv64/headers.txt
libc/src/__support/FPUtil/riscv32/FEnvImpl.h
libc/src/__support/FPUtil/riscv64/FEnvImpl.h
libc/src/__support/FPUtil/riscv64/FMA.h
libc/src/__support/FPUtil/riscv64/sqrt.h
libc/src/__support/OSUtil/linux/riscv64/CMakeLists.txt
libc/src/__support/OSUtil/linux/riscv64/syscall.h
libc/src/setjmp/riscv64/CMakeLists.txt
libc/src/setjmp/riscv64/longjmp.cpp
libc/src/setjmp/riscv64/setjmp.cpp
libc/startup/linux/riscv64/CMakeLists.txt
libc/startup/linux/riscv64/start.cpp
################################################################################
diff --git a/libc/cmake/modules/LLVMLibCArchitectures.cmake b/libc/cmake/modules/LLVMLibCArchitectures.cmake
index 89b5f2d38fb36ae..10571101a341785 100644
--- a/libc/cmake/modules/LLVMLibCArchitectures.cmake
+++ b/libc/cmake/modules/LLVMLibCArchitectures.cmake
@@ -150,10 +150,12 @@ elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "aarch64")
set(LIBC_TARGET_ARCHITECTURE_IS_AARCH64 TRUE)
elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "x86_64")
set(LIBC_TARGET_ARCHITECTURE_IS_X86 TRUE)
-elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv32")
- set(LIBC_TARGET_ARCHITECTURE_IS_RISCV32 TRUE)
elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv64")
set(LIBC_TARGET_ARCHITECTURE_IS_RISCV64 TRUE)
+ set(LIBC_TARGET_ARCHITECTURE "riscv")
+elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv32")
+ set(LIBC_TARGET_ARCHITECTURE_IS_RISCV32 TRUE)
+ set(LIBC_TARGET_ARCHITECTURE "riscv")
else()
message(FATAL_ERROR
"Unsupported libc target architecture ${LIBC_TARGET_ARCHITECTURE}")
diff --git a/libc/config/baremetal/riscv32/entrypoints.txt b/libc/config/baremetal/riscv/entrypoints.txt
similarity index 100%
rename from libc/config/baremetal/riscv32/entrypoints.txt
rename to libc/config/baremetal/riscv/entrypoints.txt
diff --git a/libc/config/baremetal/riscv32/headers.txt b/libc/config/baremetal/riscv/headers.txt
similarity index 100%
rename from libc/config/baremetal/riscv32/headers.txt
rename to libc/config/baremetal/riscv/headers.txt
diff --git a/libc/config/linux/app.h b/libc/config/linux/app.h
index 5521991e3e1c36d..b17026a7832a3c4 100644
--- a/libc/config/linux/app.h
+++ b/libc/config/linux/app.h
@@ -37,7 +37,7 @@ struct TLSImage {
#if defined(LIBC_TARGET_ARCH_IS_X86_64) || \
defined(LIBC_TARGET_ARCH_IS_AARCH64) || \
- defined(LIBC_TARGET_ARCH_IS_RISCV64)
+ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
// At the language level, argc is an int. But we use uint64_t as the x86_64
// ABI specifies it as an 8 byte value. Likewise, in the ARM64 ABI, arguments
// are usually passed in registers. x0 is a doubleword register, so this is
diff --git a/libc/config/linux/riscv64/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt
similarity index 100%
rename from libc/config/linux/riscv64/entrypoints.txt
rename to libc/config/linux/riscv/entrypoints.txt
diff --git a/libc/config/linux/riscv64/headers.txt b/libc/config/linux/riscv/headers.txt
similarity index 100%
rename from libc/config/linux/riscv64/headers.txt
rename to libc/config/linux/riscv/headers.txt
diff --git a/libc/src/__support/FPUtil/FEnvImpl.h b/libc/src/__support/FPUtil/FEnvImpl.h
index 8801760d887fc2e..6f2f3c75f512a3e 100644
--- a/libc/src/__support/FPUtil/FEnvImpl.h
+++ b/libc/src/__support/FPUtil/FEnvImpl.h
@@ -30,10 +30,8 @@
#include "x86_64/FEnvImpl.h"
#elif defined(LIBC_TARGET_ARCH_IS_ARM)
#include "arm/FEnvImpl.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
-#include "riscv32/FEnvImpl.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/FEnvImpl.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/FEnvImpl.h"
#else
namespace LIBC_NAMESPACE::fputil {
diff --git a/libc/src/__support/FPUtil/FMA.h b/libc/src/__support/FPUtil/FMA.h
index 32e562ab1d5e48d..0e1ede02d5cc00b 100644
--- a/libc/src/__support/FPUtil/FMA.h
+++ b/libc/src/__support/FPUtil/FMA.h
@@ -18,8 +18,8 @@
#include "x86_64/FMA.h"
#elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
#include "aarch64/FMA.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/FMA.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/FMA.h"
#elif defined(LIBC_TARGET_ARCH_IS_GPU)
#include "gpu/FMA.h"
#endif
diff --git a/libc/src/__support/FPUtil/riscv32/FEnvImpl.h b/libc/src/__support/FPUtil/riscv/FEnvImpl.h
similarity index 95%
rename from libc/src/__support/FPUtil/riscv32/FEnvImpl.h
rename to libc/src/__support/FPUtil/riscv/FEnvImpl.h
index 4b2d0ea9e6990cd..b73c4798b0539a1 100644
--- a/libc/src/__support/FPUtil/riscv32/FEnvImpl.h
+++ b/libc/src/__support/FPUtil/riscv/FEnvImpl.h
@@ -1,4 +1,4 @@
-//===-- riscv32 floating point env manipulation functions -------*- C++ -*-===//
+//===-- riscv floating point env manipulation functions ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV32_FENVIMPL_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV32_FENVIMPL_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H
+#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H
#include "src/__support/FPUtil/FPBits.h"
#include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM
@@ -177,4 +177,4 @@ LIBC_INLINE int set_env(const fenv_t *envp) {
} // namespace fputil
} // namespace LIBC_NAMESPACE
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV32_FENVIMPL_H
+#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H
diff --git a/libc/src/__support/FPUtil/riscv64/FMA.h b/libc/src/__support/FPUtil/riscv/FMA.h
similarity index 83%
rename from libc/src/__support/FPUtil/riscv64/FMA.h
rename to libc/src/__support/FPUtil/riscv/FMA.h
index 770a2342c441e7d..32bef1ea8843e15 100644
--- a/libc/src/__support/FPUtil/riscv64/FMA.h
+++ b/libc/src/__support/FPUtil/riscv/FMA.h
@@ -1,4 +1,4 @@
-//===-- RISCV64 implementations of the fma function -------------*- C++ -*-===//
+//===-- RISCV implementations of the fma function ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,14 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FMA_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FMA_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H
+#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H
#include "src/__support/macros/attributes.h" // LIBC_INLINE
#include "src/__support/macros/properties/architectures.h"
#include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
#error "Invalid include"
#endif
@@ -47,4 +47,4 @@ LIBC_INLINE cpp::enable_if_t<cpp::is_same_v<T, double>, T> fma(T x, T y, T z) {
} // namespace fputil
} // namespace LIBC_NAMESPACE
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FMA_H
+#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H
diff --git a/libc/src/__support/FPUtil/riscv64/sqrt.h b/libc/src/__support/FPUtil/riscv/sqrt.h
similarity index 82%
rename from libc/src/__support/FPUtil/riscv64/sqrt.h
rename to libc/src/__support/FPUtil/riscv/sqrt.h
index b34a099486bfc29..a42687004639b4b 100644
--- a/libc/src/__support/FPUtil/riscv64/sqrt.h
+++ b/libc/src/__support/FPUtil/riscv/sqrt.h
@@ -6,13 +6,13 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_SQRT_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_SQRT_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_SQRT_H
+#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_SQRT_H
#include "src/__support/common.h"
#include "src/__support/macros/properties/architectures.h"
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
#error "Invalid include"
#endif
@@ -36,4 +36,4 @@ template <> LIBC_INLINE double sqrt<double>(double x) {
} // namespace fputil
} // namespace LIBC_NAMESPACE
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_SQRT_H
+#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_SQRT_H
diff --git a/libc/src/__support/FPUtil/riscv64/FEnvImpl.h b/libc/src/__support/FPUtil/riscv64/FEnvImpl.h
deleted file mode 100644
index db244fc0906c52d..000000000000000
--- a/libc/src/__support/FPUtil/riscv64/FEnvImpl.h
+++ /dev/null
@@ -1,180 +0,0 @@
-//===-- riscv64 floating point env manipulation functions -------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
-
-#include "src/__support/FPUtil/FPBits.h"
-#include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM
-#include "src/__support/macros/config.h" // For LIBC_INLINE
-
-#include <fenv.h>
-#include <stdint.h>
-
-namespace LIBC_NAMESPACE {
-namespace fputil {
-
-struct FEnv {
- // We will ignore RMM and DYN rounding modes.
- static constexpr uint32_t TONEAREST = 0x0;
- static constexpr uint32_t TOWARDZERO = 0x1;
- static constexpr uint32_t DOWNWARD = 0x2;
- static constexpr uint32_t UPWARD = 0x3;
-
- // These are the bit locations of the corresponding exceptions in fcsr.
- static constexpr uint32_t INEXACT = 0x1;
- static constexpr uint32_t UNDERFLOW = 0x2;
- static constexpr uint32_t OVERFLOW = 0x4;
- static constexpr uint32_t DIVBYZERO = 0x8;
- static constexpr uint32_t INVALID = 0x10;
-
- LIBC_INLINE static uint32_t get_frm() {
- unsigned int rm;
- LIBC_INLINE_ASM("frrm %0\n\t" : "=r"(rm));
- return rm;
- }
-
- LIBC_INLINE static void set_frm(uint32_t rm) {
- LIBC_INLINE_ASM("fsrm %0, %0\n\t" : "+r"(rm));
- }
-
- LIBC_INLINE static uint32_t get_fflags() {
- unsigned int flags;
- LIBC_INLINE_ASM("frflags %0\n\t" : "=r"(flags));
- return flags;
- }
-
- LIBC_INLINE static void set_fflags(uint32_t flags) {
- LIBC_INLINE_ASM("fsflags %0, %0\n\t" : "+r"(flags));
- }
-
- LIBC_INLINE static uint32_t get_fcsr() {
- unsigned int fcsr;
- LIBC_INLINE_ASM("frcsr %0\n\t" : "=r"(fcsr));
- return fcsr;
- }
-
- LIBC_INLINE static void set_fcsr(uint32_t fcsr) {
- LIBC_INLINE_ASM("fscsr %0, %0\n\t" : "+r"(fcsr));
- }
-
- LIBC_INLINE static int exception_bits_to_macro(uint32_t status) {
- return (status & INVALID ? FE_INVALID : 0) |
- (status & DIVBYZERO ? FE_DIVBYZERO : 0) |
- (status & OVERFLOW ? FE_OVERFLOW : 0) |
- (status & UNDERFLOW ? FE_UNDERFLOW : 0) |
- (status & INEXACT ? FE_INEXACT : 0);
- }
-
- LIBC_INLINE static uint32_t exception_macro_to_bits(int except) {
- return (except & FE_INVALID ? INVALID : 0) |
- (except & FE_DIVBYZERO ? DIVBYZERO : 0) |
- (except & FE_OVERFLOW ? OVERFLOW : 0) |
- (except & FE_UNDERFLOW ? UNDERFLOW : 0) |
- (except & FE_INEXACT ? INEXACT : 0);
- }
-};
-
-// Since RISCV does not have exception enable bits, we will just return
-// the failure indicator.
-LIBC_INLINE int enable_except(int) { return -1; }
-
-// Always succeed.
-LIBC_INLINE int disable_except(int) { return 0; }
-
-// Always return "no exceptions enabled".
-LIBC_INLINE int get_except() { return 0; }
-
-LIBC_INLINE int clear_except(int excepts) {
- uint32_t flags = FEnv::get_fflags();
- uint32_t to_clear = FEnv::exception_macro_to_bits(excepts);
- flags &= ~to_clear;
- FEnv::set_fflags(flags);
- return 0;
-}
-
-LIBC_INLINE int test_except(int excepts) {
- uint32_t to_test = FEnv::exception_macro_to_bits(excepts);
- uint32_t flags = FEnv::get_fflags();
- return FEnv::exception_bits_to_macro(flags & to_test);
-}
-
-LIBC_INLINE int set_except(int excepts) {
- uint32_t flags = FEnv::get_fflags();
- FEnv::set_fflags(flags | FEnv::exception_macro_to_bits(excepts));
- return 0;
-}
-
-LIBC_INLINE int raise_except(int excepts) {
- // Since there are no traps, we just set the exception flags.
- uint32_t flags = FEnv::get_fflags();
- FEnv::set_fflags(flags | FEnv::exception_macro_to_bits(excepts));
- return 0;
-}
-
-LIBC_INLINE int get_round() {
- uint32_t rm = FEnv::get_frm();
- switch (rm) {
- case FEnv::TONEAREST:
- return FE_TONEAREST;
- case FEnv::DOWNWARD:
- return FE_DOWNWARD;
- case FEnv::UPWARD:
- return FE_UPWARD;
- case FEnv::TOWARDZERO:
- return FE_TOWARDZERO;
- default:
- return -1; // Error value.
- }
- return 0;
-}
-
-LIBC_INLINE int set_round(int mode) {
- uint32_t rm;
- switch (mode) {
- case FE_TONEAREST:
- rm = FEnv::TONEAREST;
- break;
- case FE_DOWNWARD:
- rm = FEnv::DOWNWARD;
- break;
- case FE_UPWARD:
- rm = FEnv::UPWARD;
- break;
- case FE_TOWARDZERO:
- rm = FEnv::TOWARDZERO;
- break;
- default:
- return -1; // To indicate failure
- }
- FEnv::set_frm(rm);
- return 0;
-}
-
-LIBC_INLINE int get_env(fenv_t *envp) {
- uint32_t *state = reinterpret_cast<uint32_t *>(envp);
- *state = FEnv::get_fcsr();
- return 0;
-}
-
-LIBC_INLINE int set_env(const fenv_t *envp) {
- if (envp == FE_DFL_ENV) {
- FEnv::set_frm(FEnv::TONEAREST);
- FEnv::set_fflags(0);
- return 0;
- }
- uint32_t status = *reinterpret_cast<const uint32_t *>(envp);
- // We have to do the masking to preserve the reserved bits.
- FEnv::set_fcsr((status & 0xFF) | (FEnv::get_fcsr() & 0xFFFFFF00));
- return 0;
-}
-
-} // namespace fputil
-} // namespace LIBC_NAMESPACE
-
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
diff --git a/libc/src/__support/FPUtil/sqrt.h b/libc/src/__support/FPUtil/sqrt.h
index 521ac4f14d4e528..3ba1bdf687a3eed 100644
--- a/libc/src/__support/FPUtil/sqrt.h
+++ b/libc/src/__support/FPUtil/sqrt.h
@@ -15,8 +15,8 @@
#include "x86_64/sqrt.h"
#elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
#include "aarch64/sqrt.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/sqrt.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/sqrt.h"
#else
#include "generic/sqrt.h"
diff --git a/libc/src/__support/OSUtil/linux/riscv64/CMakeLists.txt b/libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
similarity index 79%
rename from libc/src/__support/OSUtil/linux/riscv64/CMakeLists.txt
rename to libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
index 69540e3b45cbcfa..e271204f519820c 100644
--- a/libc/src/__support/OSUtil/linux/riscv64/CMakeLists.txt
+++ b/libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
@@ -1,5 +1,5 @@
add_header_library(
- linux_riscv64_util
+ linux_riscv_util
HDRS
syscall.h
DEPENDS
diff --git a/libc/src/__support/OSUtil/linux/riscv64/syscall.h b/libc/src/__support/OSUtil/linux/riscv/syscall.h
similarity index 93%
rename from libc/src/__support/OSUtil/linux/riscv64/syscall.h
rename to libc/src/__support/OSUtil/linux/riscv/syscall.h
index 53ee21d5cbdf103..4fc716f7d416c30 100644
--- a/libc/src/__support/OSUtil/linux/riscv64/syscall.h
+++ b/libc/src/__support/OSUtil/linux/riscv/syscall.h
@@ -1,4 +1,4 @@
-//===--------- inline implementation of riscv64 syscalls ----------* C++ *-===//
+//===--------- inline implementation of riscv syscalls ------------* C++ *-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
-#define LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
+#define LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
#include "src/__support/common.h"
@@ -107,4 +107,4 @@ LIBC_INLINE long syscall_impl(long number, long arg1, long arg2, long arg3,
#undef REGISTER_CONSTRAINT_5
#undef REGISTER_CONSTRAINT_6
-#endif // LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
+#endif // LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
diff --git a/libc/src/__support/OSUtil/linux/syscall.h b/libc/src/__support/OSUtil/linux/syscall.h
index 6c9559bb12ee4ea..2be3cefa906af1a 100644
--- a/libc/src/__support/OSUtil/linux/syscall.h
+++ b/libc/src/__support/OSUtil/linux/syscall.h
@@ -19,8 +19,8 @@
#include "aarch64/syscall.h"
#elif defined(LIBC_TARGET_ARCH_IS_ARM)
#include "arm/syscall.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/syscall.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/syscall.h"
#endif
namespace LIBC_NAMESPACE {
diff --git a/libc/src/__support/macros/properties/architectures.h b/libc/src/__support/macros/properties/architectures.h
index 2ece9c5728d6dad..c88956ff41148ec 100644
--- a/libc/src/__support/macros/properties/architectures.h
+++ b/libc/src/__support/macros/properties/architectures.h
@@ -45,7 +45,7 @@
#define LIBC_TARGET_ARCH_IS_AARCH64
#endif
-#if (defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_ARM))
+#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_ARM)
#define LIBC_TARGET_ARCH_IS_ANY_ARM
#endif
@@ -57,8 +57,7 @@
#define LIBC_TARGET_ARCH_IS_RISCV32
#endif
-#if (defined(LIBC_TARGET_ARCH_IS_RISCV64) || \
- defined(LIBC_TARGET_ARCH_IS_RISCV32))
+#if defined(LIBC_TARGET_ARCH_IS_RISCV64) || defined(LIBC_TARGET_ARCH_IS_RISCV32)
#define LIBC_TARGET_ARCH_IS_ANY_RISCV
#endif
diff --git a/libc/src/__support/threads/linux/thread.cpp b/libc/src/__support/threads/linux/thread.cpp
index 05fa0433ed86463..5c84266ee5d0eda 100644
--- a/libc/src/__support/threads/linux/thread.cpp
+++ b/libc/src/__support/threads/linux/thread.cpp
@@ -57,7 +57,7 @@ static constexpr unsigned CLONE_SYSCALL_FLAGS =
#ifdef LIBC_TARGET_ARCH_IS_AARCH64
#define CLONE_RESULT_REGISTER "x0"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
#define CLONE_RESULT_REGISTER "t0"
#elif defined(LIBC_TARGET_ARCH_IS_X86_64)
#define CLONE_RESULT_REGISTER "rax"
@@ -169,7 +169,7 @@ cleanup_thread_resources(ThreadAttributes *attrib) {
// is set to the stack pointer where start args are stored. So, we fetch
// from there.
return reinterpret_cast<uintptr_t>(__builtin_frame_address(1));
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
// The current frame pointer is the previous stack pointer where the start
// args are stored.
return reinterpret_cast<uintptr_t>(__builtin_frame_address(0));
@@ -306,7 +306,7 @@ int Thread::run(ThreadStyle style, ThreadRunner runner, void *arg, void *stack,
tls.tp // The thread pointer value for the new thread.
);
#elif defined(LIBC_TARGET_ARCH_IS_AARCH64) || \
- defined(LIBC_TARGET_ARCH_IS_RISCV64)
+ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
long register clone_result asm(CLONE_RESULT_REGISTER);
clone_result = LIBC_NAMESPACE::syscall_impl<long>(
SYS_clone, CLONE_SYSCALL_FLAGS, adjusted_stack,
diff --git a/libc/src/__support/threads/thread.h b/libc/src/__support/threads/thread.h
index 3fc3aef462a5b6f..acfe33879f8783f 100644
--- a/libc/src/__support/threads/thread.h
+++ b/libc/src/__support/threads/thread.h
@@ -41,7 +41,7 @@ union ThreadReturnValue {
#if (defined(LIBC_TARGET_ARCH_IS_AARCH64) || \
defined(LIBC_TARGET_ARCH_IS_X86_64) || \
- defined(LIBC_TARGET_ARCH_IS_RISCV64))
+ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV))
constexpr unsigned int STACK_ALIGNMENT = 16;
#endif
// TODO: Provide stack alignment requirements for other architectures.
diff --git a/libc/src/setjmp/riscv64/CMakeLists.txt b/libc/src/setjmp/riscv/CMakeLists.txt
similarity index 100%
rename from libc/src/setjmp/riscv64/CMakeLists.txt
rename to libc/src/setjmp/riscv/CMakeLists.txt
diff --git a/libc/src/setjmp/riscv64/longjmp.cpp b/libc/src/setjmp/riscv/longjmp.cpp
similarity index 97%
rename from libc/src/setjmp/riscv64/longjmp.cpp
rename to libc/src/setjmp/riscv/longjmp.cpp
index 0aed25e8125adce..034c31e723d6de6 100644
--- a/libc/src/setjmp/riscv64/longjmp.cpp
+++ b/libc/src/setjmp/riscv/longjmp.cpp
@@ -12,7 +12,7 @@
#include <setjmp.h>
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
#error "Invalid file include"
#endif
diff --git a/libc/src/setjmp/riscv64/setjmp.cpp b/libc/src/setjmp/riscv/setjmp.cpp
similarity index 97%
rename from libc/src/setjmp/riscv64/setjmp.cpp
rename to libc/src/setjmp/riscv/setjmp.cpp
index 826aa4021d3f4f6..04d6b5ec6ee5fab 100644
--- a/libc/src/setjmp/riscv64/setjmp.cpp
+++ b/libc/src/setjmp/riscv/setjmp.cpp
@@ -11,7 +11,7 @@
#include <setjmp.h>
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
#error "Invalid file include"
#endif
diff --git a/libc/startup/linux/riscv64/CMakeLists.txt b/libc/startup/linux/riscv/CMakeLists.txt
similarity index 100%
rename from libc/startup/linux/riscv64/CMakeLists.txt
rename to libc/startup/linux/riscv/CMakeLists.txt
diff --git a/libc/startup/linux/riscv64/start.cpp b/libc/startup/linux/riscv/start.cpp
similarity index 100%
rename from libc/startup/linux/riscv64/start.cpp
rename to libc/startup/linux/riscv/start.cpp
diff --git a/libc/test/src/fenv/enabled_exceptions_test.cpp b/libc/test/src/fenv/enabled_exceptions_test.cpp
index f9509202ab680ed..8bc2454faf9ea86 100644
--- a/libc/test/src/fenv/enabled_exceptions_test.cpp
+++ b/libc/test/src/fenv/enabled_exceptions_test.cpp
@@ -21,7 +21,8 @@
// This test enables an exception and verifies that raising that exception
// triggers SIGFPE.
TEST(LlvmLibcExceptionStatusTest, RaiseAndCrash) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \
+ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
// Few Arm HW implementations do not trap exceptions. We skip this test
// completely on such HW.
//
diff --git a/libc/test/src/fenv/feenableexcept_test.cpp b/libc/test/src/fenv/feenableexcept_test.cpp
index c891a552d40cfe2..41c1945368ed5a9 100644
--- a/libc/test/src/fenv/feenableexcept_test.cpp
+++ b/libc/test/src/fenv/feenableexcept_test.cpp
@@ -16,7 +16,8 @@
#include <fenv.h>
TEST(LlvmLibcFEnvTest, EnableTest) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \
+ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
// Few Arm HW implementations do not trap exceptions. We skip this test
// completely on such HW.
//
diff --git a/libc/test/src/fenv/feholdexcept_test.cpp b/libc/test/src/fenv/feholdexcept_test.cpp
index fe23ef23226ad40..735c7705ff49c6a 100644
--- a/libc/test/src/fenv/feholdexcept_test.cpp
+++ b/libc/test/src/fenv/feholdexcept_test.cpp
@@ -16,7 +16,8 @@
#include <fenv.h>
TEST(LlvmLibcFEnvTest, RaiseAndCrash) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \
+ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
// Few Arm HW implementations do not trap exceptions. We skip this test
// completely on such HW.
//
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