[libc-commits] [PATCH] D127571: Initiating a RISC-V port of llvm-libc

Mon Jun 13 10:42:34 PDT 2022

oceanfish81 added a comment.

In D127571#3576819 <https://reviews.llvm.org/D127571#3576819>, @sivachandra wrote:

> As @lntue has pointed out, the way start a new port would be to start with an `entrypoints.txt` and stick to default build. Default build is the mode in which one uses headers from the system libc. You can copy the entrypoints.txt for aarch64 and start peeling away entrypoints until you are able to build and test the remaining. In one of your messages, I see that you are hitting errors with fenv functions. Remove them from your entrypoints.txt as they are target CPU specific implementations. To keep it easy, start with only `string.h` and `math.h` functions.
>
> You will be able to work through all that and get it working eventually I would think. But, a more important question to address is the CI story. If you want to land any RISC-V configs/changes, we should have a CI bot connected to LLVM buildbot. It can be a chicken-and-egg problem as to which should go first - the bot or the first patch. We will let the patch go in first, but we will want a time-bound plan to put in place the CI bot before landing more patches. For more information on adding bots connected to LLVM buildbot, see this: https://llvm.org/docs/HowToAddABuilder.html

Still not able to patch:
https://reviews.llvm.org/D127575

Can someone explain LLVM_LIBC_CACHELINE_SIZE ?

================
Comment at: libc/cmake/modules/LLVMLibCArchitectures.cmake:21
+elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(riscv64|riscv)")
+  set(LIBC_TARGET_ARCHITECTURE_IS_POWER TRUE)
+  set(LIBC_TARGET_ARCHITECTURE "riscv")
----------------
tschuett wrote:
> This looks fishy. It is definitely not a Power Core.
Perhaps LIBC_TARGET_ARCHITECTURE_IS_RISCV makes sense here?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127571/new/

https://reviews.llvm.org/D127571