[flang-commits] [flang] [flang] Fix `getTypeSizeAndAlignment` for packed/tail-padded `RecordType` and `TRANSFER` gate (PR #220377)

[via flang-commits]

================
@@ -8904,10 +8904,15 @@ IntrinsicLibrary::genTransfer(mlir::Type resultType,
         (fir::isa_trivial(sourceType) ||
          mlir::isa<fir::RecordType>(sourceType)) &&
         fir::isa_trivial(moldType)) {
+      // Use storeSizeOnly=true so that tail padding in RecordType sources is
+      // excluded: TRANSFER reinterprets raw data bits, so the comparison must
+      // be against the store size (data bytes), not the allocation size.
       auto sourceSizeAndAlign = fir::getTypeSizeAndAlignment(
-          loc, sourceType, builder.getDataLayout(), builder.getKindMap());
+          loc, sourceType, builder.getDataLayout(), builder.getKindMap(),
+          /*storeSizeOnly=*/true);
----------------
MattPD wrote:

The separate API you described is not present at `c5025ead076c`. The code still calls `getTypeSizeAndAlignment(..., storeSizeOnly=true)`. The comment describing the returned value still equates it with `STORAGE_SIZE`.

For `t2` and `t1`, the `STORAGE_SIZE` intrinsic returns 64 and 128 bits, or 8 and 16 bytes, while `getTypeSizeAndAlignment(..., storeSizeOnly=true)` returns 5 and 10 bytes. Could the next push include the separate representation-width API and document its contract?


https://github.com/llvm/llvm-project/pull/220377