[flang-commits] [flang] [llvm] [NFC] Fix "intruction" typos. (PR #234930)
via flang-commits
flang-commits at lists.llvm.org
Fri Oct 23 05:55:35 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Paul Walker (paulwalker-arm)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/234930.diff
25 Files Affected:
- (modified) flang/lib/Optimizer/Dialect/FIROps.cpp (+1-1)
- (modified) llvm/include/llvm/MCA/CustomBehaviour.h (+1-1)
- (modified) llvm/lib/Analysis/TargetTransformInfo.cpp (+1-1)
- (modified) llvm/lib/CodeGen/InlineSpiller.cpp (+3-3)
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+1-1)
- (modified) llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp (+1-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp (+1-1)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (+1-1)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+1-1)
- (modified) llvm/lib/Target/X86/X86InstrInfo.h (+1-1)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (+1-1)
- (modified) llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp (+1-1)
- (modified) llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/licm-wwm.mir (+1-1)
- (modified) llvm/test/CodeGen/NVPTX/frameindex-lifetime.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/statepoint-split-single-block.ll (+1-1)
- (modified) llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll (+1-1)
- (modified) llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll (+1-1)
- (modified) llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll (+1-1)
- (modified) llvm/test/DebugInfo/assignment-tracking/X86/lower-offset-expression.ll (+1-1)
- (modified) llvm/test/MC/AArch64/armv8.1a-atomic.s (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll (+1-1)
- (modified) llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll (+1-1)
- (modified) llvm/utils/TableGen/Common/CodeGenInstruction.h (+1-1)
``````````diff
diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp
index 3d079afa0d1a51..57c71bd4ea013c 100644
--- a/flang/lib/Optimizer/Dialect/FIROps.cpp
+++ b/flang/lib/Optimizer/Dialect/FIROps.cpp
@@ -5505,7 +5505,7 @@ mlir::ParseResult fir::PrefetchOp::parse(mlir::OpAsmParser &parser,
result.addAttribute("cacheType", parser.getBuilder().getUnitAttr());
} else
return parser.emitError(parser.getCurrentLocation(),
- "Expected either intruction or data keyword");
+ "Expected either instruction or data keyword");
if (parser.parseComma())
return mlir::failure();
diff --git a/llvm/include/llvm/MCA/CustomBehaviour.h b/llvm/include/llvm/MCA/CustomBehaviour.h
index 73d960497e66a6..3a2029eb6b006e 100644
--- a/llvm/include/llvm/MCA/CustomBehaviour.h
+++ b/llvm/include/llvm/MCA/CustomBehaviour.h
@@ -83,7 +83,7 @@ class LLVM_ABI CustomBehaviour {
/// The return value of this method is the number of cycles that the
/// instruction needs to wait for.
/// It's safe to underestimate the number of cycles to wait for since these
- /// checks will be invoked again before the intruction gets dispatched.
+ /// checks will be invoked again before the instruction gets dispatched.
/// However, it's not safe (accurate) to overestimate the number of cycles
/// to wait for since the instruction will wait for AT LEAST that number of
/// cycles before attempting to be dispatched again.
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 607ac44783d73d..713420aab1338b 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -1078,7 +1078,7 @@ InstructionCost TargetTransformInfo::getArithmeticInstrCost(
ArrayRef<const Value *> Args, const Instruction *CtxI,
const TargetLibraryInfo *TLibInfo) const {
- // Use call cost for frem intructions that have platform specific vector math
+ // Use call cost for frem instructions that have platform specific vector math
// functions, as those will be replaced with calls later by SelectionDAG or
// ReplaceWithVecLib pass.
if (TLibInfo && Opcode == Instruction::FRem) {
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index bdcf13266ae5a3..61909969175dd2 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -515,7 +515,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
}
// If there is only 1 store instruction is required for spill, add it
- // to mergeable list. In X86 AMX, 2 intructions are required to store.
+ // to mergeable list. In X86 AMX, 2 instructions are required to store.
// We disable the merge for this case.
if (MIS.begin() == MII)
HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
@@ -1235,7 +1235,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
else if (Ops.front().second == 0) {
++NumSpills;
// If there is only 1 store instruction is required for spill, add it
- // to mergeable list. In X86 AMX, 2 intructions are required to store.
+ // to mergeable list. In X86 AMX, 2 instructions are required to store.
// We disable the merge for this case.
if (std::distance(MIS.begin(), MIS.end()) <= 1)
HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
@@ -1305,7 +1305,7 @@ void InlineSpiller::insertSpill(Register NewVReg, bool isKill,
dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill"));
++NumSpills;
// If there is only 1 store instruction is required for spill, add it
- // to mergeable list. In X86 AMX, 2 intructions are required to store.
+ // to mergeable list. In X86 AMX, 2 instructions are required to store.
// We disable the merge for this case.
if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1)
HSpiller.addToMergeableSpills(*Spill, StackSlot, Original);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 4978967c7cb112..56aaf28bab7f72 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -691,7 +691,7 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
assert(Other.isBundle() && "Expected that both instructions are bundles.");
MachineBasicBlock::const_instr_iterator I1 = getIterator();
MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
- // Loop until we analysed the last intruction inside at least one of the
+ // Loop until we analysed the last instruction inside at least one of the
// bundles.
while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
++I1;
diff --git a/llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp b/llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
index cc7de1112073a3..b53bfc89bd5e24 100644
--- a/llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
@@ -819,7 +819,7 @@ bool HexagonXQFloatGenerator::checkIfInputFromMult16(Register Reg) {
return llvm::is_contained(XQFPMult16, Def->getOpcode());
}
-// Generates sf = qf32 instruction or hf = qf16 intruction
+// Generates sf = qf32 instruction or hf = qf16 instruction
void HexagonXQFloatGenerator::createConvertInstr(MachineInstr *UseMI,
Register &NewR, Register &OldR,
bool is32bit) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp b/llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
index 351b80d91cd2e3..95fb64e4d0804d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
@@ -18,7 +18,7 @@
// This may result in significant changes to the control flow graph, e.g., when
// LLVM moves unreachable blocks to the end of the function. That's a problem
// in the context of divergent control flow, as `ptxas` uses the CFG to
-// determine divergent regions, and some intructions may not be executed
+// determine divergent regions, and some instructions may not be executed
// divergently.
//
// For example, `bar.sync` is not allowed to be executed divergently on Pascal
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 2d280b676606f2..20ac8dd47abd33 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13514,7 +13514,7 @@ static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) {
}
// Sign extend operand OpIdx if the value is not known to be sign extended.
-// Assumes the operand is a register. The flag IsByte controls which intruction
+// Assumes the operand is a register. The flag IsByte controls which instruction
// is used for the sign extension.
static void signExtendOperandIfUnknown(MachineInstr &MI, MachineBasicBlock *BB,
unsigned OpIdx, bool IsByte,
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index 694e9254636bed..215979d73d30b7 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -1379,7 +1379,7 @@ inline bool isKMergeMasked(uint64_t TSFlags) {
return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
}
-/// \returns true if the intruction needs a SIB.
+/// \returns true if the instruction needs a SIB.
inline bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode) {
// The SIB byte must be used if there is an index register.
if (IndexReg)
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index f0c83291d00d15..69a0bcd6efa74f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -9600,7 +9600,7 @@ bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
lookupAVX512(MI.getOpcode(), dom, ReplaceableCustomAVX512LogicInstrs);
assert(table && "Instruction not found in table?");
// Don't change integer Q instructions to D instructions and
- // use D intructions if we started with a PS instruction.
+ // use D instructions if we started with a PS instruction.
if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
Domain = 4;
MI.setDesc(get(table[Domain - 1]));
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index b8c1aa6b296905..8de07462b762e4 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -534,8 +534,8 @@ class X86InstrInfo final : public X86GenInstrInfo {
int64_t &Offset2) const override;
/// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
- /// make it capable of identifying ENDBR intructions and prevent it from being
- /// re-scheduled.
+ /// make it capable of identifying ENDBR instructions and prevent it from
+ /// being re-scheduled.
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index 30bca59ac09025..112118b7725f5a 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -20,7 +20,7 @@ def TruePredicate : Predicate<"true">;
// All instructions in the EVEX space can access the EGPR in their
// register/memory operands.
//
-// For the above intructions, the only difference in encoding is reflected in
+// For the above instructions, the only difference in encoding is reflected in
// the REX2/EVEX prefix when EGPR is used, i.e. the opcode and opcode name are
// unchanged. We don’t add new entries in TD, and instead we extend GPR with
// R16-R31 and make them allocatable only when the feature EGPR is available.
diff --git a/llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp b/llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
index bd111ebc09c847..c26829bc5a8614 100644
--- a/llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
+++ b/llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
@@ -626,7 +626,7 @@ void MemCmpExpansion::emitLoadCompareBlockMultipleLoads(unsigned BlockIndex,
}
}
-// This function creates the IR intructions for loading and comparing using the
+// This function creates the IR instructions for loading and comparing using the
// given LoadSize. It loads the number of bytes specified by LoadSize from each
// source of the memcmp parameters. It then does a subtract to see if there was
// a difference in the loaded values. If a difference is found, it branches
diff --git a/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll b/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
index f66245b8a1d37b..2ded69d7545594 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
@@ -2,7 +2,7 @@
; REQUIRES: asserts
; RUN: llc -verify-machineinstrs -max-registers-for-gc-values=256 -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
-; Verify that FixupStatepointCallerSaved pass uses correct intruction for spilling a register after copyprop
+; Verify that FixupStatepointCallerSaved pass uses correct instruction for spilling a register after copyprop
define dso_local ptr addrspace(1) @foo(ptr addrspace(1) %arg) gc "statepoint-example" personality ptr null {
; CHECK-LABEL: foo:
; CHECK: .Lfunc_begin0:
diff --git a/llvm/test/CodeGen/AMDGPU/licm-wwm.mir b/llvm/test/CodeGen/AMDGPU/licm-wwm.mir
index 4e5a41eead2b1b..2918a4cf5dfd8d 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-wwm.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-wwm.mir
@@ -2,7 +2,7 @@
# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -run-pass=early-machinelicm,si-wqm -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -passes=early-machinelicm,si-wqm -o - %s | FileCheck -check-prefix=GCN %s
-# Machine LICM may hoist an intruction from a WWM region, which will force SI-WQM pass
+# Machine LICM may hoist an instruction from a WWM region, which will force SI-WQM pass
# to create a second WWM region. This is an unwanted hoisting.
---
diff --git a/llvm/test/CodeGen/NVPTX/frameindex-lifetime.ll b/llvm/test/CodeGen/NVPTX/frameindex-lifetime.ll
index 9c564ffe7037ed..e7ae5d11d11b7e 100644
--- a/llvm/test/CodeGen/NVPTX/frameindex-lifetime.ll
+++ b/llvm/test/CodeGen/NVPTX/frameindex-lifetime.ll
@@ -37,7 +37,7 @@
;; This test is intended to verify that we don't crash when -opt-bisect-limit
;; is used in conjunction with lifetime markers. Previously, later passes
-;; would not handle these intructions correctly and relied on earlier passes
+;; would not handle these instructions correctly and relied on earlier passes
;; to remove them.
declare void @bar(ptr)
diff --git a/llvm/test/CodeGen/X86/statepoint-split-single-block.ll b/llvm/test/CodeGen/X86/statepoint-split-single-block.ll
index da02acdf432418..84b20c0f093bc6 100644
--- a/llvm/test/CodeGen/X86/statepoint-split-single-block.ll
+++ b/llvm/test/CodeGen/X86/statepoint-split-single-block.ll
@@ -61,7 +61,7 @@ entry:
br label %do_call
do_call:
- ; Basic block with two use intructions inside:
+ ; Basic block with two use instructions inside:
; copy to rdi as an argument to call and use in statepoint instruction as gc-live and deopt value.
%statepoint_token = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void (ptr addrspace(1))) @bar, i32 1, i32 0, ptr addrspace(1) %arg, i32 0, i32 0) [ "deopt"(ptr addrspace(1) %arg), "gc-live"(ptr addrspace(1) %arg) ]
%arg.reloc = call coldcc ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %statepoint_token, i32 0, i32 0)
diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
index ee7e9341ca59a3..b9e5e17a99ab55 100644
--- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
+++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
@@ -1,7 +1,7 @@
; RUN: opt -passes=sroa,verify -S %s -o - \
; RUN: | FileCheck %s --implicit-check-not="#dbg_"
-;; Check that the new slices of an alloca and memcpy intructions get dbg.assign
+;; Check that the new slices of an alloca and memcpy instructions get dbg.assign
;; intrinsics with the correct fragment info.
;;
;; Also check that the new dbg.assign intrinsics are inserted after each split
diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
index 73e954a27375f6..ffb009d2fef91a 100644
--- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
+++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
@@ -1,7 +1,7 @@
; RUN: opt -passes=sroa,verify -S %s -o - \
; RUN: | FileCheck %s --implicit-check-not="#dbg_"
-; Check that the new slices of an alloca and memset intructions get dbg.assign
+; Check that the new slices of an alloca and memset instructions get dbg.assign
; intrinsics with the correct fragment info. Ensure that only the
; value-expression gets fragment info; that the address-expression remains
; untouched.
diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
index 5ea3ae47424651..b460d4a013454b 100644
--- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
+++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
@@ -1,7 +1,7 @@
; RUN: opt -passes=sroa,verify -S %s -o - \
; RUN: | FileCheck %s --implicit-check-not="#dbg_"
-; Check that the new slices of an alloca and memset intructions get dbg.assign
+; Check that the new slices of an alloca and memset instructions get dbg.assign
; intrinsics with the correct fragment info. Ensure that only the
; value-expression gets fragment info; that the address-expression remains
; untouched.
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/lower-offset-expression.ll b/llvm/test/DebugInfo/assignment-tracking/X86/lower-offset-expression.ll
index 7ba6322babfef4..4e84853e28e7a1 100644
--- a/llvm/test/DebugInfo/assignment-tracking/X86/lower-offset-expression.ll
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/lower-offset-expression.ll
@@ -5,7 +5,7 @@
;; Here we have dbg.assign intrinsics with fragments (in the value-expression)
;; and address-expressions that involve arithmetic. The generated DBG_VALUE
-;; intructions needs a DIExpression that:
+;; instructions needs a DIExpression that:
;; a) Uses the fragment from the value-expression,
;; b) Uses the offset expression of the address-expression,
;; c) Has a DW_OP_deref appended.
diff --git a/llvm/test/MC/AArch64/armv8.1a-atomic.s b/llvm/test/MC/AArch64/armv8.1a-atomic.s
index bcfd3e7d166a5e..42781ce6e76695 100644
--- a/llvm/test/MC/AArch64/armv8.1a-atomic.s
+++ b/llvm/test/MC/AArch64/armv8.1a-atomic.s
@@ -75,7 +75,7 @@
//CHECK-ERROR: casal x0, w1, [x2]
//CHECK-ERROR: ^
- // LD<OP> intructions
+ // LD<OP> instructions
ldadda x0, x1, [x2]
ldclrl x0, x1, [x2]
ldeoral x0, x1, [x2]
@@ -95,7 +95,7 @@
//CHECK: ldumin w0, w1, [x2] // encoding: [0x41,0x70,0x20,0xb8]
//CHECK: ldsminb w2, w3, [x5] // encoding: [0xa3,0x50,0x22,0x38]
- // ST<OP> intructions: aliases to LD<OP>
+ // ST<OP> instructions: aliases to LD<OP>
stADDlb w0, [x2]
stclrlh w0, [x2]
steorl w0, [x2]
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll b/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
index b1ddc5402a5573..f028f1aeb49ddf 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -enable-vplan-native-path -S %s | FileCheck %s
-; Test that VPlan native path is able to widen call intructions like
+; Test that VPlan native path is able to widen call instructions like
; llvm.sqrt.* intrincis calls.
define void @widen_call_instruction(ptr noalias nocapture readonly %a.in, ptr noalias nocapture readonly %b.in, ptr noalias nocapture %c.out) {
diff --git a/llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll b/llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
index fd400632a59160..3daf2f422d3883 100644
--- a/llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
+++ b/llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
@@ -4,7 +4,7 @@
%struct.S = type { [4 x i32] }
; Check the second, third, and fourth basic blocks are folded into
-; the first basic block since each has one bonus intruction, which
+; the first basic block since each has one bonus instruction, which
; does not exceed the default bouns instruction threshold of 1.
define i1 @test1(i32 %0, i32 %1, i32 %2, i32 %3) {
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index a50b19099a6de9..4398048b0a385c 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -297,7 +297,7 @@ class CodeGenInstruction {
unsigned Variant);
// Is the specified operand in a generic instruction implicitly a pointer.
- // This can be used on intructions that use typeN or ptypeN to identify
+ // This can be used on instructions that use typeN or ptypeN to identify
// operands that should be considered as pointers even though SelectionDAG
// didn't make a distinction between integer and pointers.
bool isInOperandAPointer(unsigned i) const {
``````````
</details>
https://github.com/llvm/llvm-project/pull/234930
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