[flang-commits] [flang] [flang][debug] Name real and complex types by their kind (PR #232259)
Abid Qadeer via flang-commits
flang-commits at lists.llvm.org
Thu Oct 15 03:21:21 PDT 2026
https://github.com/abidh created https://github.com/llvm/llvm-project/pull/232259
Debug info names intrinsic types <type>(kind=N), with N taken from the size of the type in bytes. So real(kind=3) (bfloat16) is 2 bytes, so it was named real(kind=2) and became the same debug type as IEEE half real(kind=2).
Take the kind of real and complex types from mlirFloatTypeToKind instead. Logical types now use their own kind as well.
>From c7890a78126b070ba8625b4be859dabf20d5c6da Mon Sep 17 00:00:00 2001
From: Abid Qadeer <haqadeer at amd.com>
Date: Thu, 15 Oct 2026 11:06:38 +0100
Subject: [PATCH] [flang][debug] Name real and complex types by their kind
Debug info names intrinsic types <type>(kind=N), with N taken from the
size of the type in bytes. That isn't the kind for every real type:
real(kind=3) (bfloat16) is 2 bytes, so it was named real(kind=2) and
became the same debug type as IEEE half real(kind=2).
Take the kind of real and complex types from mlirFloatTypeToKind
instead. Logical types now use their own kind as well.
Co-authored-by: Cursor <cursoragent at cursor.com>
---
.../Transforms/DebugTypeGenerator.cpp | 21 ++++++++++++-------
flang/test/Transforms/debug-real-kind.fir | 20 ++++++++++++++++++
flang/test/Transforms/debug-vector-type.fir | 4 ++--
3 files changed, 35 insertions(+), 10 deletions(-)
create mode 100644 flang/test/Transforms/debug-real-kind.fir
diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
index 05b7992c28a542..c9c9794d6913f0 100644
--- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
+++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
@@ -83,14 +83,14 @@ static mlir::LLVM::DITypeAttr genBasicType(mlir::MLIRContext *context,
static mlir::StringAttr getBasicTypeName(mlir::MLIRContext *context,
llvm::StringRef baseName,
- unsigned bitSize) {
+ unsigned kind) {
std::ostringstream oss;
- oss << baseName.str() << "(kind=" << (bitSize / 8) << ")";
+ oss << baseName.str() << "(kind=" << kind << ")";
return mlir::StringAttr::get(context, oss.str());
}
static mlir::LLVM::DITypeAttr genPlaceholderType(mlir::MLIRContext *context) {
- return genBasicType(context, getBasicTypeName(context, "integer", 32),
+ return genBasicType(context, getBasicTypeName(context, "integer", /*kind=*/4),
/*bitSize=*/32, llvm::dwarf::DW_ATE_signed);
}
@@ -777,21 +777,25 @@ DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr,
mlir::MLIRContext *context = module.getContext();
if (Ty.isInteger()) {
unsigned bitWidth = Ty.getIntOrFloatBitWidth();
- return genBasicType(context, getBasicTypeName(context, "integer", bitWidth),
+ return genBasicType(context,
+ getBasicTypeName(context, "integer", bitWidth / 8),
bitWidth, llvm::dwarf::DW_ATE_signed);
} else if (mlir::isa<mlir::FloatType>(Ty)) {
unsigned bitWidth = Ty.getIntOrFloatBitWidth();
- return genBasicType(context, getBasicTypeName(context, "real", bitWidth),
+ unsigned kind = fir::mlirFloatTypeToKind(Ty).value_or(bitWidth / 8);
+ return genBasicType(context, getBasicTypeName(context, "real", kind),
bitWidth, llvm::dwarf::DW_ATE_float);
} else if (auto logTy = mlir::dyn_cast_if_present<fir::LogicalType>(Ty)) {
unsigned bitWidth = kindMapping.getLogicalBitsize(logTy.getFKind());
return genBasicType(
- context, getBasicTypeName(context, logTy.getMnemonic(), bitWidth),
+ context,
+ getBasicTypeName(context, logTy.getMnemonic(), logTy.getFKind()),
bitWidth, llvm::dwarf::DW_ATE_boolean);
} else if (auto cplxTy = mlir::dyn_cast_if_present<mlir::ComplexType>(Ty)) {
auto floatTy = mlir::cast<mlir::FloatType>(cplxTy.getElementType());
unsigned bitWidth = floatTy.getWidth();
- return genBasicType(context, getBasicTypeName(context, "complex", bitWidth),
+ unsigned kind = fir::mlirFloatTypeToKind(floatTy).value_or(bitWidth / 8);
+ return genBasicType(context, getBasicTypeName(context, "complex", kind),
bitWidth * 2, llvm::dwarf::DW_ATE_complex_float);
} else if (auto seqTy = mlir::dyn_cast_if_present<fir::SequenceType>(Ty)) {
return convertSequenceType(seqTy, fileAttr, scope, declOp);
@@ -838,7 +842,8 @@ DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr,
return convertVectorType(vecTy, fileAttr, scope, declOp);
} else if (mlir::isa<mlir::IndexType>(Ty)) {
unsigned bitWidth = llvmTypeConverter.getIndexTypeBitwidth();
- return genBasicType(context, getBasicTypeName(context, "integer", bitWidth),
+ return genBasicType(context,
+ getBasicTypeName(context, "integer", bitWidth / 8),
bitWidth, llvm::dwarf::DW_ATE_signed);
} else if (auto boxTy = mlir::dyn_cast_if_present<fir::BaseBoxType>(Ty)) {
auto elTy = boxTy.getEleTy();
diff --git a/flang/test/Transforms/debug-real-kind.fir b/flang/test/Transforms/debug-real-kind.fir
new file mode 100644
index 00000000000000..9d21ca8d216695
--- /dev/null
+++ b/flang/test/Transforms/debug-real-kind.fir
@@ -0,0 +1,20 @@
+// RUN: fir-opt --add-debug-info --mlir-print-debuginfo %s | FileCheck %s
+
+// Test that real and complex types are named by their kind, not their size.
+
+module {
+func.func private @real(%arg0: f16, %arg1: bf16, %arg2: f32, %arg3: f64, %arg4: f80, %arg5: f128)
+func.func private @cmplx(%arg0: complex<f16>, %arg1: complex<bf16>)
+}
+
+// CHECK-DAG: #[[F16:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=2)", sizeInBits = 16, encoding = DW_ATE_float>
+// CHECK-DAG: #[[BF16:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=3)", sizeInBits = 16, encoding = DW_ATE_float>
+// CHECK-DAG: #[[F32:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=4)", sizeInBits = 32, encoding = DW_ATE_float>
+// CHECK-DAG: #[[F64:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=8)", sizeInBits = 64, encoding = DW_ATE_float>
+// CHECK-DAG: #[[F80:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=10)", sizeInBits = 80, encoding = DW_ATE_float>
+// CHECK-DAG: #[[F128:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=16)", sizeInBits = 128, encoding = DW_ATE_float>
+// CHECK-DAG: #llvm.di_subroutine_type<{{.*}}types = #di_null_type, #[[F16]], #[[BF16]], #[[F32]], #[[F64]], #[[F80]], #[[F128]]>
+
+// CHECK-DAG: #[[CF16:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "complex(kind=2)", sizeInBits = 32, encoding = DW_ATE_complex_float>
+// CHECK-DAG: #[[CBF16:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "complex(kind=3)", sizeInBits = 32, encoding = DW_ATE_complex_float>
+// CHECK-DAG: #llvm.di_subroutine_type<{{.*}}types = #di_null_type, #[[CF16]], #[[CBF16]]>
diff --git a/flang/test/Transforms/debug-vector-type.fir b/flang/test/Transforms/debug-vector-type.fir
index 1ae2e88f2dbfa4..991edf8e60086d 100644
--- a/flang/test/Transforms/debug-vector-type.fir
+++ b/flang/test/Transforms/debug-vector-type.fir
@@ -2,8 +2,8 @@
module {
func.func private @foo1(%arg0: !fir.vector<20:bf16>)
-// CHECK-DAG: #[[F16:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=2)", sizeInBits = 16, encoding = DW_ATE_float>
-// CHECK-DAG: #llvm.di_composite_type<tag = DW_TAG_array_type, name = "vector real(kind=2) (20)", baseType = #[[F16]], flags = Vector, sizeInBits = 320, elements = #llvm.di_subrange<count = 20 : i64>>
+// CHECK-DAG: #[[BF16:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=3)", sizeInBits = 16, encoding = DW_ATE_float>
+// CHECK-DAG: #llvm.di_composite_type<tag = DW_TAG_array_type, name = "vector real(kind=3) (20)", baseType = #[[BF16]], flags = Vector, sizeInBits = 320, elements = #llvm.di_subrange<count = 20 : i64>>
func.func private @foo2(%arg0: !fir.vector<30:f32>)
// CHECK-DAG: #[[F32:.*]] = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "real(kind=4)", sizeInBits = 32, encoding = DW_ATE_float>
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